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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LMV831

LMV832

LMV834

SNOSAZ6C –AUGUST 2008–REVISED NOVEMBER 2015

LMV831 Single / LMV832 Dual / LMV834 Quad 3.3-MHz Low-Power CMOS, EMI-Hardened

Operational Amplifiers

1 Features

1• Unless Otherwise Noted, Typical Values at

TA= 25°C, V+= 3.3 V

• Supply Voltage 2.7 V to 5.5 V

• Supply Current (per Channel) 240 µA

• Input Offset Voltage 1-mV Maximum

• Input Bias Current 0.1 pA

• GBW 3.3 MHz

• EMIRR at 1.8 GHz 120 dB

• Input Noise Voltage at 1 kHz 12 nV/√Hz

• Slew Rate 2 V/µs

• Output Voltage Swing Rail-to-Rail

• Output Current Drive 30 mA

• Operating Ambient Temperature Range −40°C to

125°C

2 Applications

• Photodiode Preamps

• Piezoelectric Sensors

• Portable/Battery-Powered Electronic Equipment

• Filters and Buffers

• PDAs and Phone Accessories

3 Description

TI’s LMV83x devices are CMOS input, low-power

operation amplifier ICs, providing a low input bias

current, a wide temperature range of −40°C to 125°C,

and exceptional performance, making them robust

general-purpose parts. Additionally, the LMV83x are

EMI-hardened to minimize any interference, making

them ideal for EMI-sensitive applications.

The unity gain stable LMV83x feature 3.3-MHz of

bandwidth while consuming only 0.24 mA of current

per channel. These parts also maintain stability for

capacitive loads as large as 200 pF. The LMV83x

provide superior performance and economy in terms

of power and space usage.

This family of parts has a maximum input offset

voltage of 1 mV, a rail-to-rail output stage and an

input common-mode voltage range that includes

ground. Over an operating range from 2.7 V to 5.5 V,

the LMV83x provide a PSRR of 93 dB, and a CMRR

of 91 dB. The LMV831 is offered in the space-saving

5-pin SC70 package, the LMV832 in the 8-pin

VSSOP and the LMV834 is offered in the 14--in

TSSOP package.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

LMV831 SC70 (5) 1.25 mm × 2.00 mm

LMV832 VSSOP (8) 3.00 mm × 3.00 mm

LMV834 TSSOP (14) 4.40 mm × 5.00 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Typical Application

LMV831

LMV832

LMV834

SNOSAZ6C –AUGUST 2008–REVISED NOVEMBER 2015

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Product Folder Links: LMV831 LMV832 LMV834

Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics, 3.3 V ............................... 5

6.6 Electrical Characteristics, 5 V .................................. 7

6.7 Typical Characteristics............................................ 10

7 Detailed Description............................................ 17

7.1 Overview................................................................. 17

7.2 Functional Block Diagram....................................... 17

7.3 Feature Description................................................. 18

7.4 Device Functional Modes........................................ 20

8 Application and Implementation ........................ 23

8.1 Application Information............................................ 23

8.2 Typical Application.................................................. 23

9 Power Supply Recommendations...................... 25

10 Layout................................................................... 26

10.1 Layout Guidelines ................................................. 26

10.2 Layout Example .................................................... 26

11 Device and Documentation Support................. 27

11.1 Device Support .................................................... 27

11.2 Documentation Support ........................................ 27

11.3 Related Links ........................................................ 27

11.4 Community Resources.......................................... 27

11.5 Trademarks........................................................... 27

11.6 Electrostatic Discharge Caution............................ 28

11.7 Glossary................................................................ 28

12 Mechanical, Packaging, and Orderable

Information........................................................... 28

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (March 2013) to Revision C Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation

section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and

Mechanical, Packaging, and Orderable Information section.................................................................................................. 1

Changes from Revision A (March 2013) to Revision B Page

• Changed layout of National Semiconductor Data Sheet to TI format .................................................................................. 24

LMV831

LMV832

LMV834

www.ti.com

SNOSAZ6C –AUGUST 2008–REVISED NOVEMBER 2015

Product Folder Links: LMV831 LMV832 LMV834

5 Pin Configuration and Functions

DCK Package

5-Pin SC70

Top View DGK Package

8-Pin VSSOP

Top View

PW Package

14-Pin TSSOP

Top View

Pin Functions

PIN TYPE DESCRIPTION

NAME SC70 VSSOP TSSOP

IN+ 1 — — I Noninverting Input

IN– 3 — — I Inverting Input

IN A+— 3 3 I Noninverting Input, Channel A

IN A–— 2 2 I Inverting Input, Channel A

IN B+— 5 5 I Noninverting Input, Channel B

IN B–— 6 6 I Inverting Input, Channel B

IN C+— — 10 I Noninverting Input, Channel C

IN C–— — 9 I Inverting Input, Channel C

IN D+— — 12 I Noninverting Input, Channel D

IN D–— — 13 I Inverting Input, Channel D

OUT A — 1 1 O Output, Channel A

OUT B — 7 7 O Output, Channel B

OUT C — — 8 O Output, Channel C

OUT D — — 14 O Output, Channel D

OUTPUT 4 — — O Output

V+5 8 4 P Positive (highest) Power Supply

V–2 4 11 P Negative (lowest) Power Supply

LMV831

LMV832

LMV834

SNOSAZ6C –AUGUST 2008–REVISED NOVEMBER 2015

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Product Folder Links: LMV831 LMV832 LMV834

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(3) The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient

temperature is PD= (TJ(MAX) – TA) / RθJA. All numbers apply for packages soldered directly onto a PCB.

6 Specifications

6.1 Absolute Maximum Ratings

See (1)(2)

MIN MAX UNIT

VIN differential ±Supply Voltage V

Supply voltage (VS= V+– V−) 6 V

Voltage at input/output pins V−−0.4 V++ 0.4 V

Junction temperature(3) 150 °C

Soldering information Infrared or Convection (20 sec) 260 °C

Storage temperature, Tstg −65 150 °C

(1) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of

JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).

6.2 ESD Ratings VALUE UNIT

V(ESD) Electrostatic discharge(1) Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 ±2000 VCharged-device model (CDM), per JEDEC specification JESD22-C101 ±1000

Machine Model (MM) ±200

(1) The maximum power dissipation is a function of TJ(MAX),θJA, and TA. The maximum allowable power dissipation at any ambient

temperature is PD= (TJ(MAX) – TA)/ θJA . All numbers apply for packages soldered directly onto a PCB.

6.3 Recommended Operating Conditions MIN MAX UNIT

Temperature range(1) −40 125 °C

Supply voltage (VS= V+– V−) 2.7 5.5 V

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

(2) The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient

temperature is PD= (TJ(MAX) – TA) / RθJA. All numbers apply for packages soldered directly onto a PCB.

6.4 Thermal Information

THERMAL METRIC(1) LMV831 LMV832 LMV834

UNITDCK (SC70) DGK (VSSOP) PW (TSSOP)

5 PINS 8 PINS 14 PINS

RθJA Junction-to-ambient thermal resistance (2) 267.7 177.1 118.2 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 96.6 67.1 44.4 °C/W

RθJB Junction-to-board thermal resistance 48.8 97.5 60.5 °C/W

ψJT Junction-to-top characterization parameter 2.5 9.9 4.5 °C/W

ψJB Junction-to-board characterization parameter 47.9 96.1 59.9 °C/W

LMV831

LMV832

LMV834

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SNOSAZ6C –AUGUST 2008–REVISED NOVEMBER 2015

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(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very

limited self-heating of the device such that TJ= TA. No specification of parametric performance is indicated in the electrical tables under

conditions of internal self-heating where TJ> TA.

(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using

statistical quality control (SQC) method.

(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary

over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped

production material.

(4) The typical value is calculated by applying absolute value transform to the distribution, then taking the statistical average of the resulting

distribution.

(5) This parameter is specified by design and/or characterization and is not tested in production.

(6) The EMI Rejection Ratio is defined as EMIRR = 20log ( VRF_PEAK/ΔVOS).

(7) The specified limits represent the lower of the measured values for each output range condition.

6.5 Electrical Characteristics, 3.3 V

Unless otherwise specified, all limits are specified for at TA= 25°C, V+= 3.3 V, V−= 0 V, VCM = V+/2, and RL= 10 kΩto

V+/2.(1)

PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT

VOS Input offset voltage(4) TA= 25°C ±0.25 ±1 mV

–40°C ≤TA≤+125°C ±1.23

TCVOS Input offset voltage

temperature drift(4)(5)

LMV831,

LMV832 ±0.5 ±1.5 μV/°C

LMV834 ±0.5 ±1.7

IBInput bias current(5) TA= 25°C 0.1 10 pA

–40°C ≤TA≤+125°C 500

IOS Input offset current 1 pA

CMRR Common-mode

rejection ratio(4) 0.2 V ≤VCM ≤V+– 1.2 V TA= 25°C 76 91 dB

–40°C ≤TA≤+125°C 75

PSRR Power supply

rejection ratio(4) 2.7 V ≤V+≤5.5 V,

VOUT = 1 V TA= 25°C 76 93 dB

–40°C ≤TA≤+125°C 75

EMIRR EMI rejection ratio,

IN+ and IN–(6)

VRF_PEAK = 100 mVP(−20 dBP),

f = 400 MHz 80

VRF_PEAK = 100 mVP(−20 dBP),

f = 900 MHz 90

VRF_PEAK = 100 mVP(−20 dBP),

f = 1800 MHz 110

VRF_PEAK = 100 mVP(−20 dBP),

f = 2400 MHz 120

CMVR Input common-mode

voltage range CMRR ≥65 dB −0.1 2.1 V

AVOL Large signal

voltage gain(7)

RL= 2 kΩ,

VOUT = 0.15 V to 1.65 V,

VOUT = 3.15 V to 1.65 V

LMV831,

LMV832 102 121

LMV831,

LMV832,

–40°C ≤TA≤+125°C 102

LMV834 102 121

LMV834

–40°C ≤TA≤+125°C 102

RL= 10 kΩ,

VOUT = 0.1 V to 1.65 V,

VOUT = 3.2 V to 1.65 V

LMV831,

LMV832 104 126

LMV831,

LMV832,

–40°C ≤TA≤+125°C 104

LMV834 104 123

LMV834

–40°C ≤TA≤+125°C 103

LMV831

LMV832

LMV834

SNOSAZ6C –AUGUST 2008–REVISED NOVEMBER 2015

www.ti.com

Product Folder Links: LMV831 LMV832 LMV834

Electrical Characteristics, 3.3 V (continued)

Unless otherwise specified, all limits are specified for at TA= 25°C, V+= 3.3 V, V−= 0 V, VCM = V+/2, and RL= 10 kΩto

V+/2.(1)

PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT

(8) Number specified is the slower of positive and negative slew rates.

VOUT

Output voltage

swing high

RL= 2 kΩto V+/2

LMV831,

LMV832 29 36

mV from

either rail

LMV831,

LMV832,

–40°C ≤TA≤+125°C 43

LMV834 31 38

LMV834

–40°C ≤TA≤+125°C 44

RL= 10 kΩto V+/2

LMV831,

LMV832 6 8

LMV831,

LMV832,

–40°C ≤TA≤+125°C 9

LMV834 7 9

LMV834

–40°C ≤TA≤+125°C 10

Output voltage

swing low

R = 2 kΩto V+/2 TA= 25°C 25 34

–40°C ≤TA≤+125°C 43

RL= 10 kΩto V+/2 TA= 25°C 5 8

–40°C ≤TA≤+125°C 10

IOUT Output short circuit

current

Sourcing, VOUT = VCM,

VIN = 100 mV

LMV831,

LMV832 27 28

LMV831,

LMV832,

–40°C ≤TA≤+125°C 22

LMV834 24 28

LMV834

–40°C ≤TA≤+125°C 19

Sinking, VOUT = VCM,

VIN =−100 mV TA= 25°C 27 32

–40°C ≤TA≤+125°C 21

ISSupply current

LMV831 0.24 0.27

LMV831,

–40°C ≤TA≤+125°C 0.3

LMV832 0.46 0.51

LMV832,

–40°C ≤TA≤+125°C 0.58

LMV834 0.9 1

LMV834,

–40°C ≤TA≤+125°C 1.16

SR Slew rate(8) AV= +1, VOUT = 1 VPP,

10% to 90% 2 V/μs

GBW Gain bandwidth

product 3.3 MHz

ΦmPhase margin 65 deg

enInput referred

voltage noise f = 1 kHz 12 nV/√Hz

f = 10 kHz 10

inInput referred

current noise f = 1 kHz 0.005 pA/√Hz

ROUT Closed-loop

output impedance f = 2 MHz 500 Ω

LMV831

LMV832

LMV834

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SNOSAZ6C –AUGUST 2008–REVISED NOVEMBER 2015

Product Folder Links: LMV831 LMV832 LMV834

Electrical Characteristics, 3.3 V (continued)

Unless otherwise specified, all limits are specified for at TA= 25°C, V+= 3.3 V, V−= 0 V, VCM = V+/2, and RL= 10 kΩto

V+/2.(1)

PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT

CIN

Common-mode

input capacitance 15 pF

Differential-mode

input capacitance 20

THD+N Total harmonic

distortion + noise f = 1 kHz, AV= 1, BW ≥500 kHz 0.02%

(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very

limited self-heating of the device such that TJ= TA. No specification of parametric performance is indicated in the electrical tables under

conditions of internal self-heating where TJ> TA.

(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using

statistical quality control (SQC) method.

(3) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary

over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped

production material.

(4) The typical value is calculated by applying absolute value transform to the distribution, then taking the statistical average of the resulting

distribution.

(5) This parameter is specified by design and/or characterization and is not tested in production.

(6) The EMI Rejection Ratio is defined as EMIRR = 20log ( VRF_PEAK/ΔVOS).

6.6 Electrical Characteristics, 5 V

Unless otherwise specified, all limits are specified for at TA= 25°C, V+= 5 V, V−= 0 V, VCM = V+/2, and RL= 10 kΩto V+/2. (1)

PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT

VOS Input offset voltage(4) TA= 25°C ±0.25 ±1 mV

–40°C ≤TA≤+125°C ±1.23

TCVOS Input offset voltage

temperature drift(4)(5)

LMV831,

LMV832 ±0.5 ±1.5 μV/°C

LMV834 ±0.5 ±1.7

IBInput bias current(5) TA= 25°C 0.1 10 pA

–40°C ≤TA≤+125°C 500

IOS Input offset current 1 pA

CMRR Common-mode

rejection ratio(4) 0 V ≤VCM ≤V+−1.2 V TA= 25°C 77 93 dB

–40°C ≤TA≤+125°C 77

PSRR Power supply

rejection ratio(4) 2.7 V ≤V+≤5.5 V,

VOUT = 1 V TA= 25°C 76 93 dB

–40°C ≤TA≤+125°C 75

EMIRR EMI rejection ratio,

IN+ and IN–(6)

VRF_PEAK = 100 mVP(−20 dBP),

f = 400 MHz 80

VRF_PEAK = 100 mVP(−20 dBP),

f = 900 MHz 90

VRF_PEAK = 100 mVP(−20 dBP),

f = 1800 MHz 110

VRF_PEAK=100 mVP(−20 dBP),

f = 2400 MHz 120

CMVR Input common-mode

voltage range CMRR ≥65 dB –0.1 3.8 V

LMV831

LMV832

LMV834

SNOSAZ6C –AUGUST 2008–REVISED NOVEMBER 2015

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Product Folder Links: LMV831 LMV832 LMV834

Electrical Characteristics, 5 V (continued)

Unless otherwise specified, all limits are specified for at TA= 25°C, V+= 5 V, V−= 0 V, VCM = V+/2, and RL= 10 kΩto V+/2. (1)

PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT

(7) The specified limits represent the lower of the measured values for each output range condition.

AVOL Large signal voltage

gain(7)

RL= 2 kΩ,

VOUT = 0.15 V to 2.5 V,

VOUT = 4.85 V to 2.5 V

LMV831,

LMV832 107 127

LMV831,

LMV832,

–40°C ≤TA≤+125°C 106

LMV834 104 127

LMV834,

–40°C ≤TA≤+125°C 104

RL= 10 kΩ,

VOUT = 0.1 V to 2.5 V,

VOUT = 4.9 V to 2.5 V

LMV831,

LMV832 107 130

LMV831,

LMV832,

–40°C ≤TA≤+125°C 107

LMV834 105 127

LMV834,

–40°C ≤TA≤+125°C 104

VOUT

Output voltage

swing high

RL= 2 kΩto V+/2

LMV831,

LMV832 32 42

mV from

either rail

LMV831,

LMV832,

–40°C ≤TA≤+125°C 49

LMV834 35 45

LMV834,

–40°C ≤TA≤+125°C 52

RL= 10 kΩto V+/2

LMV831,

LMV832 6 9

LMV831,

LMV832,

–40°C ≤TA≤+125°C 10

LMV834 7 10

LMV834,

–40°C ≤TA≤+125°C 11

Output voltage

swing low

RL= 2 kΩto V+/2 TA= 25°C 27 43

–40°C ≤TA≤+125°C 52

RL= 10 kΩto V+/2 TA= 25°C 6 10

–40°C ≤TA≤+125°C 12

IOUT Output short

circuit current

Sourcing VOUT = VCM

VIN = 100 mV

LMV831,

LMV832 59 66

LMV831,

LMV832,

–40°C ≤TA≤+125°C 49

LMV834 57 63

LMV834,

–40°C ≤TA≤+125°C 45

Sinking VOUT = VCM

VIN =−100 mV

LMV831,

LMV832 50 64

LMV831,

LMV832,

–40°C ≤TA≤+125°C 41

LMV834 53 63

LMV834,

–40°C ≤TA≤+125°C 41

LMV831

LMV832

LMV834

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Electrical Characteristics, 5 V (continued)

Unless otherwise specified, all limits are specified for at TA= 25°C, V+= 5 V, V−= 0 V, VCM = V+/2, and RL= 10 kΩto V+/2. (1)

PARAMETER TEST CONDITIONS MIN(2) TYP(3) MAX(2) UNIT

(8) Number specified is the slower of positive and negative slew rates.

ISSupply current

LMV831 0.25 0.27

LMV831,

–40°C ≤TA≤+125°C 0.31

LMV832 0.47 0.52

LMV832,

–40°C ≤TA≤+125°C 0.6

LMV834 0.92 1.02

LMV834,

–40°C ≤TA≤+125°C 1.18

SR Slew rate(8) AV= +1, VOUT = 2 VPP,

10% to 90% 2 V/μs

GBW Gain bandwidth

product 3.3 MHz

ΦmPhase margin 65 deg

enInput referred

voltage noise f = 1 kHz 12 nV/√Hz

f = 10 kHz 10

inInput referred

current noise f = 1 kHz 0.005 pA/√Hz

ROUT Closed-loop

output impedance f = 2 MHz 500 Ω

CIN

Common-mode

input capacitance 14 pF

Differential-mode

input capacitance 20

THD+N Total harmonic

distortion + noise f = 1 kHz, AV= 1, BW ≥500 kHz 0.02%

VCM (V)

IB (pA)

-1

-2

-3

-4

-5

-1 0 1 2 3 4 5 6

3.3V

TA = 25°C

VOUT (V)

VOS (µV)

-2

-4

-6

0 1 2 3 4 5

V+= 5.0V, RL= 2k

VSUPPLY (V)

VOS (mV)

0.3

0.2

0.1

-0.1

-0.2

-0.3

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

-40°C

25°C

85°C

125°C

TEMPERATURE (°C)

VOS (µV)

200

150

100

-50

-100

-150

-200

-50 -25 0 25 50 75 100 125

3.3V

5.0V

VCM (V)

VOS (mV)

0.3

0.2

0.1

-0.1

-0.2

-0.3

-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

-40°C

25°C

85°C

125°C

V+= 3.3V

VCM (V)

VOS (mV)

0.3

0.2

0.1

-0.1

-0.2

-0.3

-0.5 0.5 1.5 2.5 3.5 4.5 5.5

-40°C

25°C

85°C 125°C

V+= 5.0V

LMV831

LMV832

LMV834

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Product Folder Links: LMV831 LMV832 LMV834

6.7 Typical Characteristics

At TA= 25°C, RL= 10 kΩ, V+= 3.3 V, V−= 0 V, Unless otherwise specified.

Figure 1. VOS vs VCM at V+= 3.3 V Figure 2. VOS vs VCM at V+= 5 V

Figure 3. VOS vs Supply Voltage Figure 4. VOS vs Temperature

Figure 5. VOS vs VOUT Figure 6. Input Bias Current vs VCM at 25°C

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

1.4

1.2

1.0

0.8

0.6

0.4

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

-40°C

25°C

85°C

125°C

TEMPERATURE (°C)

SUPPLY CURRENT (mA)

0.4

0.3

0.2

0.1

-50 -25 0 25 50 75 100 125

3.3V

5.0V

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

0.4

0.3

0.2

0.1

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

-40°C

25°C

85°C

125°C

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

0.4

0.3

0.2

0.1

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

-40°C

25°C

85°C

125°C

VCM (V)

IBIAS (pA)

-10

-20

-30

-40

-50

-1 0 1 2 3 4 5 6

3.3V

5.0V

TA = 85°C

VCM (V)

IBIAS (pA)

500

400

300

200

100

-100

-200

-300

-400

-500

-1 0 1 2 3 4 5 6

3.3V

5.0V

TA = 125°C

LMV831

LMV832

LMV834

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SNOSAZ6C –AUGUST 2008–REVISED NOVEMBER 2015

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Typical Characteristics (continued)

At TA= 25°C, RL= 10 kΩ, V+= 3.3 V, V−= 0 V, Unless otherwise specified.

Figure 7. Input Bias Current vs VCM at 85°C Figure 8. Input Bias Current vs VCM at 125°C

Figure 9. Supply Current vs Supply Voltage Single LMV831 Figure 10. Supply Current vs Supply Voltage Dual LMV832

Figure 11. Supply Current vs Supply Voltage Quad LMV834 Figure 12. Supply Current vs Temperature Single LMV831

SUPPLY VOLTAGE (V)

VOUT FROM RAIL HIGH (mV)

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

-40°C

25°C

85°C

125°C

RL= 2k

SUPPLY VOLTAGE (V)

VOUT FROM RAIL HIGH (mV)

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

-40°C

25°C

85°C

125°C

RL= 10k

SUPPLY VOLTAGE (V)

ISOURCE (mA)

100

102.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

-40°C

25°C

85°C

125°C

SUPPLY VOLTAGE (V)

ISINK (mA)

100

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

-40°C

25°C

85°C 125°C

TEMPERATURE (°C)

SUPPLY CURRENT (mA)

1.4

1.2

1.0

0.8

0.6

0.4

-50 -25 0 25 50 75 100 125

3.3V

5.0V

TEMPERATURE (°C)

SUPPLY CURRENT (mA)

0.7

0.6

0.5

0.4

0.3

-50 -25 0 25 50 75 100 125

3.3V

5.0V

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Typical Characteristics (continued)

At TA= 25°C, RL= 10 kΩ, V+= 3.3 V, V−= 0 V, Unless otherwise specified.

Figure 13. Supply Current vs Temperature Dual LMV832 Figure 14. Supply Current vs Temperature Quad LMV834

Figure 15. Sinking Current vs Supply Voltage Figure 16. Sourcing Current vs Supply Voltage

RL= 2 kΩ

Figure 17. Output Swing High vs Supply Voltage RL= 10 kΩ

Figure 18. Output Swing High vs Supply Voltage

PHASE (°)

FREQUENCY (Hz)

GAIN (dB)

10k 100k 1M 10M

-40°C

GAIN

PHASE

CL = 5 pF

25°C, 85°C, 125°C 100

-20

-40°C

25°C

85°C

125°C

PHASE (°)

FREQUENCY (Hz)

GAIN (dB)

10k 100k 1M 10M

PHASE

GAIN

5 pF

100 pF

5 pF

100 pF

100

-20

20 pF

50 pF

CL = 5 pF

20 pF

50 pF

100 pF

ILOAD (mA)

VOUT FROM RAIL (V)

2.0

1.6

1.2

0.8

0.4

-0.4

-0.8

-1.2

-1.6

-2.0 0 10 20 30 40 50 60 70 80

-40°C

125°C

V+= 5.0V

SOURCE

-40°C

125°C

SINK

ILOAD (mA)

VOUT FROM RAIL (V)

2.0

1.6

1.2

0.8

0.4

-0.4

-0.8

-1.2

-1.6

-2.0

0 5 10 15 20 25 30 35 40

-40°C

SOURCE

125°C

SOURCE

-40°C

125°C

SINK

V+= 3.3V

SUPPLY VOLTAGE (V)

VOUT FROM RAIL LOW (mV)

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

-40°C

25°C

85°C

125°C

RL= 2k

SUPPLY VOLTAGE (V)

VOUT FROM RAIL LOW (mV)

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

-40°C

25°C

85°C

125°C

RL= 10k

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Typical Characteristics (continued)

At TA= 25°C, RL= 10 kΩ, V+= 3.3 V, V−= 0 V, Unless otherwise specified.

RL= 2 kΩ

Figure 19. Output Swing Low vs Supply Voltage RL= 10 kΩ

Figure 20. Output Swing Low vs Supply Voltage

Figure 21. Output Voltage Swing vs Load Current at V+= 3.3

VFigure 22. Output Voltage Swing vs Load Current at V+= 5 V

Figure 23. Open-Loop Frequency Response vs Temperature Figure 24. Open-Loop Frequency Response vs Load

Conditions

1 µs/DIV

100 mV/DIV

f = 100 kHz

AV = +1

VIN = 500 mVPP

1 us/DIV

200 mV/DIV

f = 100 kHz

AV = +10

VIN = 100 mVPP

FREQUENCY (Hz)

CMRR (dB)

100

100 1k 10k 100k 1M 10M

V+ = 3.3V, 5.0V

AC CMRR

CMRR

FREQUENCY (Hz)

CHANNEL SEPARATION (dB)

160

140

120

100

1k 10k 100k 1M 10M

V+ = 3.3V, 5.0V

FREQUENCY (Hz)

PSRR (dB)

120

100

100 1k 10k 100k 1M 10M

3.3V

5.0V

3.3V

+PSRR

-PSRR

CLOAD (pF)

PHASE(°)

1 10 100 1000

3.3V

5.0V

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Typical Characteristics (continued)

At TA= 25°C, RL= 10 kΩ, V+= 3.3 V, V−= 0 V, Unless otherwise specified.

Figure 25. Phase Margin vs Capacitive Load Figure 26. PSRR vs Frequency

Figure 27. CMRR vs Frequency Figure 28. Channel Separation vs Frequency

Figure 29. Large Signal Step Response With Gain = 1 Figure 30. Large Signal Step Response With Gain = 10

VOUT (VPP)

THD + N (%)

0.1

0.01

0.001

1m 10m 100m 1 10

f = 1 kHz

BW = >500 kHz

V+= 3.3V

AV= 10x

AV= 1x

V+= 5.0V

FREQUENCY (Hz)

THD + N (%)

0.1

0.01

0.001

0.0001

10 100 1k 10k

BW = >500 kHz

VIN = 300 mVPP

VIN = 480 mVPP

VIN = 2.3 VPP

V+= 5.0V

AV= 10x

AV= 1x

V+= 3.3V

VIN = 3.8 VPP

SUPPLY VOLTAGE (V)

SLEW RATE (V/µs)

2.0

1.9

1.8

1.7

1.6

1.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

FALLING EDGE

RISING EDGE

AV= +1

CL= 5 pF

FREQUENCY (Hz)

NOISE (nV/ Hz)

100

110 100 1k 10k 100k

V+= 3.3V, 5.0V

1 µs/DIV

20 mV/DIV

f = 100 kHz

AV = +1

VIN = 100 mVPP

1 µs/DIV

20 mV/DIV

f = 100 kHz

AV = +10

VIN = 10 mVPP

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Typical Characteristics (continued)

At TA= 25°C, RL= 10 kΩ, V+= 3.3 V, V−= 0 V, Unless otherwise specified.

Figure 31. Small Signal Step Response With Gain = 1 Figure 32. Small Signal Step Response With Gain = 10

Figure 33. Slew Rate vs Supply Voltage Figure 34. Input Voltage Noise vs Frequency

Figure 35. THD+N vs Frequency Figure 36. THD+N vs Amplitude

RF INPUT PEAK VOLTAGE (dBVp)

EMIRRV_PEAK (dB)

-40 -30 -20 -10 0 10

-40°C

25°C

125°C

85°C

fRF = 2400 MHz

140

130

120

110

100

FREQUENCY (MHz)

EMIRR V_PEAK (dB)

10 100 1000 10000

125°C

85°C

-40°C

25°C

V+ = 3.3V, 5.0V

VPEAK = -20 dBVp

140

130

120

110

100

RF INPUT PEAK VOLTAGE (dBVp)

EMIRRV_PEAK (dB)

-40 -30 -20 -10 0 10

-40°C

25°C

125°C 85°C

fRF = 900 MHz

140

130

120

110

100

RF INPUT PEAK VOLTAGE (dBVp)

EMIRRV_PEAK (dB)

-40 -30 -20 -10 0 10

-40°C

25°C

125°C 85°C

fRF = 1800 MHz

140

130

120

110

100

FREQUENCY (Hz)

ROUT (:)

100 1k 10k 100k 1M 10M

AV = 10x

AV = 100x

AV = 1x

100

0.1

0.01

RF INPUT PEAK VOLTAGE (dBVp)

EMIRRV_PEAK (dB)

-40 -30 -20 -10 0 10

-40°C

25°C

125°C 85°C

fRF = 400 MHz

140

130

120

110

100

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Typical Characteristics (continued)

At TA= 25°C, RL= 10 kΩ, V+= 3.3 V, V−= 0 V, Unless otherwise specified.

Figure 37. ROUT vs Frequency Figure 38. EMIRR IN+ vs Power at 400 MHz

Figure 39. EMIRR IN+ vs Power at 900 MHz Figure 40. EMIRR IN+ vs Power at 1800 MHz

Figure 41. EMIRR IN+ vs Power at 2400 MHz Figure 42. EMIRR IN+ vs Frequency

OUT

V+

V–

IN –

IN +

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7 Detailed Description

7.1 Overview

The LMV831, LMV832, and LMV834 are operational amplifiers with excellent specifications, such as low offset,

low noise and a rail-to-rail output. The EMI hardening makes the LMV831, LMV832 or LMV834 a must for almost

all operational amplifier applications that are exposed to Radio Frequency (RF) signals such as the signals

transmitted by mobile phones or wireless computer peripherals. The LMV831, LMV832, and LMV834 will

effectively reduce disturbances caused by RF signals to a level that will be hardly noticeable. This again reduces

the need for additional filtering and shielding. Using this EMI resistant series of operational amplifiers will thus

reduce the number of components and space needed for applications that are affected by EMI, and will help

applications, not yet identified as possible EMI sensitive, to be more robust for EMI.

7.2 Functional Block Diagram

'VOS

VRF_PEAK

EMIRRVRF_PEAK= 20 log

RF SIGNAL

VOUT OPAMP

(AV = 1)

NO RF RF

VOS + VDETECTED

VOS

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7.3 Feature Description

7.3.1 Input Characteristics

The input common-mode voltage range of the LMV831, LMV832, and LMV834 includes ground, and can even

sense well below ground. The CMRR level does not degrade for input levels up to 1.2 V below the supply

voltage. For a supply voltage of 5 V, the maximum voltage that should be applied to the input for best CMRR

performance is thus 3.8 V.

When not configured as unity gain, this input limitation will usually not degrade the effective signal range. The

output is rail-to-rail and therefore will introduce no limitations to the signal range.

The typical offset is only 0.25 mV, and the TCVOS is 0.5 μV/°C, specifications close to precision operational

amplifiers.

7.3.2 EMIRR

With the increase of RF transmitting devices in the world, the electromagnetic interference (EMI) between those

devices and other equipment becomes a bigger challenge. The LMV831, LMV832, and LMV834 are EMI-

hardened operational amplifiers which are specifically designed to overcome electromagnetic interference. Along

with EMI-hardened operational amplifiers, the EMIRR parameter is introduced to unambiguously specify the EMI

performance of an operational amplifier. This section presents an overview of EMIRR. A detailed description on

this specification for EMI-hardened operational amplifiers can be found in AN-1698 (SNOA497).

The dimensions of an operational amplifier IC are relatively small compared to the wavelength of the disturbing

RF signals. As a result the operational amplifier itself will hardly receive any disturbances. The RF signals

interfering with the operational amplifier are dominantly received by the PCB and wiring connected to the

operational amplifier. As a result the RF signals on the pins of the operational amplifier can be represented by

voltages and currents. This representation significantly simplifies the unambiguous measurement and

specification of the EMI performance of an operational amplifier.

RF signals interfere with operational amplifiers through the non-linearity of the operational amplifier circuitry. This

non-linearity results in the detection of the so called out-of-band signals. The obtained effect is that the amplitude

modulation of the out-of-band signal is downconverted into the base band. This base band can easily overlap

with the band of the operational amplifier circuit. As an example Figure 43 depicts a typical output signal of a

unity-gain connected operational amplifier in the presence of an interfering RF signal. Clearly the output voltage

varies in the rhythm of the on-off keying of the RF carrier.

Figure 43. Offset Voltage Variation Due to an Interfering RF Signal

7.3.3 EMIRR Definition

To identify EMI-hardened operational amplifiers, a parameter is needed that quantitatively describes the EMI

performance of operational amplifiers. A quantitative measure enables the comparison and the ranking of

operational amplifiers on their EMI robustness. Therefore the EMI Rejection Ratio (EMIRR) is introduced. This

parameter describes the resulting input-referred offset voltage shift of an operational amplifier as a result of an

applied RF carrier (interference) with a certain frequency and level. The definition of EMIRR is given by

Equation 1:

In which

• VRF_PEAK is the amplitude of the applied un-modulated RF signal (V)

50:

RFin

22 pF

10 µF

100 pF

VDD

VSS

Out

100 pF

10 µF

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Feature Description (continued)

•ΔVOS is the resulting input-referred offset voltage shift (V) (1)

The offset voltage depends quadratically on the applied RF level, and therefore, the RF level at which the EMIRR

is determined should be specified. The standard level for the RF signal is 100 mVP. AN-1698 (SNOA497)

addresses the conversion of an EMIRR measured for an other signal level than 100 mVP. The interpretation of

the EMIRR parameter is straightforward. When two operational amplifiers have an EMIRR which differ by 20 dB,

the resulting error signals when used in identical configurations, differ by 20 dB as well. So, the higher the

EMIRR, the more robust the operational amplifier.

7.3.3.1 Coupling an RF Signal to the IN+ Pin

Each of the operational amplifier pins can be tested separately on EMIRR. In this section, the measurements on

the IN+ pin (which, based on symmetry considerations, also apply to the IN– pin) are discussed. In AN-1698

(SNOA497) the other pins of the operational amplifier are treated as well. For testing the IN+ pin the operational

amplifier is connected in the unity gain configuration. Applying the RF signal is straightforward as it can be

connected directly to the IN+ pin. As a result the RF signal path has a minimum of components that might affect

the RF signal level at the pin. The circuit diagram is shown in Figure 44. The PCB trace from RFIN to the IN+ pin

should be a 50-Ωstripline in order to match the RF impedance of the cabling and the RF generator. On the PCB

a 50-Ωtermination is used. This 50-Ωresistor is also used to set the bias level of the IN+ pin to ground level. For

determining the EMIRR, two measurements are needed: one is measuring the DC output level when the RF

signal is off; and the other is measuring the DC output level when the RF signal is switched on. The difference of

the two DC levels is the output voltage shift as a result of the RF signal. As the operational amplifier is in the

unity-gain configuration, the input referred offset voltage shift corresponds one-to-one to the measured output

voltage shift.

Figure 44. Circuit for Coupling the RF Signal to IN+

7.3.3.2 Cell Phone Call

The effect of electromagnetic interference is demonstrated in a set-up where a cell phone interferes with a

pressure sensor application. The application is shown in Figure 49.

This application needs two operational amplifiers and therefore a dual operational amplifier is used. The

operational amplifier configured as a buffer and connected at the negative output of the pressure sensor prevents

the loading of the bridge by resistor R2. The buffer also prevents the resistors of the sensor from affecting the

gain of the following gain stage. The operational amplifiers are placed in a single-supply configuration.

The experiment is performed on two different dual operational amplifiers: a typical standard operational amplifier

and the LMV832, EMI-hardened dual operational amplifier. A cell phone is placed on a fixed position a couple of

centimeters from the operational amplifiers in the sensor circuit.

-VOUT

VIN

RISO

TIME (0.5s/DIV)

VOUT (0.5V/DIV)

Typical Opamp

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Feature Description (continued)

When the cell phone is called, the PCB and wiring connected to the operational amplifiers receive the RF signal.

Subsequently, the operational amplifiers detect the RF voltages and currents that end up at their pins. The

resulting effect on the output of the second operational amplifier is shown in Figure 45.

Figure 45. Comparing EMI Robustness

The difference between the two types of dual operational amplifiers is clearly visible. The typical standard dual

operational amplifier has an output shift (disturbed signal) larger than 1 V as a result of the RF signal transmitted

by the cell phone. The LMV832, EMI-hardened operational amplifier does not show any significant disturbances.

This means that the RF signal will not disturb the signal entering the ADC when using the LMV832.

7.4 Device Functional Modes

7.4.1 Output Characteristics

As already mentioned the output is rail-to-rail. When loading the output with a 10-kΩresistor the maximum swing

of the output is typically 6 mV from the positive and negative rail.

The output of the LMV83x can drive currents up to 30 mA at 3.3 V and even up to 65 mA at 5 V.

The LMV83x can be connected as noninverting unity-gain amplifiers. This configuration is the most sensitive to

capacitive loading. The combination of a capacitive load placed at the output of an amplifier along with the output

impedance of the amplifier creates a phase lag, which reduces the phase margin of the amplifier. If the phase

margin is significantly reduced, the response will be under damped which causes peaking in the transfer and,

when there is too much peaking, the operational amplifier might start oscillating. The LMV83x can directly drive

capacitive loads up to 200 pF without any stability issues. In order to drive heavier capacitive loads, an isolation

resistor, RISO, should be used, as shown in Figure 46. By using this isolation resistor, the capacitive load is

isolated from the output of the amplifier, and hence, the pole caused by CLis no longer in the feedback loop. The

larger the value of RISO, the more stable the amplifier will be. If the value of RISO is sufficiently large, the feedback

loop will be stable, independent of the value of CL. However, larger values of RISO result in reduced output swing

and reduced output current drive.

Figure 46. Isolating Capacitive Load

A resistor value of around 150 Ωwould be sufficient. As an example some values are given in Table 1, for 5 V.

VIN

1 k:

LMV83x Buffer VOUT

R11

1 k:

R12

995:

V-

V+

10:

V+ BUFFER

V- BUFFER

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Device Functional Modes (continued)

Table 1. Resistor Values

CLOAD RISO

300 pF 165 Ω

400 pF 175 Ω

500 pF 185 Ω

7.4.2 CMRR Measurement

The CMRR measurement results may need some clarification. This is because different set-ups are used to

measure the AC CMRR and the DC CMRR.

The DC CMRR is derived from ΔVOS versus ΔVCM. This value is stated in the tables, and is tested during

production testing. The AC CMRR is measured with the test circuit shown in Figure 47.

Figure 47. AC CMRR Measurement Set-Up

The configuration is largely the usually applied balanced configuration. With potentiometer P1, the balance can

be tuned to compensate for the DC offset in the DUT. The main difference is the addition of the buffer. This

buffer prevents the open-loop output impedance of the DUT from affecting the balance of the feedback network.

Now the closed-loop output impedance of the buffer is a part of the balance. As the closed-loop output

impedance is much lower, and by careful selection of the buffer also has a larger bandwidth, the total effect is

that the CMRR of the DUT can be measured much more accurately. The differences are apparent in the larger

measured bandwidth of the AC CMRR.

One artifact from this test circuit is that the low frequency CMRR results appear higher than expected. This is

because in the AC CMRR test circuit the potentiometer is used to compensate for the DC mismatches. So,

mainly AC mismatch is all that remains. Therefore, the obtained DC CMRR from this AC CMRR test circuit tends

to be higher than the actual DC CMRR based on DC measurements.

The CMRR curve in Figure 48 shows a combination of the AC CMRR and the DC CMRR.

FREQUENCY (Hz)

CMRR (dB)

100

100 1k 10k 100k 1M 10M

V+ = 3.3V, 5.0V

AC CMRR

CMRR

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Figure 48. CMRR Curve

5 NŸ

100 

2.4 k

V+

ADC

VOUT

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LMV83x family of amplifiers is specified for operation from 2.7 V to 5.5 V (±1.35 V to ±2.25 V). Parameters

that can exhibit significant variance with regard to operating voltage or temperature are presented in the Typical

Characteristics.

8.2 Typical Application

Figure 49. Pressure Sensor Application

8.2.1 Design Requirements

The LMV83x can be used for pressure sensor applications. Because of their low power the LMV83x are ideal for

portable applications, such as blood pressure measurement devices, or portable barometers. This example

describes a universal pressure sensor that can be used as a starting point for different types of sensors and

applications.

The pressure sensor used in this example functions as a Wheatstone bridge. The value of the resistors in the

bridge change when pressure is applied to the sensor. This change of the resistor values will result in a

differential output voltage, depending on the sensitivity of the sensor and the applied pressure.

8.2.2 Detailed Design Procedure

The difference between the output at full-scale pressure and the output at zero pressure is defined as the span of

the pressure sensor. A typical value for the span is 100 mV. A typical value for the resistors in the bridge is 5 kΩ.

Loading of the resistor bridge could result in incorrect output voltages of the sensor. Therefore the selection of

the circuit configuration, which connects to the sensor, should take into account a minimum loading of the

sensor.

The configuration shown in Figure 49 is simple, and is very useful for the read out of pressure sensors. With two

operational amplifiers in this application, the dual LMV832 fits very well. The operational amplifier configured as a

buffer and connected at the negative output of the pressure sensor prevents the loading of the bridge by resistor

R2. The buffer also prevents the resistors of the sensor from affecting the gain of the following gain stage. Given

the differential output voltage VSof the pressure sensor, the output signal of this operational amplifier

configuration, VOUT, equals Equation 2:

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

4500 4600 4700 4800 4900 5000 5100 5200 5300 5400 5500

Output Voltage (V)

Rx Resistance (Ohms)

C001

=VOUT VS

VDD 1R

2×

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Typical Application (continued)

(2)

To align the pressure range with the full range of an ADC, the power supply voltage and the span of the pressure

sensor are needed. For this example a power supply of 5 V is used and the span of the sensor is 100 mV. When

a 100-Ωresistor is used for R2, and a 2.4-kΩresistor is used for R1, the maximum voltage at the output is 4.95

V and the minimum voltage is 0.05 V. This signal is covering almost the full input range of the ADC. Further

processing can take place in the microprocessor following the ADC.

8.2.3 Application Curve

Figure 50 shows the resulting output voltage as RXis varied between 4.5 kΩand 5.5 kΩ.

Figure 50. Output Voltage vs RX

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9 Power Supply Recommendations

For proper operation, the power supplies must be properly decoupled. For decoupling the supply lines, TI

recommends that 10-nF capacitors be placed as close as possible to the operational amplifier power supply pins.

For single-supply, place a capacitor between V+ and V−supply leads. For dual supplies, place one capacitor

between V+ and ground, and one capacitor between V– and ground.

CAUTION

Supply voltages larger than 6 V can permanently damage the device.

The internal RFI filters shunt the received EMI energy to the supply pins. To maximize the effectiveness of the

built-in EMI filters, the power supply pin bypassing should have a low impedance, low inductance path to RF

ground.

The normally suggested 0.1-µF and larger capacitors tend to be inductive over the effective frequency range of

the EMI filters and are not effective at filtering high frequencies (> 50 MHz). Capacitors with high self-resonance

frequencies near the GHz range should be placed at the supply pins. This can be accomplished with small (0805

or less) 10 pF to 100 pF SMT ceramic capacitors placed directly at the supply pins to a solid RF ground. These

capacitors will provide a direct AC path for the high-frequency EMI to ground. These capacitors are in addition to,

and not a replacement for, the recommended low-frequency supply bypassing capacitors.

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10 Layout

10.1 Layout Guidelines

• Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as close to

the device as possible. A single bypass capacitor from V+ to ground is applicable for single-supply

applications.

• For single-supply, place a capacitor between V+and V−.

• For dual supplies, place one capacitor between V+and the board ground, and a second capacitor between

ground and V−.

• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and operational

amplifier itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power

sources local to the analog circuitry.

• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective

methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.

A ground plane helps distribute heat and reduces EMI noise pick-up. Make sure to physically separate digital

and analog grounds paying attention to the flow of the ground current. For more detailed information refer to

Circuit Board Layout Techniques,SLOA089.

• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as

possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular

as opposed to in parallel with the noisy trace.

• Place the external components as close to the device as possible, keeping RF and RG close to the inverting

input minimizes parasitic capacitance.

• Keep the length of input traces as short as possible. Always remember that the input traces are the most

sensitive part of the circuit.

Even with the LMV83x inherent hardening against EMI, TI still recommends to keep the input traces short and as

far as possible from RF sources. Then the RF signals entering the chip are as low as possible, and the

remaining EMI can be, almost, completely eliminated in the chip by the EMI reducing features of the LMV83x.

10.2 Layout Example

Figure 51. SOT-23 Noninverting Layout Example

LMV831

LMV832

LMV834

www.ti.com

SNOSAZ6C –AUGUST 2008–REVISED NOVEMBER 2015

Product Folder Links: LMV831 LMV832 LMV834

11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support

LMV831 PSPICE Model, SNOM049

LMV832 PSPICE Model, SNOM050

LMV834 PSPICE Model, SNOM038

TINA-TI SPICE-Based Analog Simulation Program, http://www.ti.com/tool/tina-ti

TI Filterpro Software, http://www.ti.com/tool/filterpro

DIP Adapter Evaluation Module, http://www.ti.com/tool/dip-adapter-evm

TI Universal Operational Amplifier Evaluation Module, http://www.ti.com/tool/opampevm

11.2 Documentation Support

11.2.1 Related Documentation

For related documentation, see the following:

•AN-028 Feedback Plots Define Op Amp AC Performance,SBOA015

•Circuit Board Layout Techniques,SLOA089

•Capacitive Load Drive Solution using an Isolation Resistor,TIPD128

•Handbook of Operational Amplifier Applications,SBOA092

•EMI-Hardened Operational Amplifiers for Robust Circuit Design,SNOA817

•AN-1698 A Specification for EMI Hardened Operational Amplifiers,SNOA497

•AN-1867 EMIRR Evaluation Boards for LMV831/LMV832/LMV834 (Boards are no longer available - for

reference only), SNOA530

11.3 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

Table 2. Related Links

PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL

DOCUMENTS TOOLS &

SOFTWARE SUPPORT &

COMMUNITY

LMV831 Click here Click here Click here Click here Click here

LMV832 Click here Click here Click here Click here Click here

LMV834 Click here Click here Click here Click here Click here

11.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.5 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

LMV831

LMV832

LMV834

SNOSAZ6C –AUGUST 2008–REVISED NOVEMBER 2015

www.ti.com

Product Folder Links: LMV831 LMV832 LMV834

11.6 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.7 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM

www.ti.com 2-Oct-2015

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LMV831MG/NOPB ACTIVE SC70 DCK 5 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AFA

LMV831MGE/NOPB ACTIVE SC70 DCK 5 250 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AFA

LMV831MGX/NOPB ACTIVE SC70 DCK 5 3000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AFA

LMV832MM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AU5A

LMV832MME/NOPB ACTIVE VSSOP DGK 8 250 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AU5A

LMV832MMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AU5A

LMV834MT/NOPB ACTIVE TSSOP PW 14 94 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV834

LMV834MTX/NOPB ACTIVE TSSOP PW 14 2500 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 LMV834

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

PACKAGE OPTION ADDENDUM

www.ti.com 2-Oct-2015

Addendum-Page 2

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LMV831MG/NOPB SC70 DCK 5 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3

LMV831MGE/NOPB SC70 DCK 5 250 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3

LMV831MGX/NOPB SC70 DCK 5 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3

LMV832MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

LMV832MME/NOPB VSSOP DGK 8 250 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

LMV832MMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

LMV834MTX/NOPB TSSOP PW 14 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 6-Nov-2015

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LMV831MG/NOPB SC70 DCK 5 1000 210.0 185.0 35.0

LMV831MGE/NOPB SC70 DCK 5 250 210.0 185.0 35.0

LMV831MGX/NOPB SC70 DCK 5 3000 210.0 185.0 35.0

LMV832MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0

LMV832MME/NOPB VSSOP DGK 8 250 210.0 185.0 35.0

LMV832MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0

LMV834MTX/NOPB TSSOP PW 14 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 6-Nov-2015

Pack Materials-Page 2

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Click to View Pricing, Inventory, Delivery & Lifecycle Information:

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LMV831MG/NOPB LMV831MGE/NOPB LMV831MGX/NOPB