1
Data sheet acquired from Harris Semiconductor
SCHS055
Features
• High-Voltage Types (20V Rating)
• CD4070B - Quad Exclusive-OR Gate
• CD4077B - Quad Exclusive-NOR Gate
• Medium Speed Operation
-t
PHL, tPLH = 65ns (Typ) at VDD = 10V, CL = 50pF
• 100% Tested for Quiescent Current at 20V
• Standardized Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
• Maximum Input Current of 1µA at 18V Over Full
Package Temperature Range
- 100nA at 18V and 25oC
• Noise Margin (Over Full Package Temperature Range)
- 1V at VDD = 5V, 2V at VDD = 10V, 2.5V at VDD = 15V
• Meets All Requirements of JEDEC Standard No. 13B,
“Standard Specifications for Description of ‘B’ Series
CMOS Devices
Applications
• Logical Comparators
• Adders/Subtractors
• Parity Generators and Checkers
Description
The Harris CD4070B contains four independent Exclusive-
OR gates. The Harris CD4077B contains four independent
Exclusive-NOR gates.
The CD4070B and CD4077B provide the system designer
with a means for direct implementation of the Exclusive-OR
and Exclusive-NOR functions, respectively.
Pinouts
Ordering Information
PART NUMBER TEMP.
RANGE (oC) PACKAGE PKG.
NO.
CD4070BE -55 to 125 14 Ld PDIP E14.3
CD4077BE -55 to 125 14 Ld PDIP E14.3
CD4070BF -55 to 125 14 Ld CERDIP F14.3
CD4077BF -55 to 125 14 Ld CERDIP F14.3
CD4070BM -55 to 125 14 Ld SOIC M14.15
CD4077BM -55 to 125 14 Ld SOIC M14.15
CD4070B
(PDIP, CERDIP, SOIC)
TOP VIEW
CD4077B
(PDIP, CERDIP, SOIC)
TOP VIEW
A
B
J = A ⊕ B
K = C ⊕ D
C
D
VSS
VDD
H
G
M = G ⊕ H
L = E ⊕ F
F
E
1
2
3
4
5
6
7
14
13
12
11
10
9
8
A
B
J = A ⊕ B
K = C ⊕ D
C
D
VSS
VDD
H
G
M = G ⊕ H
L = E ⊕ F
F
E
1
2
3
4
5
6
7
14
13
12
11
10
9
8
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1998
CD4070B,
CD4077B
CMOS Quad Exclusive-OR
and Exclusive-NOR Gate
File Number 910.1
[ /Title
(CD40
70B,
CD407
7B)
/
Sub-
j
ect
(CMO
SQuad
Exclu-
sive-
OR
and
Exclu-
sive-
NOR
Gate)
/
Autho
r ()
/
Key-
words
(Har-
ris
Semi-
con-
ductor,
CD400
0,
metal
gate,
CMOS
, pdip,
cerdip,
mil,
January 1998
2
Functional Diagrams
CD4070B CD4077B
A
B
C
D
E
F
G
H
1
2
5
6
8
9
12
13
3
4
10
11
J = A ⊕ B
K = C⊕ D
M = G ⊕H
L = E ⊕ F
VSS = 7
VDD = 14
J
K
L
M
A
B
C
D
E
F
G
H
1
2
5
6
8
9
12
13
3
4
10
11
J=A
⊕ B
K = C ⊕ D
M = G ⊕ H
L=E
⊕ F
J
K
L
M
FIGURE 1. SCHEMATIC DIAGRAM FOR CD4070B
(1 OF 4 IDENTICAL GATES)
CD4070B TRUTH TABLE (1 OF 4 GATES)
ABJ
000
101
011
110
NOTE:
1 = High Level
0 = Low Level
J = A ⊕B
VDD
VSS
VSS
VDD
VDD
VSS
VSS
VDD
p
n
p
n
p
np
p
n
p
n
J
3(4,10,11)
B†
2(5,9,12)
A†
1(6,8,13)
†INPUTS PROTECTED
BY CMOS PROTECTION
NETWORK
FIGURE 2. SCHEMATIC DIAGRAM FOR CD4077B
(1 OF 4 IDENTICAL GATES)
CD4077B TRUTH TABLE (1 OF 4 GATES)
ABJ
001
100
010
111
NOTE:
1 = High Level
0 = Low Level
J = A ⊕B
VDD
VSS
VSS
VDD
VDD
VSS
VSS
VDD
p
n
p
n
p
n
p
n
p
n
J
3(4,10,11)
B†
2(5,9,12)
A†
1(6,8,13)
†INPUTS PROTECTED
BY CMOS PROTECTION
NETWORK
n
CD4070B, CD4077B
3
Absolute Maximum Ratings Thermal Information
DC Supply Voltage Range (VDD) . . . . . . . . . . . . . . . . . -0.5V to 20V
Input Voltage Range, All Inputs . . . . . . . . . . . . . . -0.5V to VDD 0.5V
DC Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .± 10mA
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range (Typical) . . . . . . . . . . . . . . . . . . . . 3V to 18V
Thermal Resistance (Typical, Note 1) θJA (oC/W) θJC (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . 90 N/A
CERDIP Package . . . . . . . . . . . . . . . . 95 38
SOIC Package. . . . . . . . . . . . . . . . . . . 175 N/A
Maximum Junction Temperature (Hermetic P ac kage or Die)175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER
CONDITIONS
LIMITS AT INDICATED TEMPERATURES (oC)
UNITS-55 -40 85 125
25
VO
(V) VIN
(V) VDD
(V) MIN TYP MAX
Quiescent Device Current
IDD Max - 0, 5 5 0.25 0.25 7.5 7.5 - 0.01 0.25 µA
- 0, 10 10 0.5 0.5 15 15 - 0.01 0.5 µA
- 0, 15 15 1 1 30 30 - 0.01 1 µA
- 0, 20 20 5 5 150 150 - 0.02 5 µA
Output Low (Sink) Current
IOL Min 0.4 0, 5 5 0.64 0.61 0.42 0.36 0.51 1 - mA
0.5 0, 10 10 1.6 1.5 1.1 0.9 1.3 2.6 - mA
1.5 0, 15 15 4.2 4 2.8 2.4 3.4 6.8 - mA
Output High (Source) Current
IOH Min 4.6 0, 5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - mA
2.5 0, 5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 - mA
9.5 0, 10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 - mA
13.5 0, 15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 - mA
Output Voltage: Low Level,
VOL Max - 0, 5 5 0.05 0.05 0.05 0.05 - 0 0.05 V
- 0, 10 10 0.05 0.05 0.05 0.05 - 0 0.05 V
- 0, 15 15 0.05 0.05 0.05 0.05 - 0 0.05 V
Output Voltage: High Level,
VOH Min - 0, 5 5 4.95 4.95 4.95 4.95 4.95 5 - V
- 0, 10 10 9.95 9.95 9.95 9.95 9.95 10 - V
- 0, 15 15 14.95 14.95 14.95 14.95 14.95 15 - V
Input Low Voltage,
VIL Max 0.5, 4.5 - 5 1.5 1.5 1.5 1.5 - - 1.5 V
1, 9-103333--3V
1.5, 13.5 - 15 4444--4V
Input High Voltage,
VIH Min 0.5, 4.5 - 5 3.5 3.5 3.5 3.5 3.5 - - V
1, 9-1077777--V
1.5, 13.5 - 15 11 11 11 11 11 - - V
Input Current, IIN Max - 0, 18 18 ±0.1 ±0.1 ±1±1-±10-5 ±0.1 µA
CD4070B, CD4077B
4
AC Electrical Specifications TA = 25oC, Input tr, tf = 20ns, CL = 50pF, RL = 200kΩ
PARAMETER SYMBOL
TEST CONDITIONS LIMITS ON ALL TYPES
UNITSVDD (V) TYP MAX
Propagation Delay Time tPHL, tPLH 5 140 280 ns
10 65 130 ns
15 50 100 ns
Transition Time tTHL, tTLH 5 100 200 ns
10 50 100 ns
15 40 80 ns
Input Capacitance CIN Any Input 5 7.5 pF
Typical Performance Curves
FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
TA = 25oC
GATE TO SOURCE VOLTAGE (VGS) = 15V
10V
5V
30
25
20
15
10
5
00 5 10 15
IOL, OUTPUT LOW (SINK) CURRENT (mA)
VDS, DRAIN TO SOURCE VOLTAGE (V)
TA = 25oC
GATE TO SOURCE VOLTAGE (VGS) = 15V
10V
5V
15
12.5
10
7.5
5
2.5
00 5 10 15
IOL, OUTPUT LOW (SINK) CURRENT (mA)
VDS, DRAIN TO SOURCE VOLTAGE (V)
TA = 25oC
GATE TO SOURCE VOLTAGE (VGS) = -5V
-10V
-15V
-5
-10
-15
-20
-25
-30
0
0-5-10-15
IOH, OUTPUT HIGH (SOURCE) CURRENT (mA)
VDS, DRAIN TO SOURCE VOLTAGE (V)
TA = 25oC
GATE TO SOURCE VOLTAGE (VGS) = -5V
-10V
-15V -15
-10
-5
0
0-5-10-15
IOH, OUTPUT HIGH (SINK) CURRENT (mA)
VDS, DRAIN TO SOURCE VOLTAGE (V)
CD4070B, CD4077B
5
FIGURE 7. TYPICAL TRANSITION TIME AS A FUNCTION OF
LOAD CAPACITANCE FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A
FUNCTION OF LOAD CAPACITANCE
FIGURE 9. TYPICAL PROPAGATION DELAY TIME AS A
FUNCTION OF SUPPLY VOLTAGE FIGURE 10. TYPICAL DYNAMIC POWER DISSIPATION AS A
FUNCTION OF INPUT FREQUENCY
Typical Performance Curves
(Continued)
TA = 25oC
SUPPLY VOLTAGE (VDD) = 5V
10V
15V
200
150
100
50
00204060
t
THL, tTLH, TRANSITION TIME (ns)
CL, LOAD CAPACITANCE (pF)
80 100 110
TA = 25oC
SUPPLY VOLTAGE (VDD) = 5V
10V
15V
300
200
100
00204060
t
PHL, tPLH, PROPAGATION DELAY TIME (ns)
CL, LOAD CAPACITANCE (pF)
80 100
TA = 25oC
300
200
100
00 5 10 15
tPHL, tPLH, PROPAGATION DELAY TIME (ns)
VDD, SUPPLY VOLTAGE (V)
20
LOAD CAPACITANCE CL = 50pF
TA = 25oC
SUPPLY VOLTAGE (V
DD
) = 15V
5V
103
102
10
1
10-1
10-1 110
102
PD, POWER DISSIPATION (µW)
fI, INPUT FREQUENCY (kHz) 103104
104
105
10V
CL = 50pF
CL = 15pF
10V
CD4070B, CD4077B
6
CD4070B, CD4077B
Dual-In-Line Plastic Packages (PDIP)
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 1 2 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1 B0.010 (0.25) C A
MBS
e
D
D1
A
A2
L
A1
-A-
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and are measured with the leads constrained to be perpen-
dicular to datum .
7. eB and eC are measured at the lead tips with the leads uncon-
strained. eC must be zero or greater.
8. B1maximumdimensionsdonotincludedambarprotrusions.Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 -
1.14mm).
eA-C-
E14.3 (JEDEC MS-001-AA ISSUE D)
14 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.15 1.77 8
C 0.008 0.014 0.204 0.355 -
D 0.735 0.775 18.66 19.68 5
D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA0.300 BSC 7.62 BSC 6
eB- 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N14 149
Rev. 0 12/93
7
CD4070B, CD4077B
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
NOTES:
1. Indexarea:Anotch or a pinoneidentificationmarkshallbe locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
bbb C A - B
S
c
Q
L
A
SEATING
BASE
D
PLANE
PLANE
-D-
-A-
-C-
-B-
α
D
E
S1
b2 b
A
e
M
c1
b1
(c)
(b)
SECTION A-A
BASE
LEAD FINISH
METAL
eA/2
A
M
S S
ccc C A - B
MD
SSaaa C A - B
MD
SS
eA
F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A)
14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.200 - 5.08 -
b 0.014 0.026 0.36 0.66 2
b1 0.014 0.023 0.36 0.58 3
b2 0.045 0.065 1.14 1.65 -
b3 0.023 0.045 0.58 1.14 4
c 0.008 0.018 0.20 0.46 2
c1 0.008 0.015 0.20 0.38 3
D - 0.785 - 19.94 5
E 0.220 0.310 5.59 7.87 5
e 0.100 BSC 2.54 BSC -
eA 0.300 BSC 7.62 BSC -
eA/2 0.150 BSC 3.81 BSC -
L 0.125 0.200 3.18 5.08 -
Q 0.015 0.060 0.38 1.52 6
S1 0.005 - 0.13 - 7
α90o105o90o105o-
aaa - 0.015 - 0.38 -
bbb - 0.030 - 0.76 -
ccc - 0.010 - 0.25 -
M - 0.0015 - 0.038 2 , 3
N14 148
Rev. 0 4/94
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