SN74CBT3253
DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER
SCDS018O − MAY 1995 − REVISED JANUARY 2004
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
DTTL-Compatible Input Levels
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1OE
S1
1B4
1B3
1B2
1B1
1A
GND
VCC
2OE
S0
2B4
2B3
2B2
2B1
2A
D, DB, DBQ, OR PW PACKAGE
(TOP VIEW)
RGY PACKAGE
(TOP VIEW)
116
89
2
3
4
5
6
7
15
14
13
12
11
10
2OE
S0
2B4
2B3
2B2
2B1
S1
1B4
1B3
1B2
1B1
1A
1OE
2A V
GND
CC
description/ordering information
The SN74CBT3253 is a dual 1-of-4 high-speed TTL-compatible FET multiplexer/demultiplexer. The low
on-state resistance of the switch allows connections to be made with minimal propagation delay.
1OE, 2OE, S0, and S1 select the appropriate B output for the A-input data.
ORDERING INFORMATION
TAPACKAGEORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QFN − RGY Tape and reel SN74CBT3253RGYR CU253
SOIC D
Tube SN74CBT3253D
CBT3253
SOIC − D Tape and reel SN74CBT3253DR CBT3253
−40°C to 85°CSSOP − DB Tape and reel SN74CBT3253DBR CU253
40 C
to
85 C
SSOP (QSOP) − DBQ Tape and reel SN74CBT3253DBQR CU253
TSSOP PW
Tube SN74CBT3253PW
CU253
TSSOP − PW Tape and reel SN74CBT3253PWR CU253
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
INPUTS
FUNCTION
1OE 2OE S1 S0 FUNCTION
X H X X Disconnect 1A and 2A
HX X X Disconnect 1A and 2A
LL L L 1A to 1B1 and 2A to 2B1
LL L H 1A to 1B2 and 2A to 2B2
LL H L 1A to 1B3 and 2A to 2B3
L L H H 1A to 1B4 and 2A to 2B4
Copyright © 2004, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN74CBT3253
DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER
SCDS018O − MAY 1995 − REVISED JANUARY 2004
2POST OFFICE BOX 655303 DALLAS, TEXAS 75265
logic diagram (positive logic)
2B1
1B1
2A
1A
S0
S1
1OE
2OE
1B2
1B3
1B4
2B2
2B3
2B4
7
9
14
2
1
15
6
5
4
3
10
11
12
13
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous channel current 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IK (VI/O < 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): DB package 82°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): DBQ package 90°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): PW package 108°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): RGY package 39°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-5.
SN74CBT3253
DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER
SCDS018O − MAY 1995 − REVISED JANUARY 2004
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
MIN MAX UNIT
VCC Supply voltage 4 5.5 V
VIH High-level control input voltage 2 V
VIL Low-level control input voltage 0.8 V
TAOperating free-air temperature −40 85 °C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYPMAX UNIT
VIK VCC = 4.5 V, II = −18 mA −1.2 V
IIVCC = 5 V, VI = 5.5 V or GND ±1μA
ICC VCC = 5.5 V, IO = 0, VI = VCC or GND 3μA
ΔICCControl inputs VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND 2.5 mA
CiControl inputs VI = 3 V or 0 3.5 pF
C
A port
V3Vor0
OE V
10
pF
Cio(OFF) B port VO = 3 V or 0, OE = VCC 4pF
II = 64 mA 5 7
ron§VCC = 4.5 V VI = 0 II = 30 mA 5 7 Ω
ron
VCC
4.5
V
VI = 2.4 V, II = 15 mA 10 15
Ω
All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
§Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is determined
by the lower voltage of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
VCC = 4 V VCC = 5 V
± 0.5 V UNIT
PARAMETER
(INPUT) (OUTPUT) MIN MAX MIN MAX
UNIT
tpdA or B B or A 0.35 0.25 ns
tpd SA or B 6.6 1.6 6.2 ns
t
S
AorB
7.1 1.3 6.3
ns
ten OE A or B 7.3 1.4 6.4 ns
t
S
AorB
7.9 1.1 7.4
ns
tdis OE
A or B 7.3 2.3 7 ns
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
SN74CBT3253
DUAL 1-OF-4 FET MULTIPLEXER/DEMULTIPLEXER
SCDS018O − MAY 1995 − REVISED JANUARY 2004
4POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
7 V
Open
GND
500 Ω
500 Ω
TEST
tpd
tPLZ/tPZL
tPHZ/tPZH
S1
Open
7 V
Open
tPLH tPHL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
3 V
0 V
VOH
VOL
0 V
VOL + 0.3 V
VOH − 0.3 V
0 V
Input
3 V
3.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 Ω, tr 2.5 ns, tf 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN74CBT3253D ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74CBT3253DBLE OBSOLETE SSOP DB 16 TBD Call TI Call TI
SN74CBT3253DBQR ACTIVE SSOP DBQ 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN74CBT3253DBQRE4 ACTIVE SSOP DBQ 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN74CBT3253DBQRG4 ACTIVE SSOP DBQ 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN74CBT3253DBR ACTIVE SSOP DB 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74CBT3253DBRE4 ACTIVE SSOP DB 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74CBT3253DBRG4 ACTIVE SSOP DB 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74CBT3253DE4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74CBT3253DG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74CBT3253DR ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74CBT3253DRE4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74CBT3253DRG4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74CBT3253PW ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74CBT3253PWE4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74CBT3253PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74CBT3253PWLE OBSOLETE TSSOP PW 16 TBD Call TI Call TI
SN74CBT3253PWR ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN74CBT3253PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74CBT3253PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74CBT3253RGYR ACTIVE VQFN RGY 16 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN74CBT3253RGYRG4 ACTIVE VQFN RGY 16 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74CBT3253DBR SSOP DB 16 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
SN74CBT3253DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN74CBT3253PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74CBT3253RGYR VQFN RGY 16 3000 330.0 12.4 3.8 4.3 1.5 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74CBT3253DBR SSOP DB 16 2000 367.0 367.0 38.0
SN74CBT3253DR SOIC D 16 2500 333.2 345.9 28.6
SN74CBT3253PWR TSSOP PW 16 2000 367.0 367.0 35.0
SN74CBT3253RGYR VQFN RGY 16 3000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2