General Description
The MAX20751 PMBus™-compliant multiphase
master IC, with extensive status and parameter monitor-
ing, is capable of driving up to four smart-slave integrated
power devices.
Utilizing Maxim’s smart-slave ICs, the device
provides a high-density and flexible solution that can be
tailored to a range of power loads used in commu-
nication equipment. Proprietary-coupled inductors,
recommended to reduce the effective inductor value with-
out excessive ripple current, results in improved transient
response and reduction in the number of output capaci-
tors required.
The device incorporates current reporting, tempera-
ture monitoring, fault detection, and PMBus support.
Overcurrent and overtemperature faults are detected
by the individual smart slaves and faults communicated
through the master IC. The highest junction temperature
is reported, both before and after smart-slave regulation.
The device features an integrated switching regulator
that can optionally be used to supply the VDD rail for the
master controller and smart-slave devices to reduce the
power-rail requirements and simplify the regulator design.
Applications
●Communication, Networking, Servers, and Storage
Equipment
• ASICs
• Microprocessor Chipsets
• Memory VDDQ
• Other High-Current Digital ICs
Benets and Features
●Increased Power Density with Fewer External
Components Needed
• Scalable, Multiphase Solution
• Compatibility with Coupled Inductors Enables Fast
Transient Response and Reduced COUT
• Integrated Internal Switching Regulator to Power
Smart Slaves
●Optimized Component Performance and Efficiency
with Reduced Design-In Time
• PMBus-Compliant Interface for Telemetry and
Power Management
• Field-Programmable Memory to Allow Storage of
Desired Conguration Parameters
• Fault Logging
●Comprehensive System and IC Self-Protection
Features Promote Increased Power-Supply Reliability
• Overcurrent and Overtemperature
• Boost Voltage UVLO
• VX Short to Ground or VDDH Detection
• Phase-Current Steering for Thermal Balancing
●36-Pin (6mm x 6mm) QFN Package
Ordering Information appears at end of data sheet.
19-7080; Rev 2; 3/15
PMBus is a trademark of SMIF, Inc.
Figure 1. Basic Application Circuit
PWM1
PWM3
PWM4
PWM2
ISENSE1
ISENSE2
ISENSE3
ISENSE4
TS_FAULTB VOUT
SENSE_P
SENSE_N
MAX20751
Power
Management
COntroller
PMBus
Smart
Slave
Smart
Slave
Smart
Slave
Smart
Slave
MAX20751 Multiphase Master with PMBus Interface
and Internal Buck Converter
EVALUATION KIT AVAILABLE
VDD33 Supply Voltage...............................................-0.3V to +4V
VIN_UV, VR_ON and PWRGD Pins.........................-0.3V to +4V
VDD Supply Voltage ...............................................-0.3V to +2.5V
PVX to PGND...........................................-0.6V to VDD33 + 0.6V
PMBus Pins (PMD, PMC, ALERTB).........................-0.3V to +6V
SENSE_N .....................................................-0.3V to VDD +0.3V
SENSE_P.................................................................-0.3V to +4V
R_REF, MRAMP, R_SELx, PWMx, TS_FAULTB, ISENSEx,
A1_OUT, A2_x, A2B_OUT, A3_x ............... -0.3 to VDD + 0.3V
Junction Temperature (TJ) ................ ...............................+150°C
Storage Temperature Range..............................-65°C to +150°C
Peak Reflow Temperature................................................+260°C
VDD33 Supply Voltage ..................................... +2.97V to +3.63V
VDD Supply Voltage ........................................+1.71V to +1.98V
VIN_UV, VR_ON and PWRGD ............................-0.1V to +3.6V
PMBus Pins (PMD, PMC, ALERTB) ....................-0.1V to +5.5V
SENSE_N ............................................................. -0.1V to +0.2V
SENSE_P .............................................................-0.1V to +2.5V
Junction Temperature Range (TJ).......................-40°C to +125°C
TQFN
Junction-to-Case Thermal Resistance (θJC) ..............1.7°C/W
Electrical Characteristics
(VDD = 1.71V to 1.98V, VDD33 = 3.3V ±10%, TJ = +25°C, unless otherwise noted.)
This product is completely Halogen-free and Pb-free, employing SnAgCu solder balls. The product is RoHS compliant with an -e1 termina-
tion finish and is compatible with both SnPb and Pb-free soldering operations. The product is MSL classified at peak reflow temperatures
that meet JEDEC JSTD-020.
MAX20751 Multiphase Master with PMBus Interface
and Internal Buck Converter
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PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SUPPLY VOLTAGES AND CURRENTS
Supply Voltage Range VDD If external VDD supply is used 1.71 1.86 1.98 V
Supply Current IDD PWM not switching (Note 2) 14 17 20 mA
3.3V Supply Voltage Range VDD33 2.97 3.30 3.63 V
3.3V Supply Current IDD33
No load, internal integrated
switcher disabled, PMBus idle
(Note 2)
24 130 µA
VDD UVLO (UNDERVOLTAGE LOCKOUT)
Supply Voltage Undervoltage-
Lockout Rising Threshold VDD_UVLO_RIS (Note 2) 1.62 1.66 V
Supply Voltage Undervoltage-
Lockout Falling Threshold VDD_UVLO_FAL (Note 2) 1.58 1.60 V
VDD33 UVLO
3.3V Supply Voltage Undervoltage-
Lockout Rising Threshold VDD33_UV_RIS (Note 2) 2.90 2.95 V
3.3V Supply Voltage Undervoltage-
Lockout Falling Threshold VDD33_UV_FAL (Note 2) 2.80 2.85 V
Absolute Maximum Ratings
Operating Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Thermal Characteristics
Electrical Characteristics (continued)
(VDD = 1.71V to 1.98V, VDD33 = 3.3V ±10%, TJ = +25°C, unless otherwise noted.)
MAX20751 Multiphase Master with PMBus Interface
and Internal Buck Converter
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PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VIN UVLO (USING VIN_UV PIN)
VIN_UV Rising Threshold VIN_UVRIS (Note 2) 0.380 0.390 V
VIN_UV Falling Threshold VIN_UVFAL (Note 2) 0.318 0.328 V
Delay from VIN_UV UVLO to
System Shutdown tdVIN_UV_UVLO 125 275 ns
INTEGRATED INTERNAL SWITCHER
Output Valley Voltage VOUT_IIS 1.86 V
Current Driving Capability IOUT_IIS Tested at L = 2.2μH, tON = 1.30μs 300 mA
Switcher Peak Inductor Current ILPK_IIS 1.5 A
High-Side Switch On-Time tON_IIS Default 1.30μs (Notes 1, 2)
0.52 0.65 0.78
µs
1.04 1.30 1.56
1.52 1.90 3.28
2.20 2.75 3.30
VNOM (NOMINAL OUTPUT VOLTAGE AFTER STARTUP, WITHOUT DROOP)
Output Voltage Range
VNOM
Programmable through R_SEL
or PMBus, direct feedback of
VOUT to SENSE_P (Notes 1, 2)
0.500 1.520 V
Resolution (Note 2) 5 mV
DC Accuracy 1V ≤ VNOM ≤ 1.52V (Note 2) -0.5 +0.5 %
0.5V ≤ VNOM < 1V (Note 2) -5 +5 mV
VID Set Point (VOUT Fine-
Adjustment Voltage) VOUT_FINE_ADJ Programmable with PMBus,
default is 0.00mV. (Notes 1, 2)
3.25 3.75 4.25
mV
2.00 2.50 3.00
0.75 1.25 1.75
-0.50 0.00 +0.50
-1.75 -1.25 -0.75
-3.00 -2.50 -2.00
-4.25 -3.75 -3.25
-5.50 -5.00 -4.50
SWITCHING FREQUENCY
Nominal Switching Frequency
Range fSW Programmable through R_SEL or
PMBus (Note 1) 300 800 kHz
Switching Frequency Tolerance fSW_TOL (Note 2) -10 +10 %
OUTPUT-VOLTAGE STARTUP SLEW RATES
Output-Voltage Slew Rate After
Initial Jump from 0V SVOUT Programmable through R_SEL or
PMBus (Note 1)
0.5
mV/μs
1.25
2.5
5
Electrical Characteristics (continued)
(VDD = 1.71V to 1.98V, VDD33 = 3.3V ±10%, TJ = +25°C, unless otherwise noted.).
MAX20751 Multiphase Master with PMBus Interface
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PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
R_REF
Reference Voltage for R_REF VR_REF (Note 2) 0.79 0.80 0.81 V
AMPLIFIER A1
A1 Amplier Closed-Loop
Differential Gain A1DM (Note 2) 2.17 2.19 2.23 V/V
Error-Amplier Closed-Loop BW CLBW 7 15 MHz
Positive Sense Line Current ISENSE_P VSENSE_N grounded (Note 2) 90 µA
Negative Sense Line Current ISENSE_N VSENSE_P grounded (Note 2) -90 µA
AMPLIFIER A2
Amplier Closed-Loop Gain of A2
with feedback capacitor C2 shorted AV2 Set through external R (Note 1) 1 4 V/V
A2 Amplier Open-Loop Gain AOL2 60 dB
Closed-Loop Bandwidth CLBW_A2 Gain = 2 10 MHz
AMPLIFIER A2B
A2B Amplier Closed-Loop Gain ADM 1 V/V
Closed-Loop Bandwidth CLBW_A2B 11 MHz
AMPLIFIER A3
A3 Amplier Open-Loop Gain AOL3 60 dB
Closed-Loop Bandwidth CLBW_A3 Gain = 2 10 MHz
MODULATOR RAMP RATE
Ramp-Rate Programming Range MRAMP Program through R at MRAMP pin
(Note 1) 0.4 2 V/µs
OVERCURRENT PROTECTION (OCP)
Positive Current Limit (Sustaining),
Programmed Through RDES POCP Voltage across RDES referred to
VCM, 4-phase system (Notes 1, 2) -0.658 -0.598 -0.538 V
Negative Current Limit (Sustaining) NOCP Voltage across RDES referred to
VCM, 4-phase system (Note 2) 0.157 0.183 0.209 V
Positive Current-Limit Tolerance ILIM_TOL Not including the external resistor
tolerance (1%) (Note 2) -10 +10 %
OVERVOLTAGE PROTECTION (OVP)
Tracking OVP Threshold Voltage
Above VNOM (Rising) V_TRA_OVP
(Note 2) 205 217
mV
Tracking OVP Threshold Voltage
(Falling) (Note 2) 187 199
Tracking OVP Blanking Time from
the End of an IDAC Transition t_BL_OVP 90 µs
Electrical Characteristics (continued)
(VDD = 1.71V to 1.98V, VDD33 = 3.3V ±10%, TJ = +25°C, unless otherwise noted.)
MAX20751 Multiphase Master with PMBus Interface
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PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Umbrella OVP Threshold Voltage
(Rising) V_UMB_OVP
(Note 2) 2.52 2.59 V
Umbrella OVP Threshold Voltage
(Falling) (Note 2) 2.38 2.45 V
Delay Time to Respond to OVP td_OVP 1 µs
VR_ON (ENABLE) PIN
VR_ONIH VR_ON (Note 2) 0.9 V
VR_ONIL (Note 2) 0.2 V
VR_ON Deglitch Filter Time tFLT_VRON 2 µs
PWRGD (Note 3)
PWRGD Assert Threshold (Rising)
VTHR_PG
Referenced to VNOM (Note 2) -225 -216 mV
PWRGD Deassert Threshold
(Falling) Referenced to VNOM (Note 2) -234 -227 mV
PWRGD Deassert Threshold
Deglitch Filter Time 8 µs
PWRGD High-Deglitch
Filter Time td_PG
PWRGD remains deasserted until
90μs after the end of the startup
IDAC transition
90 µs
Output Low Voltage VPG_OL IOL = -4mA (Note 2) 0.3 V
ORTHOGONAL CURRENT REBALANCING (OCR)
Gain OCR Programmable through PMBus
(Note 1)
0
1.8
3.5
4.4
PMBus (PMC, PMD, ALERTB PINS)
Input High Voltage (PMC, PMD) VIH (Note 2) 1.5 VPM V
Input Low Voltage (PMC, PMD) VIL (Note 2) -0.1 +0.8 V
Output Low Voltage (PMD,
ALERTB) VOL IOL = -4mA (Note 2) 0.4 V
PMBus Resistor Pullup Voltage
(PMC, PMD, ALERTB) VPM 1.71 5.5 V
PMBus Clock Frequency fPMC 100 400 kHz
NONVOLATILE MEMORY PROGRAMMING
Temperature Range for
Programming Data into Nonvolatile
Memory
TEMPNVM_PROG Applies only to STORE_USER_
ALL PMBus command -40 +85 °C
Electrical Characteristics (continued)
(VDD = 1.71V to 1.98V, VDD33 = 3.3V ±10%, TJ = +25°C, unless otherwise noted.).
MAX20751 Multiphase Master with PMBus Interface
and Internal Buck Converter
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PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
PMBus MONITORING AND TELEMETRY
Range of Reported Output Current
as a Percentage of Positive Output
Current-Limit IPLIM
IOUTREPORT
1, 2, or 3 slaves -30 +100
%
4 slaves -30 +88
Error of Reported Output Current 4-phase system at 100A, 1.0V, not
including RDES tolerance (Note 2) -6 +6
Resolution of Reported Output
Current 0.5 A
Update Rate of Reported Output
Current 512 µs
Overcurrent Warning Response
Time Delay After Update 1 ms
Range of Reported Highest Slave
Temperature
TEMPREPORT
-40 +127 °C
Error of Reported Highest Slave
Temperature
4-phase system at 70A, 1.0V
(Note 2) -6 +6 °C
Resolution of Reported Slave
Temperature 1 °C
Update Rate of Reported Slave
Temperature 3 ms
Temperature Warning or Fault-
Response Time Delay After Update 1 ms
Scaled Voltage Range of Input
Voltage at VIN_UV Pin VINSCALE 0.317 1.383 V
Range of Reported Input Voltage
VINREPORT
140/2048 for VIN_UV/VIN voltage
ratio, no offset added 4.625 20.25 V
Error of Reported Input Voltage Not including tolerance of resistor
voltage-divider (Note 2) -2 +2 %
Resolution of Reported Input
Voltage 31.25 mV
Update Rate of Reported Input
Voltage 3 ms
Input-Voltage Warning or Fault-
Response Time Delay After Update 1 ms
Electrical Characteristics (continued)
(VDD = 1.71V to 1.98V, VDD33 = 3.3V ±10%, TJ = +25°C, unless otherwise noted.)
Note 1: Parameters are programmable.
Note 2: Specifications apply over the TJ = -40°C to +105°C temperature range.
Note 3: PWRGD output signal is different from the PMBus POWER_GOOD signal.
MAX20751 Multiphase Master with PMBus Interface
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PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Range of Reported Output Voltage
VOUTREPORT
0.500 1.520 V
Error of Reported Output Voltage 1.000V ≤ VOUT ≤ 1.520V (Note 2) -1 +1 %
0.500V ≤ VOUT < 1.000V (Note 2) -10 +10 mV
Resolution of Reported Output
Voltage 5 mV
Update Rate of Reported Output
Voltage 3 ms
Output Voltage Warning or Fault-
Response Time Delay After Update 1 ms
Range of Reported Output
Power as a Percentage of
(VOUT) x (IPLIM)
POUTREPORT
1, 2, or 3 slaves 0 100
%
4 slaves 0 88
Error of Reported Output Power 4-phase system at 100A, 1.0V, not
including RDES tolerance (Note 2) -7 +7 %
Resolution of Reported Output
Power 2 W
Update Rate of Reported Output
Power 3 ms
(VIN = 12V, VOUT = 1.00V, fSW = 300kHz, Four Phases, COUT = 32 x 47μF Multilayer Ceramic Capacitors, LOUT = 100nH/Phase Two
Winding-Coupled Inductor for Each Pair of Phases.)
OUTPUT-VOLTAGE
RIPPLE - NO LOAD
MAX20751 toc01
CONDITIONS: TRIGGER ON PWM2, POSITIVE-GOING EDGE
1. VOUT: 5mV/div, 20MHz BANDWIDTH
2. PWM2: 1.00V/div, 20MHz BANDWIDTH
1
2
Time/div: 2µs
TURN-OFF
WAVEFORMS - NO LOAD
MAX20751 toc04
CONDITIONS: TRIGGER ON VR_ON, NEGATIVE-GOING EDGE
1. VOUT: 500mV/div, 20MHz BANDWIDTH
2. PWRGD: 2.00V/div, 20MHz BANDWIDTH
3. PWM2: 1.00V/div, 20MHz BANDWIDTH
4. VR_ON: 2.00V/div, 20MHz BANDWIDTH
1
2
3
4
Time/div: 20ms
OUTPUT-VOLTAGE
RIPPLE - 120A LOAD
MAX20751 toc02
CONDITIONS: TRIGGER ON PWM2, POSITIVE-GOING EDGE
1. VOUT: 5mV/div, 20MHz BANDWIDTH
2. PWM2: 1.00V/div, 20MHz BANDWIDTH
1
2
Time/div: 2µs
OUTPUT-VOLTAGE LOAD
TRANSIENT RESPONSE (60A-90A)
MAX20751 toc05
CONDITIONS: TRIGGER ON V
OUT, POSITIVE-GOING EDGE
1. V
OUT: 50mV/div, 20MHz BANDWIDTH
Time/div: 20μs
TURN-ON
WAVEFORMS - NO LOAD
MAX20751 toc03
CONDITIONS: TRIGGER ON VR_ON, POSITIVE-GOING EDGE
1. VOUT: 500mV/div, 20MHz BANDWIDTH
2. PWRGD: 2.00V/div, 20MHz BANDWIDTH
3. PWM2: 2.00V/div, 20MHz BANDWIDTH
4. VR_ON: 2.00V/div, 20MHz BANDWIDTH
1
2
3
4
Time/div: 200μs
OUTPUT VOLTAGE IN HICCUP-MODE
OVERCURRENT PROTECTION
MAX20751 toc06
CONDITIONS: TRIGGER ON VOUT, NEGATIVE-GOING EDGE
1. VOUT: 500mV/div, 20MHz BANDWIDTH
2. IOUT: 133.3A/div, 20MHz BANDWIDTH
3. PWM2: 2.00V/div, 20MHz BANDWIDTH
1
2
Time/div: 10ms
1
3
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MAX20751 Multiphase Master with PMBus Interface
and Internal Buck Converter
Typical Operating Characteristics
R_REF 1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
36 35 34 33 32 31 30 29 28
27
26
25
24
23
22
21
20
19
GND
(Underside Pin)
MRAMP
R_SEL0
R_SEL1
R_SEL2
R_SEL3
GND
VDD
VR_ON
VDD33
PVX
PGND
PWRGD
ISENSE4
ISENSE3
ISENSE2
ISENSE1
TS_FAULTB
N.C.
PMD
PMC
ALERTB
VIN_UV
PWM4
PWM3
PWM2
PWM1
SENSE_P
SENSE_N
A1_OUT
A2_IN
A2_OUT
A2B_OUT
A3_IN
A3_OUT_NORM
A3_OUT_PS
(Top View)
MAX20751 Multiphase Master with PMBus Interface
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PIN NAME FUNCTION
1 R_REF Connect the 20kΩ reference resistor R_REF from this pin to ground. The resistor should have
±0.5% tolerance or lower, with a temperature coefcient of ±25ppm/°C or lower.
2 MRAMP Connect this node to ground through a resistor to program the PWM regulator modulator ramp rate.
3–6 R_SEL0–R_SEL3 Programming Input. Connect these nodes to ground through a conguration resistor with ±1%
tolerance or lower and a temperature coefcient of ±100ppm/°C or lower.
7 GND Ground
8 VDD VDD Supply Voltage Connection
9 VR_ON Input for Regulator to Enable Regulation
10 N.C. No Connection. This node should not be connected to any other devices or components. It is
connected internally.
Pin Conguration
Pin Description
MAX20751 Multiphase Master with PMBus Interface
and Internal Buck Converter
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Pin Description (continued)
PIN NAME FUNCTION
11 PMD PMBus Data I/O
12 PMC PMBus Clock
13 ALERTB Open-Drain, Active-Low PMBus Alert Output
14 VIN_UV Scaled Version of Slave VDDH Voltage. A resistor-divider on this input is used to program the
input undervoltage lockout (UVLO) threshold for the slave VDDH supply.
15–18 PWM4–PWM1
Pulse-Width-Modulation Phase-Control Outputs for the Regulator. Connect these nodes to
the input pins of the slave devices selected for the application. Connect pins for phases not
populated to ground. Do not leave any PWM pin unconnected.
19 TS_FAULTB
Temperature Sensor and Slave Fault Flag. Connect this node to the TSENSE outputs of the
slave ICs. This node is an analog representation of the junction temperature for the hottest slave
of the regulator during normal operation and is also used by the slave devices to report faults (a
fault condition is asserted low).
20–23 ISENSE1–ISENSE4
Phase Current-Sense Inputs. Connect these nodes to the ISENSE outputs of the slave devices.
Ground the pin if not in use (the corresponding RPH resistor should not be connected to ISENSE
when ISENSE is connected to ground) to minimize noise into the device.
24 PWRGD
Power-Good Output for the Regulator. This node indicates whether the output voltage is
within regulation. This open-drain output should be pulled high externally with a resistor of
approximately 10kΩ.
25 PGND Power Ground. Connect this node to power ground.
26 PVX Internal Switcher Switching Node. This node should be connected to an inductor for correct operation.
27 VDD33 3.3V Supply for the IC and Internal Switcher
28 A3_OUT_PS Phase-Shedding Feature (disabled in the MAX20751). This pin must be connected to A3_OUT_
NORM with a short trace or a 0Ω resistor.
29 A3_OUT_NORM Phase Current-Loop Amplier Output for the Regulator. Must be connected to A3_OUT_PS with
a short trace or a 0Ω resistor.
30 A3_IN Phase Current-Loop Amplier Negative Input
31 A2B_OUT This node has the same value as A2_OUT during normal operation, but has programmable
positive and negative voltage clamps that limit the maximum positive and negative output current.
32 A2_OUT Voltage-Loop Amplier Output
33 A2_IN Voltage-Loop Amplier Negative Input
34 A1_OUT Differential Error-Amplier Output
35 SENSE_N Negative Remote-Voltage Sense
36 SENSE_P Positive Remote-Voltage Sense
Block Diagram
A3
SENSE_N
SENSE_P
A1_OUT
A3_OUT_PS
A3_IN
Vcm
IRAMP
PWM
LOGIC
tristate
driver
Shutdown<5:0>
PWRGD
OVP
VREF
DIGITAL
Core
OCP
Ramp Current
Generator
PWRGD
TS_FAULTB
VR_UV
VIN_uvlo
Oscillator
timing reference
Bandgap, Bias,
VDD PORB/UVLO
reset
R_REF
Bias
Generation
R
A1
Vcm
Threshold
Generation
Threshold
Generator
A2
A2_IN A2_OUT
Vcm
capacitor
initialization
Phase
Oscillator mclk
VIN_UV
Freq req<1:0>
PMD
PMC
phase_gen
Phase
Detect
Logic
num_phases_active phase_clock<5:0>
start
num_phases_present
early turn-on
O/C
detector
ALERTB
I_ADC
V(Iout)
num_phases_active
IVT_ADC
en
VDD
digGND and anlog GND
VDD
O/C
detector
R
2R
DACnom
V(Vout)
TS_FAULTB
V(VIN_UV)
VDD33
3.3V
x 4
R_SEL<3:0>
PWM<4:1>
ISENSE<4:1>
4 Phase Gen
2R
11 bits
PMBus Write
OVP_thresh
Umb_OVP
Threshold
Mux
PMBus Write
PVX
PGND
Driver
Switcher
Control
Power
Sequencing
BG_OK_3V
VX Detect
PWDN
OTP_ready
BG_CR
SW_ONTIME<0:1>
3.3V UVLO
OCR
4
VR_ON
SFR Interface
PMBus
Interface
OTP Interface
OTP
BLK
Charge
Pump
3.3V rdy
Scaling
PMBus W
VX
GND
3V UVLO
3.3V rdy
A2B_OUT
A2B
NC
MRAMP
VDD
A3_OUT_NORM
R_PS switch
capacitor
initialization
uC_clk
MAX20751 Multiphase Master with PMBus Interface
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Figure 2. System Efficiency: 4-Phase,100nH/Phase-Coupled Inductors, 350kHz Switching Frequency (VIN = 12V)
85%
90%
95%
70%
75%
80%
0 10 20 30 40 50 60 70 80 90 100 110 120 130
VOUT = 0.8V
VOUT = 1.0V
VOUT = 1.2V
VOUT = 1.5V
VOUT = 1.8V
MAX20751 Multiphase Master with PMBus Interface
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Theory of Operation
The MAX20751 master IC provides a high-frequency, highly
integrated compact solution for high-performance, low-
voltage power conversion (with PMBus interface). The
basic system architecture consists of a single-rail master
controller and up to four smart-slave devices. These ICs,
along with a small number of external components, pro-
vide a complete solution for single-rail voltage regulation.
The master IC contains a pulse-width-modulation (PWM)
control circuit, PMBus interface, and multiphase control
circuits for low-loss operation over a wide range of load
currents. The applicable smart-slave ICs utilize the full
benefits of a synchronous rectification topology. Both the
top and bottom power FETs are integrated on-chip, with
no external power components (MOSFETs or Schottky
diodes) required. Each smart-slave device contains
temperature and current monitoring. PWM signals are
generated in the master IC and sent to the slaves.
Current-sense and temperature feedback signals are
generated in the slaves and sent to the master.
The smart-slave ICs have integrated lossless current-
sense technology. This current-sense technology pro-
vides accurate current information that is not affect-
ed by temperature, process variation, or tolerances of
passive elements such as the output inductor, resistors
and capacitors, and NTCs used in other systems to
extract current information. With this approach, a current-
sense signal is fed back to the master as a current instead
of a voltage, as is the case with DCR and other forms of
current sensing. This allows very robust system
feedback of current, with better noise immunity than
other methods. The current information can be used
to control the load line precisely and in the calcula-
tion of real output-power measurements. Highly precise
current information removes the challenges of meeting
load-line specifications, especially at light load, an area
known to challenge DCR current sensing due to the low
signal levels and tolerances involved.
The output voltage, output-voltage turn-on slew rate,
PMBus address, and PMBus output-current gain are
hardware programmable using configuration resistors,
as discussed in the Configuration section.
An internal integrated switching regulator allows
creation of the VDD supply from the VDD33 supply, with the
addition of an LC filter.
Control Architecture
Figure 3 shows the internal amplifier stages of the master
and how phase-current information is used to generate
the phase-control signals, as well as provide accurate
current reporting. The master IC contains multiple ampli-
fier stages and one duty-cycle modulator for each phase,
to allow independent control of the high-side MOSFET
on-time according to each individual phase current.
The first amplifier stage (A1) in Figure 3 is a differential
amplifier, the output being the error between the DAC
reference voltage and the differential voltage-sense lines
multiplied by a factor of 2.19. This stage enables true
remote voltage sensing, and its differential structure pro-
vides high common-mode rejection ratio to protect from
any noise present at the processor ground. The second
amplifier stage (A2) provides voltage-loop compensation,
with its DC gain used to set the load line of the voltage
regulator. The A2 amplifier is followed by a clamping
circuit and buffer amplifier (A2B) to provide overcur-
rent protection (OCP). The output of amplifier A2B is
converted to a current through the resistor (RDES) and rep-
resents the desired total system current (IDES), which sets
the target for the current loop. The third amplifier (A3) acts
as a current-error amplifier, as it receives the current com-
mand (through RDES) and each individual sensed current
from the smart-slave ICs (through resistors RPH1, RPH2,
and RPH3, as shown in Figure 3. This stage has an inte-
grator connection. The very large DC gain of the A3 stage
guarantees that the total load current equals the current
command (IDES) in steady state. As a result, the load line
of the voltage regulator is set by the gain of the voltage-
loop amplifier (A2). Zero load line can be achieved by
configuring the amplifier as an integrator by placing
capacitor C2 in series with R2, as shown in Figure 3.
The system also offers programmable modulator ramp-
rate stability and noise immunity, set by connecting a
resistor between the MRAMP pin and ground. This ramp
determines the duty-cycle modulator gain and is used to
tune the current-loop compensation.
Loop compensation is implemented by adding series or par-
allel RC networks across the voltage-loop and current-loop
amplifiers (A2 and A3), respectively. For the voltage loop,
lead compensation can be added by using a series RC net-
work across the R1 resistor, as shown in Figure 3 (RLD_A2
and CLD_A2). Lag compensation can be added by adding
a series RC network across the R2-C2 network resistor.
Compensation for the current loop is achieved by
placing a series RC network across the current-loop
amplifier feedback (RINT-CINT, in Figure 3). This network
provides extremely high gain at low frequency, which
guarantees tight current regulation (i.e., the output current
is very close to the current command).
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Integrated 1.8V Switching Regulator
The MAX20751 master IC features an integrated switch-
ing regulator that provides the bias current to the master
controller and to the smart-slave ICs (both core analog/
digital circuits and gate drive).
This regulator enables efficient power conversion from
the 3.3V supply at both light load and heavy load using
a pulse-frequency-modulation (PFM) mode of operation.
The external LC filter for this regulator is extremely small
and inexpensive, as it only requires a chip inductor and
small case-size ceramic capacitors. The control scheme
adopted here is voltage mode constant on-time with the
inductor always operated in the discontinuous-conduction
mode (DCM) of operation, providing an inherent current-
limiting protection as well as soft-start capability. Details
of the integrated regulator can be seen in the Block
Diagram. The PGND pin should connect to the GND pins
through a single wide trace or via.
In order to achieve simple average-output current-limiting
protection, this converter is forced to stay in DCM mode
by only allowing high-side turn-on when the current
reaches zero. The peak current in the inductor is given in
Equation 1.
Equation 1:
DD33 DD
P ON
PVX
VV
It
L
−
=
where:
LPVX is the switcher inductor
The maximum average current is given by Equation 2.
Equation 2:
DD33 DD
MAX_AVE ON
PVX
VV
It
2L
−
=
If load current is higher than IMAX_AVE, the VDD voltage
drops. If VDD drops below the falling UVLO threshold, the
device resets.
The on-time (tON) is programmable using the
PMBus. Table 1 shows the programmable on-times.
Before VDD has risen above the rising undervoltage-
lockout (UVLO) threshold, the lowest on-time of 0.64μs
is used. When VDD has risen above both the rising
and falling UVLO thresholds, the switcher uses the
programmed on-time. The default value is 1.30μs.
The switcher becomes active when VDD33 voltage has
risen above its rising UVLO threshold.
The inductor (LPVX) must be able to support the
maximum peak current without saturating significantly,
since the inductor impedance is what provides the current
limit. The maximum peak current occurs at startup from
zero output voltage.
The output-voltage peak-to-peak ripple depends on the
capacitor (CVDD). The worst-case ripple occurs at light
load and is given in Equation 3.
Equation 3:
DD33
P
P P ON
VDD DD
V
I
Vt
2C V
−
∆= ×
where:
∆VP-P should be 30mV or less
Figure 3. Control Architecture
Table 1. On-Time Selection Table
A2
VCM
A2_OUT
A2_IN
A1_OUT
OCP CLAMP
VCM
SENSE_P
SENSE_N
VDD
IDAC
R2N
R1N
R2P
R1P
Vx
A2B RDES
A3
RPH1
RPH2
RPH3
Slave1
ISENSE
Slave3
ISENSE
RFILT3
CPAD3
C
RR
I
RR
S
R
Q
ph_clk
RINT
CINT
A2B_OUT
A3_IN
ISNS3
A3_OUT_NORM
Slave2
ISENSE
VCM
Phase Control
(One Phase Shown for Clarity)
R2 C2R1
RLD_A2 CLD_A2
A1
OCP CLAMP and Buffer Amplifier
IDES
OCR
ISNS2
ISNS1
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ON-TIME (µs) 0.64 1.30 (Default) 1.91 2.76
The control method regulates the valley voltage. The
peak voltage is the valley voltage plus the peak-to-peak
ripple voltage.
The current from the VDD33 supply occurs in pulses of
charge given by Equation 4.
Equation 4:
P
VDD33 ON
I
Qt
2
=
where:
IP is the peak current
Capacitor CDD33 at the VDD33 pin should be chosen to
supply the peak current and charge without too much
voltage change. A ceramic capacitor of at least 10μF is
recommended.
To estimate the VDD33 current using the integrat-
ed switching regulator, assume a minimum efficien-
cy of 80% for the integrated switching regulator. For
example, if the maximum total master and slave IC
current from VDD is 175mA, VDD = 1.9V, and
VDD33 = 3.3V, then the VDD33 current for the
integrated switching regulator is (175mA x 1.9V)/(3.3V x
0.80) = 126mA.
To estimate the total VDD33 current, also include
the PMBus resistor pulldown current if operated
from VDD33. For example, if 2.15kΩ pulldown resis-
tors are used from the PMC, PMD, and ALERTB pins
to VDD33, then the maximum PMBus current is 3 x
3.3V/2.15kΩ = 4.6mA. Therefore, the total VDD33 cur-
rent for the integrated switching regulator and PMBus is,
approximately, 131mA.
The integrated switching regulator can be disabled by
removing LPVX and connecting a 10Ω resistor from PVX
to VDD33. An external supply is then applied to VDD.
Startup and Shutdown Operation
When VDD and VDD33 are above their rising UVLO
thresholds, the device is enabled and goes through an
initialization and phase-detection procedure. Configuration
resistors are read and external resistors checked for valid
values. Any faults will prevent the output voltage from
turning on.
The PMBus communication and telemetry are then
enabled. The VIN_UV voltage must be above its rising
UVLO threshold for the output voltage to turn on.
If the output voltage is programmed to below 0.25V
through the PMBus VOUT_COMMAND, the output is
disabled. Programming the output voltage to any other
allowable voltage using the PMBus VOUT_COMMAND
allows the output voltage to turn on.
Depending on how the voltage-regulation enable is
configured, a VR_en signal from VR_ON and/or the
PMBus OPERATION command may also be required for
the output voltage to turn on. The default configuration for
the VR_en signal is the VR_ON signal at the high logic
level, with no PMBus command needed.
When the VIN_UV voltage is above its rising UVLO
threshold and the proper VR_en signal, if required,
has occurred, the output voltage turns on after the
PMBus programmable TON_DELAY time. The default
TON_DELAY time is 0ms.
After the output voltage has reached its nominal value,
the PWRGD signal is asserted.
The startup sequence caused by VR_ON going high is
shown in Figure 5.
When shutdown occurs, the master IC causes the VX
nodes of the slaves to stop switching, which then causes
the output voltage to turn off. The PWRGD signal is deas-
serted and is actively pulled low.
Depending on how the voltage-regulation enable is
configured, the output voltage can be turned off using the
VR_en signal from VR_ON and/or the PMBus OPERATION
command. Depending on the PMBus configuration, the
output turns off immediately or with sequencing. When
the output turns off with sequencing, there is a delay time
determined by the PMBus programmable TOFF_DELAY
command and then VOUT ramps down with a turn-off slew
rate that is the same as the turn-on slew rate for turn-on
slew rates of 1.25mV/μs, 2.5mV/μs, and 5mv/μs. For turn-
on slew rate 0.5mV/μs, if sequencing is used, the delay
time is followed by an immediate turn-off (no slew rate-
controlled VOUT ramp-down). The default TOFF_DELAY
time is 0ms. Note that when VOUT ramps down, energy
Figure 4. Integrated Switcher Circuit
VDD Switcher
PVX
VDD
VDD33
PGND
CDD33 CDD
LPVX
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may be delivered from VOUT to VIN. The VIN capacitors
should be sized to absorb this energy to prevent a large
increase in the VIN voltage.
The output voltage can be turned off by program-
ming the output voltage below 0.25V using the PMBus
VOUT_COMMAND. The turn-off in this case is also
determined by the PMBus configuration.
If the VDD or VDD33 supplies go below their falling UVLO
thresholds, the output voltage is turned off and the system
is reset.
The output voltage can be turned off by the VIN_UV
voltage going below the VIN_UV falling UVLO threshold.
This is logged as a hardware fault.
The VIN_UV UVLO thresholds should be higher than
the corresponding smart-slave IC’s VDDH UVLO thresh-
olds to prevent a slave fault from occurring, which could
potentially prevent the output voltage from turning back
on. If this occurs, the system may need to be reset by
bringing the VDD or VDD33 supplies below their falling
UVLO thresholds.
The shutdown sequence caused by VR_ON going low is
shown in Figure 6.
Figure 5. Startup Sequence
VDD
VDD33
VR_en
VOUT
PWRGD
T
A
T
F
T
C
T
A
: Initialization time needed before startup
can begin. Maximum 6ms.
T
C
: Time from VR_en signal (from VR_ON or
PMBus) to V
OUT
startup with TON_DELAY.
T
F
: Time from V
OUT
reaching V
NOM
to
PWRGD assertion. Typical 90µs.
1.25mV/µs, 2.5mV/µs, or 5mV/µs
V
OUT
TURN-ON SLEW RATE TYPICAL T
C
200µs
0.5mV/µs 4ms
Delay from VR_ON to
VR_en: Typical 2µs.
Delay from last ACK of PMBus
OPERATION command to enable
VOUT to VR_en: 75µs.
VIN_UV
Note: For the 0.5mV/µs setting, T
C
:will increase if there is a nonzero prebias
voltage on V
OUT
. Also, the TON_MAX_FAULT_LIMIT and
TON_MAX_FAULT_RESPONSE commands do not work for the 0.5mV/µs setting.
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Droop and Load-Line Regulation
If the A2 amplifier series R2-C2 network is replaced by
resistor R2 only, the MAX20751 provides accurate output
load line over the entire range of output currents. The load
line is set by the combination of the R1, R2, and RDES
resistors.
Switching Frequency and Output-Voltage
Turn-On Slew Rate
The switching frequency and output voltage turn-on slew
rate are programmable using configuration resistors. See
the Configuration section. They are also programmable
using the PMBus.
Orthogonal Current Rebalancing (OCR)
Phase-current imbalance can occur due to high-
frequency loading transients. The purpose of the OCR
circuit is to reduce phase-current imbalance.
This is accomplished by modifying the output of the A3
amplifier for each individual phase (k). Instead of the A3
amplifier output voltage being fed directly to the PWM
comparator of a phase, a control voltage (VCk) is used.
The equation for VCk is given in Equation 5.
Equation 5:
N
Ck O3 OCR RPHk RPHi
i1
1
VVG V V
N=
=−−
∑
where:
VRPHk = Voltage on resistor RPHk (a voltage proportional
to the current in phase k)
VO3 = A3_OUT_NORM voltage
N = Total number of phases
GOCR = Gain of the OCR circuit
VCk = Voltage fed to the phase k PWM comparator
instead of the A3 amplifier output voltage
The difference between the current of a phase k from the
average current (with some gain GOCR) is subtracted
from VO3 to determine the control voltage (VCk). If the
current in any phase is greater than the average of all the
phases, then the corresponding VCk voltage will be less
than VO3 and the subsequent PWM pulse for that phase
shorter, thus preventing further phase-current imbalance.
The default gain (GOCR) is 1.8.
Input Voltage Undervoltage Lockout (UVLO)
Using the VIN_UV Pin
The VIN_UV pin on the master IC is connected to
the middle point of a voltage-divider from the slave
VDDH (power input rail) to ground. This pin provides an
externally programmable input supply UVLO and sensing
for the PMBus VIN telemetry.
The UVLO function is provided by comparing the VIN_UV
voltage to internal references with a comparator. When
the VIN_UVLO voltage exceeds the rising threshold, the
system is allowed to operate and the falling reference volt-
age is then used as a disable point for built-in hysteresis.
See the Electrical Characteristics table for more details.
Figure 6. Shutdown Sequence
VDD
VDD33
VR_en
VIN_UV
VOUT
PWRGD
T
Y
T
Z
PWMi
T
Y
: Time from VR_en signal (from VR_ON or
PMBus) to V
OUT
shutdown with
TOFF_DELAY=0ms. Typical 2µs for immediate
shutdown. For 1.25, 2.5, and 5mV/µs slew rate:
Typical 200us for sequenced shutdown.
Delay from VR_ON to
VR_EN: Typical 2µs.
Delay from last ACK of
PMBus OPERATION
command to disable
V
OUT
to VR_EN: 10µs.
T
Z
: Time from VR_EN to PWRGD LOW.
Maximum 9µs.
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Figure 7 shows the VIN_UV circuit. Resistors RIN and
RGND form a voltage-divider that scales the VIN voltage
to the VIN_UV pin. The scale factor (VIN_RATIO) is given
by Equation 6. VIN_RATIO is programmable using the
PMBus. The default value is (140/2048) = 0.06836.
Equation 6:
GND
GND IN
R
VIN_RATIO RR
=+
RGND||RIN should be approximately 2kΩ with
capacitor CIN_UV = 100pF. It is suggested to use 1% tol-
erance resistors with the values RGND = 2.15kΩ and RIN
= 29.4kΩ. The value for VIN_RATIO should be less than
or equal to 140/2048.
Phase Population Order
Depending on the total number of phases in the system,
specific phase positions must be populated, while the
others must be deactivated by connecting a 0Ω resistor
between the MAX20751’s phase-control pins (PWMk) of
the inactive phases and ground (Table 2).
The phase number is defined by the PWMx pin name
(e.g., phase 2 is driven by PWM2).
For example, for 2-phase operation, only phases 2 and 1
are used; therefore, pins PWM4 and PWM3 should each
be connected to GND with 0Ω resistors.
For 3-phase operation, PWM4 should be connected
to GND with a 0Ω resistor. For single-phase operation
PWM4, PWM3, and PWM1 should each be connected to
GND with 0Ω resistors.
If the wrong PWMk pins are connected to GND with 0Ω
resistors, a configuration fault occurs in the fault-checking
procedure (occurring prior to VOUT startup) and operation
is halted.
Protection And Monitoring
The master IC includes multiple protection circuits to
protect the regulator and load, and to monitor the output
voltage, as described in the following sections.
Fault Detection when VDD and VDD33 are
Initially Applied
When VDD and VDD33 are initially applied and at their
proper levels, the master IC checks the following resistor
values and connections and if detected as being outside the
correct range or open, an error is flagged and the
regulator will not start regulation:
●RMRAMP
●RREF
●SENSE_P Open
PWRGD (Power-Good) Pin
The PWRGD output (different from the PMBus POWER_
GOOD signal) is an active-high, open-drain output used
to show that the output is settled at its commanded
voltage. The output goes high after a fixed delay, after
the end of the output-voltage startup transition, assuming
the output voltage is above the PWRGD threshold. It is
deasserted when any of the following occurs:
●The output voltage drops below the threshold,
relative to the nominal voltage, for any reason.
●An OVP fault is detected.
●An OCP fault is detected when the mode is set to
hiccup mode and the regulator shuts down the output
voltage during the shutdown part of the hiccup cycle.
In constant current-limit mode, the PWRGD signal is
based on the PWRGD voltage threshold only.
●The output is disabled.
Table 2. Phase Population Positions
Figure 7. VIN_UV Pin Voltage-Divider Circuit
V
IN
R
IN
C
IN_UV
R
GND
V
IN_UV
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NUMBER OF
POPULATED PHASES
POSITIONS TO BE POPULATED
(BY FIRING SEQUENCE)
1 2
2 2, 1
3 2, 1, 3
4 2, 4, 1, 3
*Note: “Yes (through slave)” refers to the fact that the slave latches in this condition and therefore the system latches. Once the
slave fault is cleared by cycling its power, the system can restart. This table shows the effect on the system.
Overcurrent Protection (OCP)
System OCP is based on a fixed voltage threshold for the
voltage across the RDES resistor. The overcurrent thresh-
old is therefore set by selecting an appropriate value of
RDES for the design. The voltage threshold is scaled
internally, depending on the number of active phases (i.e.,
the voltage threshold is a fixed per-phase value).
The OCP trips when the peak voltage over RDES reaches
the inception value and remains tripped down to the
nominal/sustaining value (i.e., the values shown are the
sustaining currents and not the inception point, which is
5% higher). Negative (sinking) OCP is automatically set to
30% of the positive value.
The OCP is based on the instantaneous voltage over
RDES, and a small ripple voltage reflecting the out-
put-voltage ripple may be present. If the instantaneous
commanded current (output of amplifier A2) reaches
the inception voltage, the commanded current is imme-
diately clamped to the sustaining value. If the com-
manded current drops below the sustaining value, it must
once again reach the inception point before clamping
commences.
An overcurrent fault is logged in the fault log if clamp-
ing continues for 5ms, to ensure that only periods of
continuous overloads are recorded as faults.
Table 3. Master Faults
Table 4. Effects of Slave Faults
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MAX20751
PROTECTION
MAX20751 OUTPUT
SIGNAL(S) SHOWING FAULT
SYSTEM
SHUTDOWN
SYSTEM
LATCHED OFF?
LOGGED IN
FAULT LOG?
Resistor Out-of-Range
Detected at Startup PWRGD low System
does not start Yes Yes
OCP: Hiccup or CCM PWRGD low (if output
drops below threshold) No No Yes
(after 5ms)
Fixed (Umbrella) or
Tracking OVP PWRGD low Yes Yes Yes
VIN_UV UVLO PWRGD low (if output
drops below threshold) Yes No Yes
Output Undervoltage PWRGD low No No No
VDD UVLO PWRGD low Yes No
(system in reset) No
VDD33 UVLO PWRGD low Yes No
(system in reset) No
SLAVE FAULT MAX20751 OUTPUT SIGNAL
SHOWING FAULT
SYSTEM
SHUTDOWN
SYSTEM
LATCHED OFF*
LOGGED IN
FAULT LOG
Slave Cycle-by-Cycle OCP
(Sinking or Sourcing Current) None No No Yes
Slave Sourcing OCP
Current Shutdown PWRGD low Yes Yes
(through slave) Yes
Slave OTP Shutdown (Sent to
Master through Slave TS_FAULTB
Low)
PWRGD low Yes Yes
(through slave) Yes
Slave Boost UVLO (Undervoltage
Lockout on Boost Supply) PWRGD low Yes No Yes
Slave VX Short-to-Ground
or VDDH PWRGD low Yes Yes (through slave) Yes
Three modes of operation are provided for positive
(sourcing) OCP: shutdown, constant current, and
hiccup (default); negative OCP is always constant current.
The mode can be changed using PMBus commands. If
hiccup OCP mode is selected, when the OCP is exceed-
ed, the system will deliver the maximum programmed
sustaining current for 5ms before shutting down
and waiting 45ms before restarting. This cycling
continues until the commanded current falls below
the programmed value. Should constant-current mode
be selected, the system tries to regulate at the OCP
sustaining current until the commanded current falls
below the sustaining value. The upper threshold of
current delivery is the OCP inception point and, once
this level is reached, the system folds back to the
sustaining level (the programmed value) to deliver
constant current indefinitely. The shutdown mode is similar
to the constant-current mode but shuts down VOUT after
5ms. The VOUT voltage can be enabled again by using the
VR_ON signal and/or the OPERATION PMBus command.
Overvoltage Protection (OVP)
Two separate OVP circuits are included, one based on
the programmed nominal output voltage, the other on an
“umbrella” fixed value. If either is tripped, an OVP fault is
recorded, PWRGD is deasserted, and the system stops
regulating. OVP faults can only be cleared by toggling the
VDD or VDD33 supply rail.
Undervoltage Lockout
The master IC includes three UVLO circuits, VDD rail,
VDD33 rail and VDDH (i.e., VIN). VIN is monitored through
an external resistor-divider to bring the voltage down to
within the operating range of the VIN_UV pin. If a VIN
UVLO is detected, the system stops regulating and indi-
cates an input-voltage fault. Once the input voltage rises
above the rising threshold, the IC reinitiates and follows
the same startup procedure as if enabled by VR_ON.
Conguration
Determining the Optimum Number of Phases,
IOUTMAX, and Overcurrent Protection
The typical starting point for a voltage-regulator design is
to choose a value of maximum output current (IOUTMAX).
The value of IOUTMAX is determined by the MAX20751
system overcurrent-protection (OCP) setting and is set to
85% of this setting. Therefore, a target minimum system
OCP rating can easily be determined based on IOUTMAX.
Once this value is known, the area available, smart-slave
part numbers to be used, and the desired performance
Table 5. Selection of RDES for Overcurrent Limit and Maximum
Output Current IOUTMAX = 0.85 IOCP
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1-PHASE OCP (A) 2-PHASE OCP (A) 3-PHASE OCP (A) 4-PHASE OCP (A) RDES (Ω)
25 50 75 100 604
27.3 54.7 82 109.3 549
29.7 59.3 89 118.6 511
32 64 96 128 464
34.3 68.6 103 137.3 432
36.7 73.3 110 146.6 412
39 78 116.9 155.9 383
41.3 82.6 123.9 165.2 365
43.6 87.3 130.9 174.6 340
46 91.9 137.9 183.9 324
48.3 96.6 144.9 193.2 309
50.6 101.3 151.9 202.5 294
53 105.9 158.9 211.8 280
55.3 110.6 165.9 221.2 274
57.6 115.2 172.9 230.5 261
60 119.9 179.9 239.8 249
versus cost should all be considered, with the number of
phases and smart-slave devices determined. Efficiency
curves and ratings shown on the respective smart-slave
data sheets can be used for this purpose.
If any phases
aren’t used, their corresponding PWMx pins should be
connected to GND with 0Ω resistors, as discussed in the
Phase Population Order section.
Selecting RDES
With the number of phases and part numbers
known, RDES should be selected to give the correct
overcurrent-protection (OCP) value. The OCP value is
set by RDES, in that the master IC uses a fixed value
of 150mV per phase. Since RDES is also used by
Table 6. Using R_SEL3 to Set the VOUT Slew Rate and Switching Frequency
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VOUT SLEW RATE (V/ms) fSW (kHz) R_SEL3 (Ω)
1.25
300 0
350 17.8
400 33.2
450 48.7
500 64.9
600 80.6
700 95.3
800 115
2.5
300 133
350 154
400 178
450 200
500 226
600 249
700 274
800 301
5
300 332
350 365
400 402
450 432
500 464
600 499
700 536
800 576
0.5
300 619
350 665
400 715
450 768
500 825
600 887
700 953
800 1020
Note 1: Selecting VOUT below 0.25V disables the output voltage.
Note 2: RDES defines IOCP, IOUTMAX, and the IOUT PMBus telemetry.
the PMBus telemetry circuitry to measure the output
current (IOUT), the value of RDES must be selected from
Table 5 of standard 1% resistors.
For example, if an IOUTMAX of 170A is required, IOCP
must be a minimum of 170/0.85 = 200A. If a 4-phase
design has been selected, looking in the 4-Phase OCP
column, we see the next highest value for IOCP is 202.5A
and requires the use of RDES with a value of 294Ω, which
gives a nominal reported IOUTMAX of 0.85 x 202.5 = 172A
(IOUTMAX is rounded to an integer value). Care should
be taken with tolerance and rounding to ensure that the
required IOUTMAX is met.
Using Conguration Resistors to Program
the Output-Voltage Slew Rate and Switching
Frequency
R_SEL3 is used to set the output-voltage slew rate and
switching frequency. Table 6 shows the output-voltage
slew rates, switching frequencies, and corresponding
values for R_SEL3.
R_SEL3 has 32 possible values, with each value
corresponding to a distinct pairing of slew rate and
switching frequency.
For example, to choose an output-voltage slew rate of
0.5V/ms and a switching frequency of 350kHz, R_SEL3
= 665Ω.
Using Conguration Resistors to Program
the Output Voltage, PMBus Address Lowest
3 Bits, and IOUT Telemetry for the RDES Value
Being Used
Table 7 shows the parameter values and corresponding
configuration resistor values used to program the output
voltage, PMBus address lowest 3 bits (PMAD[3:1]), and
PMBus IOUT telemetry circuitry with the RDES value used
in the overcurrent-limit circuit.
R_SEL2 and R_SEL1 are the configuration resistors used
to set the output voltage. The output voltage is the sum of
the two voltages chosen by R_SEL2 and R_SEL1.
R_SEL1 and R_SEL0 are the configuration resistors used
to set the lowest 3 bits (PMAD[3:1]) of the entire PMBus
address (PMAD[7:1]). The upper 4 bits (PMAD[7:4]) are
constant at the value 1110b.
R_SEL0 is the configuration resistor used to program
the PMBus IOUT telemetry circuitry with the RDES value
being used in the overcurrent-limit circuit.
Table 7. Using R_SEL2, R_SEL1, and R_SEL0 to Set the Output Voltage, Set the Lowest
PMBus Address Bits, and Program the IOUT Telemetry with the RDES Value Being Used
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VOUT
(V)
R_SEL2
(Ω)
PMAD
[2:1]
VOUT
(V)
R_SEL1
(Ω) PMAD3 RDES
(Ω)
R_SEL0
(Ω)
0.890 332
10
-0.005 332
1
604 332
0.930 365 0.000 365 549 365
0.970 402 0.005 402 511 402
1.010 432 0.010 432 464 432
1.050 464 0.015 464 432 464
1.090 499 0.020 499 412 499
1.130 536 0.025 536 383 536
1.170 576 0.030 576 365 576
1.210 619
11
-0.005 619 340 619
1.250 665 0.000 665 324 665
1.290 715 0.005 715 309 715
1.330 768 0.010 768 294 768
1.370 825 0.015 825 280 825
1.410 887 0.020 887 274 887
1.450 953 0.025 953 261 953
1.490 1020 0.030 1020 249 1020
VOUT
(V)
R_SEL2
(Ω)
PMAD
[2:1]
VOUT
(V)
R_SEL1
(Ω) PMAD3 RDES
(Ω)
R_SEL0
(Ω)
0
00
-0.005 0
0
604 0
17.8 0.000 17.8 549 17.8
33.2 0.005 33.2 511 33.2
48.7 0.010 48.7 464 48.7
64.9 0.015 64.9 432 64.9
80.6 0.020 80.6 412 80.6
0.490 95.3 0.025 95.3 383 95.3
0.530 115 0.030 115 365 115
0.570 133
01
-0.005 133 340 133
0.610 154 0.000 154 324 154
0.650 178 0.005 178 309 178
0.690 200 0.010 200 294 200
0.730 226 0.015 226 280 226
0.770 249 0.020 249 274 249
0.810 274 0.025 274 261 274
0.850 301 0.030 301 249 301
Each R_SELx resistor has 32 possible values, with
each value corresponding to one or more programmable
parameters.
For example, to program 1.000V output voltage,
PMAD[3:1] = 011b, and RDES = 294Ω, use:
R_SEL2 = 402Ω (0.970V),
R_SEL1 = 1020Ω (PMAD[2:1] = 11b, 0.030V),
R_SEL0 = 200Ω (PMAD3 = 0b, RDES = 294Ω)
This results in the output voltage = 0.970V + 0.030V =
1.000V, PMAD[3:1] = 011b, and RDES = 294Ω.
The output voltage can also be programmed using the
PMBus. Note that the output voltage is disabled if it is set
below 0.25V through the PMBus.
Inductor Phase-Current Ripple
For coupled inductors, the inductor peak-to-peak phase-
current ripple can be calculated from Equation 7 (which
assumes perfect coupling for coupled inductors, and duty
cycle ≤ 1/N).
Equation 7:
= −
OUT OUT
PHPP
SW CW IN
VV
1
If Ln V
where:
IPHPP = Peak-to-peak phase-current ripple in the inductor
fSW = Switching frequency
L = Inductance per phase
nCW = Number of coupled windings
VIN = Input voltage
VOUT = Output voltage
In practice, the coupling will not be perfect, but good
coupling can be achieved, with the actual ripple current
close to what is calculated by the equation.
The output current ripple is given by Equation 8,
assuming duty cycle ≤ 1/N.
Equation 8:
= −
OUT OUT
PP SW IN
VV
1
IN
f LN V
where:
IPP = Peak-to-peak output-current ripple
L = Inductance per phase
N = Number of phases
Output Capacitance Calculation
One criterion for determining the value of the output
capacitance (COUT) is the maximum allowable output-
voltage overshoot (∆VOST) during unloading transients.
For a maximum unloading current step (∆I) and maximum
allowed output-voltage overshoot change (∆VOST), the
required output capacitance is given by Equation 9.
Equation 9:
2
OUT
OST OUT
L
( I) N
C2( V ) V
∆
≥∆
where:
L = Inductance per phase
N = Number of phases
VOUT = Nominal output voltage
For example, in a case where allowable overshoot is
the limiting factor for a 3-phase system with 250nH of
inductance per phase, 1.0V output, maximum current step
of 50A, and maximum allowable overshoot of 100mV,
the minimum COUT theoretically required is 1042μF.
Selecting a higher value gives good design margin
against component variation and effective capacitance
loss due to voltage bias.
Bleed Resistor
A small bleed resistor of approximately 100Ω should
be connected between the output of the regulator
and ground to ensure that the output capacitors are
discharged shortly after the output is disabled. The
resistor should be sized so that when the maximum
expected output voltage is applied, the resistor’s power
dissipation is sufficiently below its rated power dissipation.
Droop and No-Droop Operation
The device provides accurate output-droop resistance
over the entire range of output currents. The RDROOP is
set by the combination of the R1, R2, and RDES resistors,
according to Equation 10.
Equation 10:
=1 DES
DROOP 2I
RR
RR 2.19A
where:
AI = Slave current gain factor
R1 = Having a typical value of 600 to 800. The R2/R1
should be a minimum of 0.45
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If R2/R1 < 1, then R1 should be between 600Ω and 800Ω,
R2 should be 353Ω, minimum, and the ratio of R2/R1
should be 0.45, minimum.
If R2/R1 > 1, then R1 should be between 400Ω and 800Ω.
R2 should be 400Ω, minimum.
No-droop operation can be achieved by adding capaci-
tor C2 in series with R2 in the A2 stage, according to
Equation 11.
Equation 11:
OUT
2
LC
N
C2 R
≥
Above the frequency (Equation 12), the voltage-regulator
impedance approaches RDROOP.
Equation 12:
222
1
f2RC
=π
With either the droop or no-droop configuration, above the
frequency (Equation 13).
Equation 13:
ZINT PH
INT INT
1
fR
2R C
N
=
π+
where:
N = Number of phases
The voltage-regulator impedance approaches:
PH
INT
DROOP INT
R
RN
RR
+
up to the voltage-loop bandwidth, unless the lead network
is used.
RFILT Selection
The RFILT resistor, together with the capacitance at the
ISENSE pin, creates a lowpass filter for the sensed smart-
slave phase-current signal. A 3.01kΩ resistor should be
used for RFILT.
Selecting the Modulator Ramp Rate
The modulator ramp rate is set using external resistor
RMRAMP from the MRAMP pin to GND.
The ramp rate (SRAMP) can be determined from the
switching frequency (fSW), steady-state ramp voltage
(VRAMPD), and duty cycle (D = VOUT/VIN), according to
Equation 14.
Equation 14:
RAMPD
RAMP SW
V
Sf
D
=
The VRAMPD voltage typically ranges from 100mV to
300mV. Note that VRAMPD changes with D, while SRAMP
remains constant.
A smaller SRAMP provides a larger-loop bandwidth for the
total inductor current (see the Loop Bandwidths section).
Once a ramp-rate value has been determined, the value
of the resistor can be calculated using Equation 15.
Equation 15:
MRAMP
RAMP
23.81
RS
=
where:
RMRAMP is in kΩ
SRAMP is in V/μs
Example: If the required ramp rate = 1.0V/μs, then
RMRAMP = 23.81kΩ, and the closest 1% value is 23.7kΩ.
RINT Selection
Set RINT according to Equation 16.
Equation 16:
For single phase:
( )
DD_MIN CM
INT
PP
DES I
V -0.2V-V
R< I
0.15VN+
RA
For 2 or more phases:
( )
DD_MIN CM
INT DES
PP
DES I
V -0.2V-V
R < MIN ,3R
I
0.15V N+
RA
where:
VDD_MIN = Minimum VDD voltage used in the application
VCM = Compensation circuit common-mode voltage =
0.85V
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RDES = Resistor used to set the IOCP value
IPP = Peak-to-peak ripple of the output current
AI = Save current-gain factor
Note that a larger RINT provides a larger-loop bandwidth for
the total inductor current (see the Loop Bandwidths section).
RPH Selection
Each of the Maxim slave’s current-sense pins is
connected to the A3_IN pin of the master IC through its
phase resistor (RPHk). The value of each phase resistor
determines the amplitude of the phase current-sense
signal, which must be below 0.4V at all times, up to and
including the overcurrent limit.
To help prevent phase-current imbalance due to load
transients, set according to Equation 17.
Equation 17:
( )
≥I
PH NT
OCR
R
G
R + 1
where:
GOCR = Gain of the OCR circuit
Current Steering
The phase-current-balancing circuitry works to keep the
voltages across the RPH resistors approximately equal.
By increasing the RPH resistor from the nominal value on
a particular phase, the steady-state current in that phase
can be reduced with respect to the other phases. This may
be useful in reducing the temperature on the smart-slave
device and inductor of that phase, if they tend to get hotter
than the corresponding components of the other phases
when the phase currents are all equal. Care should be
taken so the inductors of the other phases do not saturate
because of too much current; with coupled inductors, the
relative balance of phase currents is also important.
CINT Value
CINT should be selected to match the time constant of the
double pole, which is intrinsic in the buck-converter duty
cycle-to-output transfer function given by Equation 19.
Equation 19:
Loop Bandwidths
The output-voltage loop bandwidth is given by Equation 20
(if the lead network is not used).
Equation 20:
VL PH
INT
DROOP OUT
INT
1
BW R
RN
2R C
R
=
+
π
If the lead network is used, the output-voltage loop band-
width and phase margin can be increased.
The loop bandwidth for the total inductor current is given
by Equation 21.
Equation 21:
PH
INT SW
RAMP
INT
IL I
R
RN
N
BW < 2L A
Vf
S
+
π
where:
L = Inductance per phase
A
I
= Slave current gain factor
The loop bandwidths should meet the conditions given by
Equation 22.
Equation 22:
<
<
VL IL
SW
VL
BW BW (by at least 50kHz difference)
f
BW
4
Note: If BWVL < BWIL + 50kHz cannot be met, additional
phase margin can be added with the lead network.
OUT
INT PH
INT
LC
N
CR
RN
≥
+
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Increasing VOUT Using Resistor
Voltage-Divider Feedback
To obtain a VOUT value above the maximum VNOM value,
a resistor voltage-divider feedback circuit can be used, as
shown in Figure 8. The equations for choosing RVO_SP,
RSP_GND, and RSN are as follows:
VO_SP OUT
SP_GND NOM
R
V1
RV
= −
=+
VO_SP SP_GND
SN VO_SP SP_GND
RR
RRR
Choose RSN ≤ 150Ω, then:
OUT
VO_SP SN
NOM
V
RR
V
=
VO_SP
SP_GND
OUT
NOM
R
RV1
V−
=
where:
VNOM = Nominal output voltage programmed with the
R_SEL table or PMBus command.
The size of the resistors should be chosen so that their
power dissipation is within their rated value. RSN can be
omitted for a slight (usually less than 1%) reduction in
accuracy.
The MAX20751 regulates and monitors the voltage from
SENSE_P to SENSE_N; therefore, the PWRGD and OVP
thresholds, droop resistance, VOUT slew rates, etc., are
all scaled by the voltage-divider feedback.
MAX20751 PMBus Interface Overview
Refer to Maxim AN5941: MAX20751 PMBus Application
Note.
Basic PCB Layout Guidelines
For electrical and thermal reasons, the second layer from
the top and bottom should be reserved for contiguous
power ground planes. It is recommended to place the
MAX20751 master away from the load current path. An
analog ground (AGND) copper polygon or plane should
be used and the MAX20751 GND pins connected to it.
The AGND (or quiet ground) polygon or plane should
extend underneath the MAX20751 on one of the inner
layers and be connected to the MAX20751 PGND pin at
one point through a single wide trace or via. AGND should
be used as a shield for the control signals (ISENSE, PWM,
SENSE_P/SENSE_N, and TS_FAULTB). The control
signals to and from the slaves are ideally the same length
for each phase.
SENSE_P/SENSE_N: These output sense lines are
important for regulation and should be routed as a
differential pair with sufficient AGND plane shielding.
ISENSE Signals: The reconstructed current signals
should be kept away from noise sources and shielded
with sufficient AGND plane.
Figure 8. Increasing VOUT Using Resistor Voltage-Divider
Feedback
R
VO_SP
R
SP_GND
V
OUT
R
SN
SENSE_P
SENSE_N
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PWM Signals: Keep away from noise-sensitive traces
and provide sufficient GND plane shielding. See Master/
Slave Placement.
TS_FAULTB: Provides AGND plane shielding.
VDD/VDD33: Place decoupling capacitors as close as
possible to the part and on the same layer.
Compensation: The compensation components should
be placed as close as possible to the master and the
amplifier inputs/outputs they connect to and away from
noisy signals.
RREF/R_SEL/RMRAMP: These components should be
placed close to the master and away from noisy
signals.
Master/Slave Placement: Position the master IC
so the side with all slave-related signals is facing the
slaves. This will avoid having noisy lines go under the
master and interact with the analog compensation nets
(Figure 9).
Internal VDD Switcher
●Place the inductor (A) as close as possible to the PVX
(phase output) pin.
●Place a 100nF MLCC very close to the VDD pin to
lter high frequencies. A 22μF to 47μF MLCC is re-
quired, and should also be placed close to the induc-
tor and the IC.
●3.3V power supply requires a small 100nF MLCC
close to the master’s pin, followed by a larger 10μF
MLCC.
●Use a PGND plane or polygon underneath the VDD
switcher components. Connect the MAX20751
PGND pin to the PGND plane or polygon. The
PGND pin should connect to the MAX20751 GND
pins through a single wide trace or via. The PGND
plane or polygon should also connect to the power
ground planes.
● To make ltering capacitors effective, place vias to
shorten their path to the PGND pin. The number of
vias should be as many as allowed by area to reduce
path resistance to PGND.
Figure 9. Board and Layout for Slave Signals
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and Internal Buck Converter
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Figure 10. MAX20751 Schematic
MAX20751 Multiphase Master with PMBus Interface
and Internal Buck Converter
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Figure 11. Smart Slave ICs Schematic
MAX20751 Multiphase Master with PMBus Interface
and Internal Buck Converter
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+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel (2.5kµ).
Figure 12. VIN and VOUT Capacitors Schematic
MAX20751 Multiphase Master with PMBus Interface
and Internal Buck Converter
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Ordering Information
PART DESCRIPTION PIN-
PACKAGE TEMP RANGE PKG.
CODE OUTLINE NO. LAND
PATTERN NO.
MAX20751EKX+ Master 36 QFN
(Type C) -40°C to +125°C K3666+1 ES AP-3565 —
MAX20751EKX+T Master 36 QFN
(Type C) -40°C to +125°C K3666+1 ES AP-3565 —
Package Outline - 36 Lead QFN [Type C]
.veR.oN coD:eltiT
ES AP-3565 0
Page 1 of 3
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Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
.veR.oN coD:eltiT
ES AP-35650
Page 2 of 3
Package Outline - 36 Lead QFN [Type C]
MAX20751 Multiphase Master with PMBus Interface
and Internal Buck Converter
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Package Information (continued)
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2015 Maxim Integrated Products, Inc.
│
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MAX20751 Multiphase Master with PMBus Interface
and Internal Buck Converter
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 9/14 Initial Release —
1 10/14 Replaced Figures 10 and 11 28, 29
2 3/15 Corrected application note number 26
Revision History
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
