EVALUATION KIT AVAILABLE MAX20751 Multiphase Master with PMBus Interface and Internal Buck Converter General Description The MAX20751 PMBusTM-compliant multiphase master IC, with extensive status and parameter monitoring, is capable of driving up to four smart-slave integrated power devices. Utilizing Maxim's smart-slave ICs, the device provides a high-density and flexible solution that can be tailored to a range of power loads used in communication equipment. Proprietary-coupled inductors, recommended to reduce the effective inductor value without excessive ripple current, results in improved transient response and reduction in the number of output capacitors required. The device incorporates current reporting, temperature monitoring, fault detection, and PMBus support. Overcurrent and overtemperature faults are detected by the individual smart slaves and faults communicated through the master IC. The highest junction temperature is reported, both before and after smart-slave regulation. The device features an integrated switching regulator that can optionally be used to supply the VDD rail for the master controller and smart-slave devices to reduce the power-rail requirements and simplify the regulator design. Benefits and Features Increased Power Density with Fewer External Components Needed * Scalable, Multiphase Solution * Compatibility with Coupled Inductors Enables Fast Transient Response and Reduced COUT * Integrated Internal Switching Regulator to Power Smart Slaves Optimized Component Performance and Efficiency with Reduced Design-In Time * PMBus-Compliant Interface for Telemetry and Power Management * Field-Programmable Memory to Allow Storage of Desired Configuration Parameters * Fault Logging Comprehensive System and IC Self-Protection Features Promote Increased Power-Supply Reliability * Overcurrent and Overtemperature * Boost Voltage UVLO * VX Short to Ground or VDDH Detection * Phase-Current Steering for Thermal Balancing 36-Pin (6mm x 6mm) QFN Package Applications Communication, Networking, Servers, and Storage Equipment * ASICs * Microprocessor Chipsets * Memory VDDQ * Other High-Current Digital ICs Ordering Information appears at end of data sheet. PWM1 Smart Slave ISENSE2 Smart Slave ISENSE3 Smart Slave ISENSE4 Smart Slave PWM2 Power Management COntroller PMBus TS_FAULTB MAX20751 PWM3 PWM4 PMBus is a trademark of SMIF, Inc. SENSE_N SENSE_P Figure 1. Basic Application Circuit 19-7080; Rev 2; 3/15 ISENSE1 VOUT MAX20751 Multiphase Master with PMBus Interface and Internal Buck Converter Absolute Maximum Ratings VDD33 Supply Voltage...............................................-0.3V to +4V VIN_UV, VR_ON and PWRGD Pins.........................-0.3V to +4V VDD Supply Voltage ...............................................-0.3V to +2.5V PVX to PGND...........................................-0.6V to VDD33 + 0.6V PMBus Pins (PMD, PMC, ALERTB).........................-0.3V to +6V SENSE_N......................................................-0.3V to VDD +0.3V SENSE_P.................................................................-0.3V to +4V R_REF, MRAMP, R_SELx, PWMx, TS_FAULTB, ISENSEx, A1_OUT, A2_x, A2B_OUT, A3_x................ -0.3 to VDD + 0.3V Junction Temperature (TJ)................. ...............................+150C Storage Temperature Range..............................-65C to +150C Peak Reflow Temperature................................................+260C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Operating Ratings VDD33 Supply Voltage......................................+2.97V to +3.63V VDD Supply Voltage.........................................+1.71V to +1.98V VIN_UV, VR_ON and PWRGD.............................-0.1V to +3.6V PMBus Pins (PMD, PMC, ALERTB).....................-0.1V to +5.5V SENSE_N..............................................................-0.1V to +0.2V SENSE_P..............................................................-0.1V to +2.5V Junction Temperature Range (TJ).......................-40C to +125C Package Thermal Characteristics TQFN Junction-to-Case Thermal Resistance (JC)...............1.7C/W This product is completely Halogen-free and Pb-free, employing SnAgCu solder balls. The product is RoHS compliant with an -e1 termination finish and is compatible with both SnPb and Pb-free soldering operations. The product is MSL classified at peak reflow temperatures that meet JEDEC JSTD-020. Electrical Characteristics (VDD = 1.71V to 1.98V, VDD33 = 3.3V 10%, TJ = +25C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 1.71 1.86 1.98 V 14 17 20 mA 2.97 3.30 3.63 V 24 130 A 1.62 1.66 V SUPPLY VOLTAGES AND CURRENTS Supply Voltage Range VDD If external VDD supply is used Supply Current IDD PWM not switching (Note 2) 3.3V Supply Voltage Range VDD33 3.3V Supply Current IDD33 No load, internal integrated switcher disabled, PMBus idle (Note 2) VDD UVLO (UNDERVOLTAGE LOCKOUT) Supply Voltage UndervoltageLockout Rising Threshold VDD_UVLO_RIS (Note 2) Supply Voltage UndervoltageLockout Falling Threshold VDD_UVLO_FAL (Note 2) 3.3V Supply Voltage UndervoltageLockout Rising Threshold VDD33_UV_RIS (Note 2) 3.3V Supply Voltage UndervoltageLockout Falling Threshold VDD33_UV_FAL (Note 2) 1.58 1.60 V VDD33 UVLO www.maximintegrated.com 2.90 2.80 2.85 2.95 V V Maxim Integrated 2 MAX20751 Multiphase Master with PMBus Interface and Internal Buck Converter Electrical Characteristics (continued) (VDD = 1.71V to 1.98V, VDD33 = 3.3V 10%, TJ = +25C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 0.380 0.390 V VIN UVLO (USING VIN_UV PIN) VIN_UV Rising Threshold VIN_UVRIS (Note 2) VIN_UV Falling Threshold VIN_UVFAL (Note 2) Delay from VIN_UV UVLO to System Shutdown tdVIN_UV_UVLO 0.318 0.328 125 V 275 ns INTEGRATED INTERNAL SWITCHER Output Valley Voltage VOUT_IIS Current Driving Capability IOUT_IIS Switcher Peak Inductor Current ILPK_IIS High-Side Switch On-Time tON_IIS 1.86 Tested at L = 2.2H, tON = 1.30s V 300 mA 1.5 Default 1.30s (Notes 1, 2) 0.52 0.65 0.78 1.04 1.30 1.56 1.52 1.90 3.28 2.20 2.75 3.30 A s VNOM (NOMINAL OUTPUT VOLTAGE AFTER STARTUP, WITHOUT DROOP) Output Voltage Range Resolution VNOM 0.5V VNOM < 1V (Note 2) VOUT_FINE_ADJ 0.500 (Note 2) 1V VNOM 1.52V (Note 2) DC Accuracy VID Set Point (VOUT FineAdjustment Voltage) Programmable through R_SEL or PMBus, direct feedback of VOUT to SENSE_P (Notes 1, 2) Programmable with PMBus, default is 0.00mV. (Notes 1, 2) 1.520 5 -0.5 -5 V mV +0.5 % +5 mV 3.25 3.75 4.25 2.00 2.50 3.00 0.75 1.25 1.75 -0.50 0.00 +0.50 -1.75 -1.25 -0.75 -3.00 -2.50 -2.00 -4.25 -3.75 -3.25 -5.50 -5.00 -4.50 mV SWITCHING FREQUENCY Nominal Switching Frequency Range Switching Frequency Tolerance fSW fSW_TOL Programmable through R_SEL or PMBus (Note 1) 300 800 kHz (Note 2) -10 +10 % OUTPUT-VOLTAGE STARTUP SLEW RATES 0.5 Output-Voltage Slew Rate After Initial Jump from 0V SVOUT Programmable through R_SEL or PMBus (Note 1) 1.25 2.5 mV/s 5 www.maximintegrated.com Maxim Integrated 3 MAX20751 Multiphase Master with PMBus Interface and Internal Buck Converter Electrical Characteristics (continued) (VDD = 1.71V to 1.98V, VDD33 = 3.3V 10%, TJ = +25C, unless otherwise noted.). PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS R_REF Reference Voltage for R_REF VR_REF (Note 2) 0.79 0.80 0.81 V A1 Amplifier Closed-Loop Differential Gain A1DM (Note 2) 2.17 2.19 2.23 V/V Error-Amplifier Closed-Loop BW CLBW 15 MHz 90 A AMPLIFIER A1 7 Positive Sense Line Current ISENSE_P VSENSE_N grounded (Note 2) Negative Sense Line Current ISENSE_N VSENSE_P grounded (Note 2) -90 Amplifier Closed-Loop Gain of A2 with feedback capacitor C2 shorted AV2 Set through external R (Note 1) 1 A2 Amplifier Open-Loop Gain AOL2 A AMPLIFIER A2 Closed-Loop Bandwidth CLBW_A2 Gain = 2 4 V/V 60 dB 10 MHz AMPLIFIER A2B A2B Amplifier Closed-Loop Gain Closed-Loop Bandwidth ADM 1 CLBW_A2B V/V 11 MHz AMPLIFIER A3 A3 Amplifier Open-Loop Gain 60 dB Gain = 2 10 MHz MRAMP Program through R at MRAMP pin (Note 1) 0.4 Positive Current Limit (Sustaining), Programmed Through RDES POCP Voltage across RDES referred to VCM, 4-phase system (Notes 1, 2) -0.658 Negative Current Limit (Sustaining) NOCP Voltage across RDES referred to VCM, 4-phase system (Note 2) 0.157 ILIM_TOL Not including the external resistor tolerance (1%) (Note 2) -10 Closed-Loop Bandwidth AOL3 CLBW_A3 MODULATOR RAMP RATE Ramp-Rate Programming Range 2 V/s -0.598 -0.538 V 0.183 0.209 V +10 % OVERCURRENT PROTECTION (OCP) Positive Current-Limit Tolerance OVERVOLTAGE PROTECTION (OVP) Tracking OVP Threshold Voltage Above VNOM (Rising) Tracking OVP Threshold Voltage (Falling) Tracking OVP Blanking Time from the End of an IDAC Transition www.maximintegrated.com (Note 2) V_TRA_OVP t_BL_OVP 205 217 mV (Note 2) 187 199 90 s Maxim Integrated 4 MAX20751 Multiphase Master with PMBus Interface and Internal Buck Converter Electrical Characteristics (continued) (VDD = 1.71V to 1.98V, VDD33 = 3.3V 10%, TJ = +25C, unless otherwise noted.) PARAMETER Umbrella OVP Threshold Voltage (Rising) Umbrella OVP Threshold Voltage (Falling) Delay Time to Respond to OVP SYMBOL CONDITIONS MIN (Note 2) V_UMB_OVP (Note 2) 2.38 td_OVP TYP MAX UNITS 2.52 2.59 V 2.45 V 1 s VR_ON (ENABLE) PIN VR_ONIH VR_ONIL VR_ON Deglitch Filter Time VR_ON (Note 2) 0.9 V (Note 2) 0.2 tFLT_VRON 2 V s PWRGD (Note 3) PWRGD Assert Threshold (Rising) PWRGD Deassert Threshold (Falling) Referenced to VNOM (Note 2) VTHR_PG Referenced to VNOM (Note 2) -225 -234 -227 PWRGD Deassert Threshold Deglitch Filter Time PWRGD High-Deglitch Filter Time Output Low Voltage -216 mV 8 td_PG VPG_OL PWRGD remains deasserted until 90s after the end of the startup IDAC transition 90 IOL = -4mA (Note 2) mV s s 0.3 V ORTHOGONAL CURRENT REBALANCING (OCR) 0 Gain OCR 1.8 Programmable through PMBus (Note 1) 3.5 4.4 PMBus (PMC, PMD, ALERTB PINS) Input High Voltage (PMC, PMD) VIH (Note 2) 1.5 VPM V Input Low Voltage (PMC, PMD) VIL (Note 2) -0.1 +0.8 V Output Low Voltage (PMD, ALERTB) VOL IOL = -4mA (Note 2) 0.4 V PMBus Resistor Pullup Voltage (PMC, PMD, ALERTB) VPM 5.5 V PMBus Clock Frequency fPMC 400 kHz +85 C 1.71 100 NONVOLATILE MEMORY PROGRAMMING Temperature Range for Programming Data into Nonvolatile Memory www.maximintegrated.com TEMPNVM_PROG Applies only to STORE_USER_ ALL PMBus command -40 Maxim Integrated 5 MAX20751 Multiphase Master with PMBus Interface and Internal Buck Converter Electrical Characteristics (continued) (VDD = 1.71V to 1.98V, VDD33 = 3.3V 10%, TJ = +25C, unless otherwise noted.). PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS PMBus MONITORING AND TELEMETRY Range of Reported Output Current as a Percentage of Positive Output Current-Limit IPLIM Error of Reported Output Current Resolution of Reported Output Current 1, 2, or 3 slaves -30 +100 4 slaves -30 +88 4-phase system at 100A, 1.0V, not including RDES tolerance (Note 2) -6 +6 IOUTREPORT % 0.5 A Update Rate of Reported Output Current 512 s Overcurrent Warning Response Time Delay After Update 1 ms Range of Reported Highest Slave Temperature Error of Reported Highest Slave Temperature Resolution of Reported Slave Temperature 4-phase system at 70A, 1.0V (Note 2) -40 +127 C -6 +6 C 1 C Update Rate of Reported Slave Temperature 3 ms Temperature Warning or FaultResponse Time Delay After Update 1 ms Scaled Voltage Range of Input Voltage at VIN_UV Pin TEMPREPORT VINSCALE 0.317 1.383 V Range of Reported Input Voltage 140/2048 for VIN_UV/VIN voltage ratio, no offset added 4.625 20.25 V Error of Reported Input Voltage Not including tolerance of resistor voltage-divider (Note 2) -2 +2 % Resolution of Reported Input Voltage 31.25 mV Update Rate of Reported Input Voltage 3 ms Input-Voltage Warning or FaultResponse Time Delay After Update 1 ms www.maximintegrated.com VINREPORT Maxim Integrated 6 MAX20751 Multiphase Master with PMBus Interface and Internal Buck Converter Electrical Characteristics (continued) (VDD = 1.71V to 1.98V, VDD33 = 3.3V 10%, TJ = +25C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MAX UNITS 0.500 1.520 V 1.000V VOUT 1.520V (Note 2) -1 +1 % 0.500V VOUT < 1.000V (Note 2) -10 +10 mV Range of Reported Output Voltage Error of Reported Output Voltage Resolution of Reported Output Voltage MIN TYP 5 mV Update Rate of Reported Output Voltage 3 ms Output Voltage Warning or FaultResponse Time Delay After Update 1 ms VOUTREPORT Range of Reported Output Power as a Percentage of (VOUT) x (IPLIM) Error of Reported Output Power POUTREPORT 1, 2, or 3 slaves 0 100 4 slaves 0 88 4-phase system at 100A, 1.0V, not including RDES tolerance (Note 2) -7 +7 % % Resolution of Reported Output Power 2 W Update Rate of Reported Output Power 3 ms Note 1: Parameters are programmable. Note 2: Specifications apply over the TJ = -40C to +105C temperature range. Note 3: PWRGD output signal is different from the PMBus POWER_GOOD signal. www.maximintegrated.com Maxim Integrated 7 MAX20751 Multiphase Master with PMBus Interface and Internal Buck Converter Typical Operating Characteristics (VIN = 12V, VOUT = 1.00V, fSW = 300kHz, Four Phases, COUT = 32 x 47F Multilayer Ceramic Capacitors, LOUT = 100nH/Phase Two Winding-Coupled Inductor for Each Pair of Phases.) OUTPUT-VOLTAGE RIPPLE - NO LOAD OUTPUT-VOLTAGE RIPPLE - 120A LOAD MAX20751 toc01 TURN-ON WAVEFORMS - NO LOAD MAX20751 toc03 MAX20751 toc02 1 1 1 2 3 2 4 2 Time/div: 2s Time/div: 200s Time/div: 2s CONDITIONS: TRIGGER ON PWM2, POSITIVE-GOING EDGE 1. VOUT: 5mV/div, 20MHz BANDWIDTH 2. PWM2: 1.00V/div, 20MHz BANDWIDTH TURN-OFF WAVEFORMS - NO LOAD MAX20751 toc04 CONDITIONS: TRIGGER ON PWM2, POSITIVE-GOING EDGE 1. VOUT: 5mV/div, 20MHz BANDWIDTH 2. PWM2: 1.00V/div, 20MHz BANDWIDTH CONDITIONS: TRIGGER ON VR_ON, POSITIVE-GOING EDGE 1. VOUT: 500mV/div, 20MHz BANDWIDTH 2. PWRGD: 2.00V/div, 20MHz BANDWIDTH 3. PWM2: 2.00V/div, 20MHz BANDWIDTH 4. VR_ON: 2.00V/div, 20MHz BANDWIDTH OUTPUT-VOLTAGE LOAD TRANSIENT RESPONSE (60A-90A) OUTPUT VOLTAGE IN HICCUP-MODE OVERCURRENT PROTECTION MAX20751 toc05 MAX20751 toc06 1 2 1 3 2 3 4 Time/div: 20ms CONDITIONS: TRIGGER ON VR_ON, NEGATIVE-GOING EDGE 1. VOUT: 500mV/div, 20MHz BANDWIDTH 2. PWRGD: 2.00V/div, 20MHz BANDWIDTH 3. PWM2: 1.00V/div, 20MHz BANDWIDTH 4. VR_ON: 2.00V/div, 20MHz BANDWIDTH www.maximintegrated.com Time/div: 20s CONDITIONS: TRIGGER ON VOUT, POSITIVE-GOING EDGE 1. VOUT: 50mV/div, 20MHz BANDWIDTH 1 Time/div: 10ms CONDITIONS: TRIGGER ON VOUT, NEGATIVE-GOING EDGE 1. VOUT: 500mV/div, 20MHz BANDWIDTH 2. IOUT: 133.3A/div, 20MHz BANDWIDTH 3. PWM2: 2.00V/div, 20MHz BANDWIDTH Maxim Integrated 8 MAX20751 Multiphase Master with PMBus Interface and Internal Buck Converter SENSE_N A1_OUT A2_IN A2_OUT A2B_OUT A3_IN A3_OUT_NORM A3_OUT_PS (Top View) SENSE_P Pin Configuration 36 35 34 33 32 31 30 29 28 27 VDD33 R_REF 1 MRAMP 2 26 PVX R_SEL0 3 25 PGND R_SEL1 4 24 PWRGD GND (Underside Pin) R_SEL2 5 23 ISENSE4 R_SEL3 6 22 ISENSE3 GND 7 21 ISENSE2 VDD 8 20 ISENSE1 19 TS_FAULTB 10 11 12 13 14 15 16 17 18 N.C. PMD PMC ALERTB VIN_UV PWM4 PWM3 PWM2 PWM1 VR_ON 9 Pin Description PIN NAME FUNCTION 1 R_REF Connect the 20k reference resistor R_REF from this pin to ground. The resistor should have 0.5% tolerance or lower, with a temperature coefficient of 25ppm/C or lower. 2 MRAMP Connect this node to ground through a resistor to program the PWM regulator modulator ramp rate. 3-6 R_SEL0-R_SEL3 7 GND Ground 8 VDD VDD Supply Voltage Connection 9 VR_ON 10 N.C. www.maximintegrated.com Programming Input. Connect these nodes to ground through a configuration resistor with 1% tolerance or lower and a temperature coefficient of 100ppm/C or lower. Input for Regulator to Enable Regulation No Connection. This node should not be connected to any other devices or components. It is connected internally. Maxim Integrated 9 MAX20751 Multiphase Master with PMBus Interface and Internal Buck Converter Pin Description (continued) PIN NAME FUNCTION 11 PMD PMBus Data I/O 12 PMC PMBus Clock 13 ALERTB Open-Drain, Active-Low PMBus Alert Output 14 VIN_UV Scaled Version of Slave VDDH Voltage. A resistor-divider on this input is used to program the input undervoltage lockout (UVLO) threshold for the slave VDDH supply. 15-18 PWM4-PWM1 19 20-23 TS_FAULTB Pulse-Width-Modulation Phase-Control Outputs for the Regulator. Connect these nodes to the input pins of the slave devices selected for the application. Connect pins for phases not populated to ground. Do not leave any PWM pin unconnected. Temperature Sensor and Slave Fault Flag. Connect this node to the TSENSE outputs of the slave ICs. This node is an analog representation of the junction temperature for the hottest slave of the regulator during normal operation and is also used by the slave devices to report faults (a fault condition is asserted low). Phase Current-Sense Inputs. Connect these nodes to the ISENSE outputs of the slave devices. ISENSE1-ISENSE4 Ground the pin if not in use (the corresponding RPH resistor should not be connected to ISENSE when ISENSE is connected to ground) to minimize noise into the device. 24 PWRGD 25 PGND Power-Good Output for the Regulator. This node indicates whether the output voltage is within regulation. This open-drain output should be pulled high externally with a resistor of approximately 10k. Power Ground. Connect this node to power ground. 26 PVX 27 VDD33 Internal Switcher Switching Node. This node should be connected to an inductor for correct operation. 28 A3_OUT_PS Phase-Shedding Feature (disabled in the MAX20751). This pin must be connected to A3_OUT_ NORM with a short trace or a 0 resistor. 29 A3_OUT_NORM Phase Current-Loop Amplifier Output for the Regulator. Must be connected to A3_OUT_PS with a short trace or a 0 resistor. 30 A3_IN 31 A2B_OUT 32 A2_OUT 33 A2_IN 3.3V Supply for the IC and Internal Switcher Phase Current-Loop Amplifier Negative Input This node has the same value as A2_OUT during normal operation, but has programmable positive and negative voltage clamps that limit the maximum positive and negative output current. Voltage-Loop Amplifier Output Voltage-Loop Amplifier Negative Input 34 A1_OUT Differential Error-Amplifier Output 35 SENSE_N Negative Remote-Voltage Sense 36 SENSE_P Positive Remote-Voltage Sense www.maximintegrated.com Maxim Integrated 10 VIN_UV NC ALERTB PMC PMD VR_ON PWRGD TS_FAULTB SENSE_P SENSE_N VDD OVP_thresh O/C detector PMBus W Scaling VR_UV Charge Pump PMBus Interface VDD VDD 11 bits SFR Interface DACnom VIN_uvlo OTP BLK R R DIGITAL Core Vcm GND mclk Oscillator R_REF Bias Generation TS_FAULTB V(Vout) V(VIN_UV) V(Iout) Phase Oscillator digGND and anlog GND uC_clk timing reference IVT_ADC I_ADC Freq req<1:0> OTP_ready reset Vcm A2_IN A2_OUT 3.3V UVLO A2B A2B_OUT Power Sequencing Switcher Control VX Detect 3V UVLO VREF VX tristate driver IRAMP Vcm A3 x4 R_PS switch A3_OUT_NORM capacitor initialization A3_IN OCR PWM LOGIC 4 Phase Gen 3.3V rdy SW_ONTIME<0:1> BG_CR BG_OK_3V PWDN Shutdown<5:0> phase_clock<5:0> Ramp Current Generator Bandgap, Bias, VDD PORB/UVLO Phase Detect Logic Threshold Generator PMBus Write num_phases_active A2 capacitor initialization R_SEL<3:0> phase_gen Threshold Generation num_phases_present start num_phases_active 3.3V rdy en OVP PWRGD OCP 2R A1 2R A1_OUT early turn-on www.maximintegrated.com Umb_OVP OTP Interface PGND PVX VDD33 MRAMP PWM<4:1> ISENSE<4:1> O/C detector 4 Threshold Mux PMBus Write A3_OUT_PS MAX20751 Multiphase Master with PMBus Interface and Internal Buck Converter Block Diagram 3.3V Driver Maxim Integrated 11 MAX20751 Multiphase Master with PMBus Interface and Internal Buck Converter 95% 90% 85% VOUT = 0.8V VOUT = 1.0V VOUT = 1.2V VOUT = 1.5V VOUT = 1.8V 80% 75% 70% 0 10 20 30 40 50 60 70 80 90 100 110 120 130 Figure 2. System Efficiency: 4-Phase,100nH/Phase-Coupled Inductors, 350kHz Switching Frequency (VIN = 12V) www.maximintegrated.com Maxim Integrated 12 MAX20751 Theory of Operation The MAX20751 master IC provides a high-frequency, highly integrated compact solution for high-performance, lowvoltage power conversion (with PMBus interface). The basic system architecture consists of a single-rail master controller and up to four smart-slave devices. These ICs, along with a small number of external components, provide a complete solution for single-rail voltage regulation. The master IC contains a pulse-width-modulation (PWM) control circuit, PMBus interface, and multiphase control circuits for low-loss operation over a wide range of load currents. The applicable smart-slave ICs utilize the full benefits of a synchronous rectification topology. Both the top and bottom power FETs are integrated on-chip, with no external power components (MOSFETs or Schottky diodes) required. Each smart-slave device contains temperature and current monitoring. PWM signals are generated in the master IC and sent to the slaves. Current-sense and temperature feedback signals are generated in the slaves and sent to the master. The smart-slave ICs have integrated lossless currentsense technology. This current-sense technology provides accurate current information that is not affected by temperature, process variation, or tolerances of passive elements such as the output inductor, resistors and capacitors, and NTCs used in other systems to extract current information. With this approach, a currentsense signal is fed back to the master as a current instead of a voltage, as is the case with DCR and other forms of current sensing. This allows very robust system feedback of current, with better noise immunity than other methods. The current information can be used to control the load line precisely and in the calculation of real output-power measurements. Highly precise current information removes the challenges of meeting load-line specifications, especially at light load, an area known to challenge DCR current sensing due to the low signal levels and tolerances involved. The output voltage, output-voltage turn-on slew rate, PMBus address, and PMBus output-current gain are hardware programmable using configuration resistors, as discussed in the Configuration section. An internal integrated switching regulator allows creation of the VDD supply from the VDD33 supply, with the addition of an LC filter. www.maximintegrated.com Multiphase Master with PMBus Interface and Internal Buck Converter Control Architecture Figure 3 shows the internal amplifier stages of the master and how phase-current information is used to generate the phase-control signals, as well as provide accurate current reporting. The master IC contains multiple amplifier stages and one duty-cycle modulator for each phase, to allow independent control of the high-side MOSFET on-time according to each individual phase current. The first amplifier stage (A1) in Figure 3 is a differential amplifier, the output being the error between the DAC reference voltage and the differential voltage-sense lines multiplied by a factor of 2.19. This stage enables true remote voltage sensing, and its differential structure provides high common-mode rejection ratio to protect from any noise present at the processor ground. The second amplifier stage (A2) provides voltage-loop compensation, with its DC gain used to set the load line of the voltage regulator. The A2 amplifier is followed by a clamping circuit and buffer amplifier (A2B) to provide overcurrent protection (OCP). The output of amplifier A2B is converted to a current through the resistor (RDES) and represents the desired total system current (IDES), which sets the target for the current loop. The third amplifier (A3) acts as a current-error amplifier, as it receives the current command (through RDES) and each individual sensed current from the smart-slave ICs (through resistors RPH1, RPH2, and RPH3, as shown in Figure 3. This stage has an integrator connection. The very large DC gain of the A3 stage guarantees that the total load current equals the current command (IDES) in steady state. As a result, the load line of the voltage regulator is set by the gain of the voltageloop amplifier (A2). Zero load line can be achieved by configuring the amplifier as an integrator by placing capacitor C2 in series with R2, as shown in Figure 3. The system also offers programmable modulator ramprate stability and noise immunity, set by connecting a resistor between the MRAMP pin and ground. This ramp determines the duty-cycle modulator gain and is used to tune the current-loop compensation. Loop compensation is implemented by adding series or parallel RC networks across the voltage-loop and current-loop amplifiers (A2 and A3), respectively. For the voltage loop, lead compensation can be added by using a series RC network across the R1 resistor, as shown in Figure 3 (RLD_A2 and CLD_A2). Lag compensation can be added by adding a series RC network across the R2-C2 network resistor. Compensation for the current loop is achieved by placing a series RC network across the current-loop amplifier feedback (RINT-CINT, in Figure 3). This network provides extremely high gain at low frequency, which guarantees tight current regulation (i.e., the output current is very close to the current command). Maxim Integrated 13 MAX20751 Multiphase Master with PMBus Interface and Internal Buck Converter Integrated 1.8V Switching Regulator Equation 2: The MAX20751 master IC features an integrated switching regulator that provides the bias current to the master controller and to the smart-slave ICs (both core analog/ digital circuits and gate drive). IMAX_AVE = If load current is higher than IMAX_AVE, the VDD voltage drops. If VDD drops below the falling UVLO threshold, the device resets. This regulator enables efficient power conversion from the 3.3V supply at both light load and heavy load using a pulse-frequency-modulation (PFM) mode of operation. The external LC filter for this regulator is extremely small and inexpensive, as it only requires a chip inductor and small case-size ceramic capacitors. The control scheme adopted here is voltage mode constant on-time with the inductor always operated in the discontinuous-conduction mode (DCM) of operation, providing an inherent currentlimiting protection as well as soft-start capability. Details of the integrated regulator can be seen in the Block Diagram. The PGND pin should connect to the GND pins through a single wide trace or via. The on-time (tON) is programmable using the PMBus. Table 1 shows the programmable on-times. Before VDD has risen above the rising undervoltagelockout (UVLO) threshold, the lowest on-time of 0.64s is used. When VDD has risen above both the rising and falling UVLO thresholds, the switcher uses the programmed on-time. The default value is 1.30s. The switcher becomes active when VDD33 voltage has risen above its rising UVLO threshold. The inductor (LPVX) must be able to support the maximum peak current without saturating significantly, since the inductor impedance is what provides the current limit. The maximum peak current occurs at startup from zero output voltage. In order to achieve simple average-output current-limiting protection, this converter is forced to stay in DCM mode by only allowing high-side turn-on when the current reaches zero. The peak current in the inductor is given in Equation 1. The output-voltage peak-to-peak ripple depends on the capacitor (CVDD). The worst-case ripple occurs at light load and is given in Equation 3. Equation 3: V IP VP-P= x DD33 t ON 2C VDD VDD Equation 1: IP = VDD33 - VDD t ON 2L PVX VDD33 - VDD t ON L PVX where: LPVX is the switcher inductor where: VP-P should be 30mV or less The maximum average current is given by Equation 2. Table 1. On-Time Selection Table ON-TIME (s) 0.64 1.30 (Default) 1.91 2.76 Slave1 Slave2 Slave3 ISENSE ISENSE ISENSE Phase Control (One Phase Shown for Clarity) RFILT3 CPAD3 OCP CLAMP and Buffer Amplifier CINT R2N OCR VCM A2B A1_OUT A1 A3_IN R2 C2 A2_OUT R1P RLD_A2 ISNS1 RDES A2_IN R1 SENSE_P ISNS2 A2B_OUT A2 SENSE_N RINT OCP CLAMP VCM R1N Vx ISNS3 RPH3 RPH1 IDAC RPH2 VDD IDES VCM ph_clk A3 A3_OUT_NORM CRR IRR S Q R CLD_A2 R2P Figure 3. Control Architecture www.maximintegrated.com Maxim Integrated 14 MAX20751 Multiphase Master with PMBus Interface and Internal Buck Converter Startup and Shutdown Operation CDD33 PGND VDD Switcher VDD33 PVX LPVX CDD VDD Figure 4. Integrated Switcher Circuit The control method regulates the valley voltage. The peak voltage is the valley voltage plus the peak-to-peak ripple voltage. The current from the VDD33 supply occurs in pulses of charge given by Equation 4. Equation 4: I Q VDD33 = P t ON 2 where: IP is the peak current Capacitor CDD33 at the VDD33 pin should be chosen to supply the peak current and charge without too much voltage change. A ceramic capacitor of at least 10F is recommended. To estimate the VDD33 current using the integrated switching regulator, assume a minimum efficiency of 80% for the integrated switching regulator. For example, if the maximum total master and slave IC current from VDD is 175mA, VDD = 1.9V, and VDD33 = 3.3V, then the VDD33 current for the integrated switching regulator is (175mA x 1.9V)/(3.3V x 0.80) = 126mA. To estimate the total VDD33 current, also include the PMBus resistor pulldown current if operated from VDD33. For example, if 2.15k pulldown resistors are used from the PMC, PMD, and ALERTB pins to VDD33, then the maximum PMBus current is 3 x 3.3V/2.15k = 4.6mA. Therefore, the total VDD33 current for the integrated switching regulator and PMBus is, approximately, 131mA. The integrated switching regulator can be disabled by removing LPVX and connecting a 10 resistor from PVX to VDD33. An external supply is then applied to VDD. www.maximintegrated.com When VDD and VDD33 are above their rising UVLO thresholds, the device is enabled and goes through an initialization and phase-detection procedure. Configuration resistors are read and external resistors checked for valid values. Any faults will prevent the output voltage from turning on. The PMBus communication and telemetry are then enabled. The VIN_UV voltage must be above its rising UVLO threshold for the output voltage to turn on. If the output voltage is programmed to below 0.25V through the PMBus VOUT_COMMAND, the output is disabled. Programming the output voltage to any other allowable voltage using the PMBus VOUT_COMMAND allows the output voltage to turn on. Depending on how the voltage-regulation enable is configured, a VR_en signal from VR_ON and/or the PMBus OPERATION command may also be required for the output voltage to turn on. The default configuration for the VR_en signal is the VR_ON signal at the high logic level, with no PMBus command needed. When the VIN_UV voltage is above its rising UVLO threshold and the proper VR_en signal, if required, has occurred, the output voltage turns on after the PMBus programmable TON_DELAY time. The default TON_DELAY time is 0ms. After the output voltage has reached its nominal value, the PWRGD signal is asserted. The startup sequence caused by VR_ON going high is shown in Figure 5. When shutdown occurs, the master IC causes the VX nodes of the slaves to stop switching, which then causes the output voltage to turn off. The PWRGD signal is deasserted and is actively pulled low. Depending on how the voltage-regulation enable is configured, the output voltage can be turned off using the VR_en signal from VR_ON and/or the PMBus OPERATION command. Depending on the PMBus configuration, the output turns off immediately or with sequencing. When the output turns off with sequencing, there is a delay time determined by the PMBus programmable TOFF_DELAY command and then VOUT ramps down with a turn-off slew rate that is the same as the turn-on slew rate for turn-on slew rates of 1.25mV/s, 2.5mV/s, and 5mv/s. For turnon slew rate 0.5mV/s, if sequencing is used, the delay time is followed by an immediate turn-off (no slew ratecontrolled VOUT ramp-down). The default TOFF_DELAY time is 0ms. Note that when VOUT ramps down, energy Maxim Integrated 15 MAX20751 Multiphase Master with PMBus Interface and Internal Buck Converter VDD TA: Initialization time needed before startup can begin. Maximum 6ms. TA VIN_UV VDD33 VR_en Delay from VR_ON to VR_en: Typical 2s. Delay from last ACK of PMBus OPERATION command to enable VOUT to VR_en: 75s. VOUT PWRGD TC: Time from VR_en signal (from VR_ON or PMBus) to VOUT startup with TON_DELAY. VOUT TURN-ON SLEW RATE TC TF TYPICAL TC 1.25mV/s, 2.5mV/s, or 5mV/s 200s 0.5mV/s 4ms TF: Time from VOUT reaching VNOM to PWRGD assertion. Typical 90s. Note: For the 0.5mV/s setting, TC:will increase if there is a nonzero prebias voltage on VOUT. Also, the TON_MAX_FAULT_LIMIT and TON_MAX_FAULT_RESPONSE commands do not work for the 0.5mV/s setting. Figure 5. Startup Sequence may be delivered from VOUT to VIN. The VIN capacitors should be sized to absorb this energy to prevent a large increase in the VIN voltage. The output voltage can be turned off by the VIN_UV voltage going below the VIN_UV falling UVLO threshold. This is logged as a hardware fault. The output voltage can be turned off by programming the output voltage below 0.25V using the PMBus VOUT_COMMAND. The turn-off in this case is also determined by the PMBus configuration. The VIN_UV UVLO thresholds should be higher than the corresponding smart-slave IC's VDDH UVLO thresholds to prevent a slave fault from occurring, which could potentially prevent the output voltage from turning back on. If this occurs, the system may need to be reset by bringing the VDD or VDD33 supplies below their falling UVLO thresholds. If the VDD or VDD33 supplies go below their falling UVLO thresholds, the output voltage is turned off and the system is reset. www.maximintegrated.com The shutdown sequence caused by VR_ON going low is shown in Figure 6. Maxim Integrated 16 MAX20751 Multiphase Master with PMBus Interface and Internal Buck Converter Orthogonal Current Rebalancing (OCR) Phase-current imbalance can occur due to highfrequency loading transients. The purpose of the OCR circuit is to reduce phase-current imbalance. VDD This is accomplished by modifying the output of the A3 amplifier for each individual phase (k). Instead of the A3 amplifier output voltage being fed directly to the PWM comparator of a phase, a control voltage (VCk) is used. The equation for VCk is given in Equation 5. VDD33 VIN_UV Delay from VR_ON to VR_EN: Typical 2s. VR_en Delay from last ACK of PMBus OPERATION command to disable VOUT to VR_EN: 10s. VOUT PWMi TY PWRGD TZ TY: Time from VR_en signal (from VR_ON or PMBus) to VOUT shutdown with TOFF_DELAY=0ms. Typical 2s for immediate shutdown. For 1.25, 2.5, and 5mV/s slew rate: Typical 200us for sequenced shutdown. TZ: Time from VR_EN to PWRGD LOW . Maximum 9s. Figure 6. Shutdown Sequence Droop and Load-Line Regulation If the A2 amplifier series R2-C2 network is replaced by resistor R2 only, the MAX20751 provides accurate output load line over the entire range of output currents. The load line is set by the combination of the R1, R2, and RDES resistors. Switching Frequency and Output-Voltage Turn-On Slew Rate The switching frequency and output voltage turn-on slew rate are programmable using configuration resistors. See the Configuration section. They are also programmable using the PMBus. www.maximintegrated.com Equation 5: 1 N VCk = VO3 - G OCR VRPHk - VRPHi N i=1 where: VRPHk = Voltage on resistor RPHk (a voltage proportional to the current in phase k) VO3 = A3_OUT_NORM voltage N = Total number of phases GOCR = Gain of the OCR circuit VCk = Voltage fed to the phase k PWM comparator instead of the A3 amplifier output voltage The difference between the current of a phase k from the average current (with some gain GOCR) is subtracted from VO3 to determine the control voltage (VCk). If the current in any phase is greater than the average of all the phases, then the corresponding VCk voltage will be less than VO3 and the subsequent PWM pulse for that phase shorter, thus preventing further phase-current imbalance. The default gain (GOCR) is 1.8. Input Voltage Undervoltage Lockout (UVLO) Using the VIN_UV Pin The VIN_UV pin on the master IC is connected to the middle point of a voltage-divider from the slave VDDH (power input rail) to ground. This pin provides an externally programmable input supply UVLO and sensing for the PMBus VIN telemetry. The UVLO function is provided by comparing the VIN_UV voltage to internal references with a comparator. When the VIN_UVLO voltage exceeds the rising threshold, the system is allowed to operate and the falling reference voltage is then used as a disable point for built-in hysteresis. See the Electrical Characteristics table for more details. Maxim Integrated 17 MAX20751 Multiphase Master with PMBus Interface and Internal Buck Converter Figure 7 shows the VIN_UV circuit. Resistors RIN and RGND form a voltage-divider that scales the VIN voltage to the VIN_UV pin. The scale factor (VIN_RATIO) is given by Equation 6. VIN_RATIO is programmable using the PMBus. The default value is (140/2048) = 0.06836. Equation 6: VIN_RATIO = R GND R GND + R IN RGND||RIN should be approximately 2k with capacitor CIN_UV = 100pF. It is suggested to use 1% tolerance resistors with the values RGND = 2.15k and RIN = 29.4k. The value for VIN_RATIO should be less than or equal to 140/2048. Phase Population Order Depending on the total number of phases in the system, specific phase positions must be populated, while the others must be deactivated by connecting a 0 resistor between the MAX20751's phase-control pins (PWMk) of the inactive phases and ground (Table 2). The phase number is defined by the PWMx pin name (e.g., phase 2 is driven by PWM2). For example, for 2-phase operation, only phases 2 and 1 are used; therefore, pins PWM4 and PWM3 should each be connected to GND with 0 resistors. For 3-phase operation, PWM4 should be connected to GND with a 0 resistor. For single-phase operation PWM4, PWM3, and PWM1 should each be connected to GND with 0 resistors. If the wrong PWMk pins are connected to GND with 0 resistors, a configuration fault occurs in the fault-checking procedure (occurring prior to VOUT startup) and operation is halted. Protection And Monitoring The master IC includes multiple protection circuits to protect the regulator and load, and to monitor the output voltage, as described in the following sections. Fault Detection when VDD and VDD33 are Initially Applied When VDD and VDD33 are initially applied and at their proper levels, the master IC checks the following resistor values and connections and if detected as being outside the correct range or open, an error is flagged and the regulator will not start regulation: RMRAMP RREF VIN SENSE_P Open RIN PWRGD (Power-Good) Pin VIN_UV The PWRGD output (different from the PMBus POWER_ GOOD signal) is an active-high, open-drain output used to show that the output is settled at its commanded voltage. The output goes high after a fixed delay, after the end of the output-voltage startup transition, assuming the output voltage is above the PWRGD threshold. It is deasserted when any of the following occurs: RGND CIN_UV Figure 7. VIN_UV Pin Voltage-Divider Circuit Table 2. Phase Population Positions NUMBER OF POPULATED PHASES POSITIONS TO BE POPULATED (BY FIRING SEQUENCE) 1 2 2 2, 1 3 2, 1, 3 4 2, 4, 1, 3 www.maximintegrated.com The output voltage drops below the threshold, relative to the nominal voltage, for any reason. An OVP fault is detected. An OCP fault is detected when the mode is set to hiccup mode and the regulator shuts down the output voltage during the shutdown part of the hiccup cycle. In constant current-limit mode, the PWRGD signal is based on the PWRGD voltage threshold only. The output is disabled. Maxim Integrated 18 MAX20751 Multiphase Master with PMBus Interface and Internal Buck Converter Overcurrent Protection (OCP) System OCP is based on a fixed voltage threshold for the voltage across the RDES resistor. The overcurrent threshold is therefore set by selecting an appropriate value of RDES for the design. The voltage threshold is scaled internally, depending on the number of active phases (i.e., the voltage threshold is a fixed per-phase value). The OCP trips when the peak voltage over RDES reaches the inception value and remains tripped down to the nominal/sustaining value (i.e., the values shown are the sustaining currents and not the inception point, which is 5% higher). Negative (sinking) OCP is automatically set to 30% of the positive value. The OCP is based on the instantaneous voltage over RDES, and a small ripple voltage reflecting the output-voltage ripple may be present. If the instantaneous commanded current (output of amplifier A2) reaches the inception voltage, the commanded current is immediately clamped to the sustaining value. If the commanded current drops below the sustaining value, it must once again reach the inception point before clamping commences. An overcurrent fault is logged in the fault log if clamping continues for 5ms, to ensure that only periods of continuous overloads are recorded as faults. Table 3. Master Faults MAX20751 PROTECTION MAX20751 OUTPUT SIGNAL(S) SHOWING FAULT SYSTEM SHUTDOWN SYSTEM LATCHED OFF? LOGGED IN FAULT LOG? Resistor Out-of-Range Detected at Startup PWRGD low System does not start Yes Yes OCP: Hiccup or CCM PWRGD low (if output drops below threshold) No No Yes (after 5ms) PWRGD low Yes Yes Yes PWRGD low (if output drops below threshold) Yes No Yes PWRGD low No No No No Fixed (Umbrella) or Tracking OVP VIN_UV UVLO Output Undervoltage VDD UVLO PWRGD low Yes No (system in reset) VDD33 UVLO PWRGD low Yes No (system in reset) No Table 4. Effects of Slave Faults MAX20751 OUTPUT SIGNAL SHOWING FAULT SYSTEM SHUTDOWN SYSTEM LATCHED OFF* LOGGED IN FAULT LOG None No No Yes Slave Sourcing OCP Current Shutdown PWRGD low Yes Yes (through slave) Yes Slave OTP Shutdown (Sent to Master through Slave TS_FAULTB Low) PWRGD low Yes Yes (through slave) Yes Slave Boost UVLO (Undervoltage Lockout on Boost Supply) PWRGD low Yes No Yes Slave VX Short-to-Ground or VDDH PWRGD low Yes Yes (through slave) Yes SLAVE FAULT Slave Cycle-by-Cycle OCP (Sinking or Sourcing Current) *Note: "Yes (through slave)" refers to the fact that the slave latches in this condition and therefore the system latches. Once the slave fault is cleared by cycling its power, the system can restart. This table shows the effect on the system. www.maximintegrated.com Maxim Integrated 19 MAX20751 Multiphase Master with PMBus Interface and Internal Buck Converter Three modes of operation are provided for positive (sourcing) OCP: shutdown, constant current, and hiccup (default); negative OCP is always constant current. The mode can be changed using PMBus commands. If hiccup OCP mode is selected, when the OCP is exceeded, the system will deliver the maximum programmed sustaining current for 5ms before shutting down and waiting 45ms before restarting. This cycling continues until the commanded current falls below the programmed value. Should constant-current mode be selected, the system tries to regulate at the OCP sustaining current until the commanded current falls below the sustaining value. The upper threshold of current delivery is the OCP inception point and, once this level is reached, the system folds back to the sustaining level (the programmed value) to deliver constant current indefinitely. The shutdown mode is similar to the constant-current mode but shuts down VOUT after 5ms. The VOUT voltage can be enabled again by using the VR_ON signal and/or the OPERATION PMBus command. Overvoltage Protection (OVP) Two separate OVP circuits are included, one based on the programmed nominal output voltage, the other on an "umbrella" fixed value. If either is tripped, an OVP fault is recorded, PWRGD is deasserted, and the system stops regulating. OVP faults can only be cleared by toggling the VDD or VDD33 supply rail. Undervoltage Lockout The master IC includes three UVLO circuits, VDD rail, VDD33 rail and VDDH (i.e., VIN). VIN is monitored through an external resistor-divider to bring the voltage down to within the operating range of the VIN_UV pin. If a VIN UVLO is detected, the system stops regulating and indicates an input-voltage fault. Once the input voltage rises above the rising threshold, the IC reinitiates and follows the same startup procedure as if enabled by VR_ON. Configuration Determining the Optimum Number of Phases, IOUTMAX, and Overcurrent Protection The typical starting point for a voltage-regulator design is to choose a value of maximum output current (IOUTMAX). The value of IOUTMAX is determined by the MAX20751 system overcurrent-protection (OCP) setting and is set to 85% of this setting. Therefore, a target minimum system OCP rating can easily be determined based on IOUTMAX. Once this value is known, the area available, smart-slave part numbers to be used, and the desired performance Table 5. Selection of RDES for Overcurrent Limit and Maximum Output Current IOUTMAX = 0.85 IOCP 1-PHASE OCP (A) 2-PHASE OCP (A) 3-PHASE OCP (A) 4-PHASE OCP (A) RDES () 25 50 75 100 604 27.3 54.7 82 109.3 549 29.7 59.3 89 118.6 511 32 64 96 128 464 34.3 68.6 103 137.3 432 36.7 73.3 110 146.6 412 39 78 116.9 155.9 383 41.3 82.6 123.9 165.2 365 43.6 87.3 130.9 174.6 340 46 91.9 137.9 183.9 324 48.3 96.6 144.9 193.2 309 50.6 101.3 151.9 202.5 294 53 105.9 158.9 211.8 280 55.3 110.6 165.9 221.2 274 57.6 115.2 172.9 230.5 261 60 119.9 179.9 239.8 249 www.maximintegrated.com Maxim Integrated 20 MAX20751 Multiphase Master with PMBus Interface and Internal Buck Converter versus cost should all be considered, with the number of phases and smart-slave devices determined. Efficiency curves and ratings shown on the respective smart-slave data sheets can be used for this purpose. If any phases aren't used, their corresponding PWMx pins should be connected to GND with 0 resistors, as discussed in the Phase Population Order section. Selecting RDES With the number of phases and part numbers known, RDES should be selected to give the correct overcurrent-protection (OCP) value. The OCP value is set by RDES, in that the master IC uses a fixed value of 150mV per phase. Since RDES is also used by Table 6. Using R_SEL3 to Set the VOUT Slew Rate and Switching Frequency VOUT SLEW RATE (V/ms) 1.25 2.5 5 0.5 www.maximintegrated.com fSW (kHz) R_SEL3 () 300 0 350 17.8 400 33.2 450 48.7 500 64.9 600 80.6 700 95.3 800 115 300 133 350 154 400 178 450 200 500 226 600 249 700 274 800 301 300 332 350 365 400 402 450 432 500 464 600 499 700 536 800 576 300 619 350 665 400 715 450 768 500 825 600 887 700 953 800 1020 Maxim Integrated 21 MAX20751 Multiphase Master with PMBus Interface and Internal Buck Converter the PMBus telemetry circuitry to measure the output current (IOUT), the value of RDES must be selected from Table 5 of standard 1% resistors. For example, to choose an output-voltage slew rate of 0.5V/ms and a switching frequency of 350kHz, R_SEL3 = 665. For example, if an IOUTMAX of 170A is required, IOCP must be a minimum of 170/0.85 = 200A. If a 4-phase design has been selected, looking in the 4-Phase OCP column, we see the next highest value for IOCP is 202.5A and requires the use of RDES with a value of 294, which gives a nominal reported IOUTMAX of 0.85 x 202.5 = 172A (IOUTMAX is rounded to an integer value). Care should be taken with tolerance and rounding to ensure that the required IOUTMAX is met. Using Configuration Resistors to Program the Output Voltage, PMBus Address Lowest 3 Bits, and IOUT Telemetry for the RDES Value Being Used Using Configuration Resistors to Program the Output-Voltage Slew Rate and Switching Frequency R_SEL3 is used to set the output-voltage slew rate and switching frequency. Table 6 shows the output-voltage slew rates, switching frequencies, and corresponding values for R_SEL3. R_SEL3 has 32 possible values, with each value corresponding to a distinct pairing of slew rate and switching frequency. Table 7 shows the parameter values and corresponding configuration resistor values used to program the output voltage, PMBus address lowest 3 bits (PMAD[3:1]), and PMBus IOUT telemetry circuitry with the RDES value used in the overcurrent-limit circuit. R_SEL2 and R_SEL1 are the configuration resistors used to set the output voltage. The output voltage is the sum of the two voltages chosen by R_SEL2 and R_SEL1. R_SEL1 and R_SEL0 are the configuration resistors used to set the lowest 3 bits (PMAD[3:1]) of the entire PMBus address (PMAD[7:1]). The upper 4 bits (PMAD[7:4]) are constant at the value 1110b. R_SEL0 is the configuration resistor used to program the PMBus IOUT telemetry circuitry with the RDES value being used in the overcurrent-limit circuit. Table 7. Using R_SEL2, R_SEL1, and R_SEL0 to Set the Output Voltage, Set the Lowest PMBus Address Bits, and Program the IOUT Telemetry with the RDES Value Being Used VOUT R_SEL2 PMAD VOUT R_SEL1 R R_SEL0 PMAD3 DES (V) () [2:1] (V) () () () VOUT R_SEL2 PMAD VOUT R_SEL1 R R_SEL0 PMAD3 DES (V) () [2:1] (V) () () () 0 -0.005 0 604 0 0.890 332 -0.005 332 604 332 17.8 0.000 17.8 549 17.8 0.930 365 0.000 365 549 365 33.2 0.005 33.2 511 33.2 0.970 402 0.005 402 511 402 0.010 48.7 464 48.7 1.010 432 0.010 432 464 432 48.7 64.9 00 10 0.015 64.9 432 64.9 1.050 464 0.015 464 432 464 80.6 0.020 80.6 412 80.6 1.090 499 0.020 499 412 499 0.490 95.3 0.025 95.3 383 95.3 1.130 536 0.025 536 383 536 0.530 115 0.030 115 365 115 1.170 576 0.030 576 365 576 0.570 133 -0.005 133 340 133 1.210 619 -0.005 619 340 619 0.610 154 0.000 154 324 154 1.250 665 0.000 665 324 665 0.650 178 0.005 178 309 178 1.290 715 0.005 715 309 715 0.690 200 0.010 200 294 200 1.330 768 0.010 768 294 768 0.730 226 0.015 226 280 226 1.370 825 0.015 825 280 825 0.770 249 0.020 249 274 249 1.410 887 0.020 887 274 887 0.810 274 0.025 274 261 274 1.450 953 0.025 953 261 953 0.850 301 0.030 301 249 301 1.490 1020 0.030 1020 249 1020 01 0 11 1 Note 1: Selecting VOUT below 0.25V disables the output voltage. Note 2: RDES defines IOCP, IOUTMAX, and the IOUT PMBus telemetry. www.maximintegrated.com Maxim Integrated 22 MAX20751 Multiphase Master with PMBus Interface and Internal Buck Converter Each R_SELx resistor has 32 possible values, with each value corresponding to one or more programmable parameters. For example, to program 1.000V output voltage, PMAD[3:1] = 011b, and RDES = 294, use: R_SEL2 = 402 (0.970V), R_SEL1 = 1020 (PMAD[2:1] = 11b, 0.030V), R_SEL0 = 200 (PMAD3 = 0b, RDES = 294) This results in the output voltage = 0.970V + 0.030V = 1.000V, PMAD[3:1] = 011b, and RDES = 294. The output voltage can also be programmed using the PMBus. Note that the output voltage is disabled if it is set below 0.25V through the PMBus. Inductor Phase-Current Ripple For coupled inductors, the inductor peak-to-peak phasecurrent ripple can be calculated from Equation 7 (which assumes perfect coupling for coupled inductors, and duty cycle 1/N). Equation 7: IPHPP = VOUT f SWL 1 V - OUT VIN n CW where: IPHPP = Peak-to-peak phase-current ripple in the inductor fSW = Switching frequency L = Inductance per phase nCW = Number of coupled windings VIN = Input voltage VOUT = Output voltage In practice, the coupling will not be perfect, but good coupling can be achieved, with the actual ripple current close to what is calculated by the equation. The output current ripple is given by Equation 8, assuming duty cycle 1/N. Equation 8: = IPP VOUT 1 VOUT N - f SWL N VIN where: IPP = Peak-to-peak output-current ripple L = Inductance per phase N = Number of phases www.maximintegrated.com Output Capacitance Calculation One criterion for determining the value of the output capacitance (COUT) is the maximum allowable outputvoltage overshoot (VOST) during unloading transients. For a maximum unloading current step (I) and maximum allowed output-voltage overshoot change (VOST), the required output capacitance is given by Equation 9. Equation 9: L N C OUT 2( VOST ) VOUT ( I) 2 where: L = Inductance per phase N = Number of phases VOUT = Nominal output voltage For example, in a case where allowable overshoot is the limiting factor for a 3-phase system with 250nH of inductance per phase, 1.0V output, maximum current step of 50A, and maximum allowable overshoot of 100mV, the minimum COUT theoretically required is 1042F. Selecting a higher value gives good design margin against component variation and effective capacitance loss due to voltage bias. Bleed Resistor A small bleed resistor of approximately 100 should be connected between the output of the regulator and ground to ensure that the output capacitors are discharged shortly after the output is disabled. The resistor should be sized so that when the maximum expected output voltage is applied, the resistor's power dissipation is sufficiently below its rated power dissipation. Droop and No-Droop Operation The device provides accurate output-droop resistance over the entire range of output currents. The RDROOP is set by the combination of the R1, R2, and RDES resistors, according to Equation 10. Equation 10: R DROOP = R 1 R DES R 2 2.19A I where: AI = Slave current gain factor R1 = Having a typical value of 600 to 800. The R2/R1 should be a minimum of 0.45 Maxim Integrated 23 MAX20751 Multiphase Master with PMBus Interface and Internal Buck Converter If R2/R1 < 1, then R1 should be between 600 and 800, R2 should be 353, minimum, and the ratio of R2/R1 should be 0.45, minimum. If R2/R1 > 1, then R1 should be between 400 and 800. R2 should be 400, minimum. The ramp rate (SRAMP) can be determined from the switching frequency (fSW), steady-state ramp voltage (VRAMPD), and duty cycle (D = VOUT/VIN), according to Equation 14. Equation 14: No-droop operation can be achieved by adding capacitor C2 in series with R2 in the A2 stage, according to Equation 11. Equation 11: C2 L C N OUT R2 Above the frequency (Equation 12), the voltage-regulator impedance approaches RDROOP. Equation 12: f2 = where: N = Number of phases The voltage-regulator impedance approaches: R PH R INT + N R DROOP R INT up to the voltage-loop bandwidth, unless the lead network is used. RFILT Selection The RFILT resistor, together with the capacitance at the ISENSE pin, creates a lowpass filter for the sensed smartslave phase-current signal. A 3.01k resistor should be used for RFILT. Selecting the Modulator Ramp Rate The modulator ramp rate is set using external resistor RMRAMP from the MRAMP pin to GND. VRAMPD f SW D The VRAMPD voltage typically ranges from 100mV to 300mV. Note that VRAMPD changes with D, while SRAMP remains constant. A smaller SRAMP provides a larger-loop bandwidth for the total inductor current (see the Loop Bandwidths section). Once a ramp-rate value has been determined, the value of the resistor can be calculated using Equation 15. Equation 15: 1 2R 2C 2 With either the droop or no-droop configuration, above the frequency (Equation 13). Equation 13: 1 f ZINT = R 2 R INT + PH C INT N www.maximintegrated.com S RAMP = R MRAMP = 23.81 S RAMP where: RMRAMP is in k SRAMP is in V/s Example: If the required ramp rate = 1.0V/s, then RMRAMP = 23.81k, and the closest 1% value is 23.7k. RINT Selection Set RINT according to Equation 16. Equation 16: For single phase: R INT < (VDD_MIN -0.2V-VCM) 0.15V IPP N+ AI R DES For 2 or more phases: V -0.2V-V DD_MIN CM R INT < MIN ,3R DES 0.15V I PP N+ AI R DES ( ) where: VDD_MIN = Minimum VDD voltage used in the application VCM = Compensation circuit common-mode voltage = 0.85V Maxim Integrated 24 MAX20751 Multiphase Master with PMBus Interface and Internal Buck Converter RDES = Resistor used to set the IOCP value IPP = Peak-to-peak ripple of the output current AI = Save current-gain factor Note that a larger RINT provides a larger-loop bandwidth for the total inductor current (see the Loop Bandwidths section). RPH Selection Each of the Maxim slave's current-sense pins is connected to the A3_IN pin of the master IC through its phase resistor (RPHk). The value of each phase resistor determines the amplitude of the phase current-sense signal, which must be below 0.4V at all times, up to and including the overcurrent limit. To help prevent phase-current imbalance due to load transients, set according to Equation 17. Equation 17: R PH R INT (G OCR + 1) where: GOCR = Gain of the OCR circuit Current Steering The phase-current-balancing circuitry works to keep the voltages across the RPH resistors approximately equal. By increasing the RPH resistor from the nominal value on a particular phase, the steady-state current in that phase can be reduced with respect to the other phases. This may be useful in reducing the temperature on the smart-slave device and inductor of that phase, if they tend to get hotter than the corresponding components of the other phases when the phase currents are all equal. Care should be taken so the inductors of the other phases do not saturate because of too much current; with coupled inductors, the relative balance of phase currents is also important. Loop Bandwidths The output-voltage loop bandwidth is given by Equation 20 (if the lead network is not used). Equation 20: BW VL = 1 R PH R INT + N 2 R DROOP C OUT R INT If the lead network is used, the output-voltage loop bandwidth and phase margin can be increased. The loop bandwidth for the total inductor current is given by Equation 21. Equation 21: R R INT + PH N V f N BWIL < INT SW S RAMP 2L AI where: L = Inductance per phase AI = Slave current gain factor The loop bandwidths should meet the conditions given by Equation 22. Equation 22: BW VL < BWIL (by at least 50kHz difference) f BW VL < SW 4 Note: If BWVL < BWIL + 50kHz cannot be met, additional phase margin can be added with the lead network. CINT Value CINT should be selected to match the time constant of the double pole, which is intrinsic in the buck-converter duty cycle-to-output transfer function given by Equation 19. Equation 19: L C N OUT C INT R PH R INT + N www.maximintegrated.com Maxim Integrated 25 MAX20751 Multiphase Master with PMBus Interface and Internal Buck Converter Increasing VOUT Using Resistor Voltage-Divider Feedback To obtain a VOUT value above the maximum VNOM value, a resistor voltage-divider feedback circuit can be used, as shown in Figure 8. The equations for choosing RVO_SP, RSP_GND, and RSN are as follows: R VO_SP VOUT = -1 R SP_GND V NOM R SN = R VO_SPR SP_GND R VO_SP + R SP_GND VOUT RVO_SP SENSE_P RSP_GND RSN SENSE_N Choose RSN 150, then: R VO_SP = VOUT RSN VNOM R SP_GND = R VO_SP VOUT - 1 VNOM where: VNOM = Nominal output voltage programmed with the R_SEL table or PMBus command. The size of the resistors should be chosen so that their power dissipation is within their rated value. RSN can be omitted for a slight (usually less than 1%) reduction in accuracy. The MAX20751 regulates and monitors the voltage from SENSE_P to SENSE_N; therefore, the PWRGD and OVP thresholds, droop resistance, VOUT slew rates, etc., are all scaled by the voltage-divider feedback. MAX20751 PMBus Interface Overview Refer to Maxim AN5941: MAX20751 PMBus Application Note. www.maximintegrated.com Figure 8. Increasing VOUT Using Resistor Voltage-Divider Feedback Basic PCB Layout Guidelines For electrical and thermal reasons, the second layer from the top and bottom should be reserved for contiguous power ground planes. It is recommended to place the MAX20751 master away from the load current path. An analog ground (AGND) copper polygon or plane should be used and the MAX20751 GND pins connected to it. The AGND (or quiet ground) polygon or plane should extend underneath the MAX20751 on one of the inner layers and be connected to the MAX20751 PGND pin at one point through a single wide trace or via. AGND should be used as a shield for the control signals (ISENSE, PWM, SENSE_P/SENSE_N, and TS_FAULTB). The control signals to and from the slaves are ideally the same length for each phase. SENSE_P/SENSE_N: These output sense lines are important for regulation and should be routed as a differential pair with sufficient AGND plane shielding. ISENSE Signals: The reconstructed current signals should be kept away from noise sources and shielded with sufficient AGND plane. Maxim Integrated 26 MAX20751 PWM Signals: Keep away from noise-sensitive traces and provide sufficient GND plane shielding. See Master/ Slave Placement. TS_FAULTB: Provides AGND plane shielding. VDD/VDD33: Place decoupling capacitors as close as possible to the part and on the same layer. Compensation: The compensation components should be placed as close as possible to the master and the amplifier inputs/outputs they connect to and away from noisy signals. RREF/R_SEL/RMRAMP: These components should be Multiphase Master with PMBus Interface and Internal Buck Converter Place a 100nF MLCC very close to the VDD pin to filter high frequencies. A 22F to 47F MLCC is required, and should also be placed close to the inductor and the IC. 3.3V power supply requires a small 100nF MLCC close to the master's pin, followed by a larger 10F MLCC. Use a PGND plane or polygon underneath the VDD To make filtering capacitors effective, place vias to shorten their path to the PGND pin. The number of vias should be as many as allowed by area to reduce path resistance to PGND. placed close to the master and away from noisy signals. Master/Slave Placement: Position the master IC so the side with all slave-related signals is facing the slaves. This will avoid having noisy lines go under the master and interact with the analog compensation nets (Figure 9). switcher components. Connect the MAX20751 PGND pin to the PGND plane or polygon. The PGND pin should connect to the MAX20751 GND pins through a single wide trace or via. The PGND plane or polygon should also connect to the power ground planes. Internal VDD Switcher Place the inductor (A) as close as possible to the PVX (phase output) pin. Figure 9. Board and Layout for Slave Signals www.maximintegrated.com Maxim Integrated 27 MAX20751 Multiphase Master with PMBus Interface and Internal Buck Converter Figure 10. MAX20751 Schematic www.maximintegrated.com Maxim Integrated 28 MAX20751 Multiphase Master with PMBus Interface and Internal Buck Converter Figure 11. Smart Slave ICs Schematic www.maximintegrated.com Maxim Integrated 29 MAX20751 Multiphase Master with PMBus Interface and Internal Buck Converter Figure 12. VIN and VOUT Capacitors Schematic Ordering Information PART DESCRIPTION PINPACKAGE TEMP RANGE PKG. CODE OUTLINE NO. LAND PATTERN NO. MAX20751EKX+ Master 36 QFN (Type C) -40C to +125C K3666+1 ES AP-3565 -- MAX20751EKX+T Master 36 QFN (Type C) -40C to +125C K3666+1 ES AP-3565 -- +Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel (2.5k). www.maximintegrated.com Maxim Integrated 30 MAX20751 Multiphase Master with PMBus Interface and Internal Buck Converter Package Information For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. Title: Package Outline - 36 Lead QFN [Type C] www.maximintegrated.com Doc No. ES AP-3565 Rev. 0 Page 1 of 3 Maxim Integrated 31 MAX20751 Multiphase Master with PMBus Interface and Internal Buck Converter Package Information (continued) For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. Title: Package Outline - 36 Lead QFN [Type C] Doc No. Rev. ES AP-3565 0 Page 2 of 3 www.maximintegrated.com Maxim Integrated 32 MAX20751 Multiphase Master with PMBus Interface and Internal Buck Converter Revision History REVISION NUMBER REVISION DATE DESCRIPTION 0 9/14 Initial Release 1 10/14 Replaced Figures 10 and 11 2 3/15 Corrected application note number PAGES CHANGED -- 28, 29 26 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated's website at www.maximintegrated.com. Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. (c) 2015 Maxim Integrated Products, Inc. 33 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Maxim Integrated: MAX20751EKX+ MAX20751EKX+T MAX20751S1VKIT#