MAX16932ATIS/V+ - Maxim Integrated

General Description

The MAX16932/MAX16933 offer two high-voltage,

synchronous step-down controllers that use only 20µA of

quiescent current with no load. They operate with an input

voltage supply from 3.5V to 42V and can operate in drop-

out condition by running at 95% duty cycle. The devices

are intended for applications with mid- to high-power

requirements and requiring two independently controlled

output supplies, such as automotive applications.

The MAX16932/MAX16933 step-down controllers oper-

ate 180° out-of-phase for reduced input ripple. The

devices also operate with switching frequencies up to

2.2MHz to allow use of small external components and

to guarantee no AM band interference. The FSYNC input

programmability enables three frequency modes for opti-

mized performance: forced fixed-frequency operation,

skip mode with ultra-low quiescent current (20µA), and

synchronization to an external clock. The devices provide

a spread-spectrum option to minimize EMI interference.

The devices also feature a power-OK monitor and over-

voltage and undervoltage lockout. Protection features

include cycle-by-cycle current limit and thermal shutdown.

The devices are available in a 28-pin TQFN-EP package

and are specified for operation over the -40°C to +125°C

automotive temperature range.

Benets and Features

●Meets Stringent OEM Module Power Consumption

and Performance Specifications

• 20µA Quiescent Current in Skip Mode

• ±1% Output-Voltage Accuracy: 5.0V/3.3V Fixed or

Adjustable Between 1V and 10V

●Enables Crank-Ready Designs

• Wide Input Supply Range from 3.5V to 36V

●EMI Reduction Features Reduce Interference with

Sensitive Radio Bands without Sacrificing Wide Input

Voltage Range

• 50ns (typ) Minimum On-Time Guarantees Skip-

Free Operation for 3.3V Output from Car Battery

at 2.2MHz

• Spread-Spectrum Option

• Frequency-Synchronization Input

• Resistor-Programmable Frequency Between

200kHz and 2.2MHz

●Integration and Thermally Enhanced Packages Save

Board Space and Cost

• Dual, 2MHz Step-Down Controllers

• 180° Out-of-Phase Operation

• Current-Mode Controllers with Forced-Continuous

and Skip Modes

• Thermally Enhanced 28-Pin TQFN-EP Package

●Protection Features Improve System Reliability

• Supply Overvoltage and Undervoltage Lockout

• Overtemperature and Short-Circuit Protection

Applications

●POL Applications for Automotive Power

●Distributed DC Power Systems

●Navigation and Radio Head Units

19-6716; Rev 10; 9/17

Ordering Information and Selector Guide appears at end of

data sheet.

MAX16932/MAX16933 2.2MHz, 36V, Dual Buck

with 20µA Quiescent Current

EVALUATION KIT AVAILABLE

IN, EN1, EN2, TERM to PGND_ ...........................-0.3V to +42V

CS1, CS2, OUT1, OUT2 to AGND ........................ -0.3V to +11V

CS1 to OUT1 ........................................................ -0.2V to +0.2V

CS2 to OUT2 ........................................................ -0.2V to +0.2V

BIAS, FSYNC, FOSC to AGND............................-0.3V to +6.0V

COMP1, COMP2 to AGND ..................................-0.3V to +6.0V

FB1, FB2, EXTVCC to AGND ..............................-0.3V to +6.0V

DL_ to PGND_ .....................................................-0.3V to +6.0V

BST_, to LX_ ........................................................-0.3V to +6.0V

DH_ to LX_ ........................................................... -0.3V to +6.0V

LX_ to PGND_.......................................................-0.3V to +42V

PGND_ to AGND .................................................. -0.3V to +0.3V

PGOOD1, PGOOD2 to AGND.......... ...................-0.3V to +6.0V

Continuous Power Dissipation (TA = +70°C)

TQFN (derate 28.6mW/NC above +70°C) .............2285.7mW

Operating Temperature Range. ........................ -40°C to +125°C

Junction Temperature Range ..........................................+150°C

Storage Temperature Range ............................ -65°C to +150°C

Lead Temperature (soldering, 10s) ................................. +300°C

Soldering Temperature (reflow)...................................... .+260°C

TQFN

Junction-to-Ambient Thermal Resistance (θJA) ..........35°C/W Junction-to-Case Thermal Resistance (θJC) .................3°C/W

(Note 1)

(VIN = 14V, VBIAS = 5V, CBIAS = 6.8µF, TA = TJ = -40°C to +125°C, unless otherwise noted. Typical values are at TA = +25°C under

normal conditions, unless otherwise noted.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT

SYNCHRONOUS STEP-DOWN DC-DC CONTROLLERS

Supply Voltage Range VIN

Normal operation 3.5 36 V

t < 1s 42

Output Overvoltage Threshold FB rising (Note 3) +10 +15 +20 %

FB falling +5 +10 +15

Supply Current IIN

VEN1 = VEN2 = 0V, TA = +25°C 8 20

µA

VEN1 = VEN2 = 0V, TA = +125°C 20

VEN1 = 5V, VOUT1 = 5V, VEN2 = 0V;

VEXTVCC = 5V, no switching 30 40

VEN2 = 5V, VOUT2 = 3.3V; VEN1 = 0V,

VEXTVCC = 3.3V, no switching 20 30

VEN1 = VEN2 = 5V, VOUT1 = 5V, VOUT2 =

3.3V, VEXTVCC = 3.3V, no switching 25 40

Buck 1 Fixed Output Voltage VOUT1

VFB1 = VBIAS, PWM mode 4.95 5 5.05 V

VFB1 = VBIAS, skip mode 4.95 5 5.075

Buck 2 Fixed Output Voltage VOUT2

VFB2 = VBIAS, PWM mode 3.234 3.3 3.366 V

VFB2 = VBIAS, skip mode 3.234 3.3 3.4

Output Voltage Adjustable Range Buck 1, buck 2 1 10 V

MAX16932/MAX16933 2.2MHz, 36V, Dual Buck

with 20µA Quiescent Current

www.maximintegrated.com Maxim Integrated

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Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer

board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these

or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

Package Thermal Characteristics

Electrical Characteristics

(VIN = 14V, VBIAS = 5V, CBIAS = 6.8µF, TA = TJ = -40°C to +125°C, unless otherwise noted. Typical values are at TA = +25°C under

normal conditions, unless otherwise noted.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT

Regulated Feedback Voltage VFB1,2 0.99 1.0 1.01 V

Feedback Leakage Current IFB1,2 TA = +25°C 0.01 1 µA

Feedback Line Regulation Error VIN = 3.5V to 36V, VFB = 1V 0.001 %/V

Transconductance

(from FB_ to COMP_) gmVFB = 1V, VBIAS = 5V 1200 2400 µS

Dead Time

MAX16932: DL_ low to DH_ high 35

MAX16932: DH_ low to DL_ high 60

MAX16933: DL_ low to DH_ high 60

MAX16933: DH_ low to DL_ high 100

Maximum Duty Cycle Buck 1, buck 2 95 98.5 %

Minimum On-Time tON(MIN) Buck 1, buck 2 50 ns

PWM Switching Frequency fSW

MAX16932 1 2.2 MHz

MAX16933 0.2 1

Buck 2 Switching Frequency MAX16932ATIT/V+,

MAX16932CATIU/V+ only 1/2fSW MHz

Switching Frequency Accuracy

MAX16932: RFOSC = 13.7kΩ,

VBIAS = 5V 1.98 2.2 2.42 MHz

MAX16933: RFOSC = 80.6kΩ,

VBIAS = 5V 360 400 440 kHz

Spread-Spectrum Range Spread spectrum enabled ±6 %

FSYNC INPUT

FSYNC Frequency Range MAX16932: Minimum sync pulse of 100ns 1.2 2.4 MHz

MAX16933: Minimum sync pulse of 400ns 240 1200 kHz

FSYNC Switching Thresholds High threshold 1.5 V

Low threshold 0.6

CS Current-Limit Voltage

Threshold VLIMIT1,2 VCS – VOUT, VBIAS = 5V, VOUT ≥ 2.5V 64 80 96 mV

Skip Mode Threshold 15 mV

Soft-Start Ramp Time Buck 1 and buck 2, xed soft-start time

regardless of frequency 2 6 10 ms

Phase Shift Between Buck1 and

Buck 2 180 °

LX1, LX2 Leakage Current VIN = 6V, VLX_ = VIN, TA = +25°C 0.01 µA

DH1, DH2 Pullup Resistance VBIAS = 5V, IDH_ = -100mA 10 20 Ω

DH1, DH2 Pulldown Resistance VBIAS = 5V, IDH_ = +100mA 2 4 Ω

DL1, DL2 Pullup Resistance VBIAS = 5V, IDL_ = -100mA 4 8 Ω

DL1, DL2 Pulldown Resistance VBIAS = 5V, IDL_ = +100mA 1.5 3 Ω

MAX16932/MAX16933 2.2MHz, 36V, Dual Buck

with 20µA Quiescent Current

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Electrical Characteristics (continued)

(VIN = 14V, VBIAS = 5V, CBIAS = 6.8µF, TA = TJ = -40°C to +125°C, unless otherwise noted. Typical values are at TA = +25°C under

normal conditions, unless otherwise noted.) (Note 2)

Note 2: Limits are 100% production tested at TA = +25°C. Limits over the operating temperature range and relevant supply voltage

range are guaranteed by design and characterization. Typical values are at TA = +25°C.

Note 3: Overvoltage protection is detected at the FB1/FB2 pins. If the feedback voltage reaches overvoltage threshold of FB1/FB2 +

15% (typ), the corresponding controller stops switching. The controllers resume switching once the output drops below FB1/

FB2 + 10% (typ).

Note 4: Guaranteed by design; not production tested.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT

PGOOD1, PGOOD2 Threshold PGOOD_H % of VOUT_, rising 85 90 95 %

PGOOD_F % of VOUT_, falling 80 85 90

PGOOD1, PGOOD2 Leakage

Current VPGOOD1,2 = 5V, TA = +25°C 0.01 1 µA

PGOOD1, PGOOD2 Startup

Delay Time

Buck 1 and buck 2 after soft-start

is complete 64 Cycles

PGOOD1, PGOOD2 Debounce

Time Fault detection 8 20 50 µs

INTERNAL LDO: BIAS

Internal BIAS Voltage VIN > 6V 4.75 5 5.25 V

BIAS UVLO Threshold VBIAS rising 3.1 3.4 V

VBIAS falling 2.7 2.9

Hysteresis 0.2 V

External VCC

VTH,EXTVCC

EXTVCC rising, HYST = 110mV 3.0 3.2 V

THERMAL OVERLOAD

Thermal Shutdown Temperature (Note 4) +170 °C

Thermal Shutdown Hysteresis (Note 4) 20 °C

EN LOGIC INPUT

High Threshold 1.8 V

Low Threshold 0.8 V

Input Current TA = +25°C 1 µA

MAX16932/MAX16933 2.2MHz, 36V, Dual Buck

with 20µA Quiescent Current

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│

Electrical Characteristics (continued)

(TA = +25°C, unless otherwise noted.)

QUIESCIENT CURRENT

vs. TEMPERATURE

TEMPERATURE (°C)

SUPPLY CURRENT (µA)

0 20 40 60 80 100 120 140

-20

-60 -40

MAX16932 toc03

VEN1 = VBAT

VEN2 = 0V

EXTVCC = VOUT1

VEN1 = 0V

VEN2 = VBAT

EXTVCC = VOUT2

NO LOAD STARTUP SEQUENCE

(VFSYNC = 0V)

MAX16932 toc01

VBAT

5V/div

VOUT1

2V/div

VOUT2

2V/div

VPGOOD1

5V/div

VPGOOD2

5V/div

2ms/div

BUCK1 EFFICIENCY

MAX16932 toc05

IOUT1 (A)

1.0E+001.0E-021.0E-04

100

1.0E-06

1.0E-011.0E-031.0E-05 1.0E+01

fSW = 2.2MHz

L = 2.2µH

VBAT = 14V

VOUT1 = 5V

SKIP MODE

EXTVCC = VOUT1

EXTVCC

= GND

EXTVCC

= VOUT2

EXTVCC

= GND

PWM MODE

EFFICIENCY (%)

QUIESCIENT CURRENT

vs. SUPPLY VOLTAGE

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (µA)

15 20 25 30 35 40

0 5

MAX16932 toc04

BUCK 1

EXTVCC = VOUT1

BUCK 2

EXTVCC = VOUT2

FULL LOAD STARTUP SEQUENCE

(VFSYNC = 0V)

MAX16932 toc02

VBAT

5V/div

VOUT1

2V/div

VOUT2

2V/div

IOUT1

2A/div

IOUT2

2A/div

VPGOOD1

5V/div

VPGOOD2

5V/div

4ms/div

BUCK2 EFFICIENCY

MAX16932 toc06

IOUT2 (A)

EFFICIENCY (%)

1.0E+001.0E-021.0E-04

100

1.0E-06

1.0E-011.0E-031.0E-05 1.0E+01

fSW = 2.2MHz

L = 2.2µH

VBAT = 14V

VOUT2 = 3.3V

SKIP MODE

PWM MODE

EXTVCC = VOUT2

EXTVCC

= GND

EXTVCC

= VOUT2

EXTVCC

= GND

MAX16932/MAX16933 2.2MHz, 36V, Dual Buck

with 20µA Quiescent Current

Maxim Integrated

│

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Typical Operating Characteristics

(TA = +25°C, unless otherwise noted.)

SWITCHING FREQUENCY

vs. LOAD CURRENT

MAX16932 toc07

LOAD CURRENT (A)

SWITCHING FREQUENCY (MHz)

54321

2.12

2.14

2.16

2.18

2.20

2.22

2.24

2.26

2.28

2.30

2.10

0 6

BUCK 1

BUCK 2

SWITCHING FREQUENCY

vs. RFOSC (MAX16932)

RFOSC (kΩ)

SWITCHING FREQUENCY (MHz)

15 25 30

2.4

2.2

2.0

1.8

1.6

1.4

1.2

0 20

MAX16932 toc08

VBIAS = 3.3V

VBIAS = 5V

SWITCHING FREQUENCY

vs. RFOSC (MAX16933)

MAX16932 toc09

RFOSC (kΩ)

SWITCHING FREQUENCY (MHz)

160

150130

14060

100

110

12040

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

0.2

30 170

VBIAS = 5V

VBIAS = 3.3V

SWITCHING FREQUENCY vs. TEMPERATURE

TEMPERATURE (°C)

SWITCHING FREQUENCY (MHz)

20 40 80 120

-20-40 0 60 100 140

2.10

2.05

2.30

2.25

2.15

2.35

2.20

2.40

2.00

-60

MAX16932 toc10

RFOSC = 13.7kΩ

EXTERNAL SYNC TRANSITION

MAX16932 toc12

VLX1

10V/div

VLX2

10V/div

VSYNC

2V/div

400ns/div

LOAD TRANSIENT RESPONSE

MAX16932 toc11

VOUT1

100mV/div

IOUT1

1A/div

400µs/div

DIPS AND DROPS

MAX16932 toc13

VBAT

10V/div

VPGOOD1

5V/div

VOUT1

5V/div

40ms/div

MAX16932/MAX16933 2.2MHz, 36V, Dual Buck

with 20µA Quiescent Current

Maxim Integrated

│

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Typical Operating Characteristics (continued)

(TA = +25°C, unless otherwise noted.)

BUCK 1 LOAD REGULATION

IOUT (A)

VOUT (V)

2345

1 6

4.992

4.991

4.996

4.995

4.993

4.997

4.994

4.998

4.989

4.990

MAX16932 toc18

VSYNC = VBIAS

BUCK 2 LOAD REGULATION

IOUT (A)

VOUT (V)

23456

3.294

3.293

3.296

3.295

3.292

3.291

3.290

3.289

3.297

MAX16932 toc19

VSYNC = VBIAS

VOUT vs. TEMPERATURE

TEMPERATURE (°C)

VOUT (%NOMINAL)

-20 0 20 40 60 80 100 120 140

-40

99.95

99.85

99.90

100.05

100.00

100.10

99.70

99.75

99.80

-60

MAX16932 toc20

VOUT1

VOUT2

EXTVCC = VGND

VSYNC = VBIAS

IOUT_ = 0A

SHORT CIRCUIT RESPONSE

MAX16932 toc16

IOUT1

2A/div

VPGOOD1

2V/div

VOUT1

1V/div

200µs/div

LOAD DUMP

MAX16932 toc14

VBAT

10V/div

VPGOOD2

5V/div

VOUT2

1V/div

100ms/div

OUTPUT OVERVOLTAGE RESPONSE

MAX16932 toc17

VPGOOD1

2V/div

VOUT1

1V/div

1s/div

SLOW VIN RAMP

MAX16932 toc15

VBAT

5V/div

VPGOOD2

5V/div

VPGOOD1

5V/div

VOUT2

2V/div

VOUT1

2V/div

10s/div

MAX16932/MAX16933 2.2MHz, 36V, Dual Buck

with 20µA Quiescent Current

Maxim Integrated

│

www.maximintegrated.com

Typical Operating Characteristics (continued)

(TA = +25°C, unless otherwise noted.)

SPECTRAL ENERGY DENSITY

vs. FREQUENCY

FREQUENCY (Hz)

OUTPUT SPECTRUM (dBµV)

350,000 400,000 450,000 500,000

-10

300,000

MAX16932 toc25

MEASURED ON THE MAX16933CATIS/V+

SPECTRAL ENERGY DENSITY

vs. FREQUENCY

FREQUENCY (Hz)

OUTPUT SPECTRUM (dBµV)

1000k 1100k 1200k

900k

-10

-5

800k

MAX16932 toc26

MEASURED AT VOUT2 ON THE

MAX16932CATIU/V+

SPECTRAL ENERGY DENSITY

vs. FREQUENCY

FREQUENCY (Hz)

OUTPUT SPECTRUM (dBµV)

2200k 2400k 2600k

2000k

-10

-5

1800k

MAX16932 toc27

MEASURED ON THE

MAX16932CATIS/V+

MINIMUM ON-TIME (BUCK 1)

MAX16932 toc23

VBAT

5V/div

VOUT1

1V/div

200ns/div

IOUT1 = 300mA

FB1 LINE REGULATION

VSUP (V)

VOUT (V)

10 15 20 25 30 35 40

0.995

1.005

1.000

1.010

0.990

MAX16932 toc21

VOUT1 = 1.8V

MINIMUM ON-TIME (BUCK 2)

MAX16932 toc24

VBAT

5V/div

VOUT1

1V/div

200ns/div

IOUT2 = 300mA

FB2 LINE REGULATION

VSUP (V)

VOUT (V)

10 15 20 25 30 35 40

0.995

1.005

1.000

1.010

0.990

MAX16932 toc22

VOUT2 = 1.8V

MAX16932/MAX16933 2.2MHz, 36V, Dual Buck

with 20µA Quiescent Current

Maxim Integrated

│

www.maximintegrated.com

Typical Operating Characteristics (continued)

PIN NAME DESCRIPTION

1 LX1 Inductor Connection for Buck 1. Connect LX1 to the switched side of the inductor. LX1 serves as the

lower supply rail for the DH1 high-side gate drive.

2 DL1 Low-Side Gate Drive Output for Buck 1. DL1 output voltage swings from VPGND1 to VBIAS.

3 PGND1 Power Ground for Buck 1

4 CS1

Positive Current-Sense Input for Buck 1. Connect CS1 to the positive terminal of the current-sense

resistor. See the Current Limiting and Current-Sense Inputs and Current-Sense Measurement

sections.

5 OUT1

Output Sense and Negative Current-Sense Input for Buck 1. When using the internal preset 5V

feedback divider (FB1 = BIAS), the buck uses OUT1 to sense the output voltage. Connect OUT1 to

the negative terminal of the current-sense resistor. See the Current Limiting and Current-Sense Inputs

and Current-Sense Measurement sections.

6 FB1

Feedback Input for Buck 1. Connect FB1 to BIAS for the 5V xed output or to a resistive divider

between OUT1 and GND to adjust the output voltage between 1V and 10V. In adjustable mode,

FB1 regulates to 1V (typ). See the Setting the Output Voltage in Buck Converters section.

7 COMP1 Buck 1 Error-Amplier Output. Connect an RC network to COMP1 to compensate buck 1.

8 BIAS

5V Internal Linear Regulator Output. Bypass BIAS to GND with a low-ESR ceramic capacitor of 6.8µF

minimum value. BIAS provides the power to the internal circuitry and external loads. See the Fixed 5V

Linear Regulator (BIAS) section.

9 AGND Signal Ground for IC

MAX16932

MAX16933

TQFN

(5mm x 5mm)

TOP VIEW

DL1

CS1

OUT1

FB1

COMP1

LX1

PGND2

OUT2

FB2

DL2

COMP2

FOSC

1 2

EN2

4 5 6 7

2021 19 17 16 15

EN1

BST1

PGOOD1

EXTVCC

AGND

PGND1 CS2

28 8

DH1

BIAS

BST2

23 13 PGOOD2

DH2

22 14 FSYNC

LX2

MAX16932/MAX16933 2.2MHz, 36V, Dual Buck

with 20µA Quiescent Current

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Pin Description

Pin Conguration

PIN NAME DESCRIPTION

10 EXTVCC 3.1V to 5.2V Input to the Switchover Comparator

11 IN Supply Input. Bypass IN with su󰀩cient capacitance to supply the two out-of-phase buck converters.

12 PGOOD1

Open-Drain Power-Good Output for Buck 1. PGOOD1 is low if OUT1 is more than 15% (typ) below

the normal regulation point. PGOOD1 asserts low during soft-start and in shutdown. PGOOD1

becomes high impedance when OUT1 is in regulation. To obtain a logic signal, pullup PGOOD1

with an external resistor connected to a positive voltage lower than 5.5V. Place a minimum of 100Ω

(RPGOOD1) in series with PGOOD1. See the Voltage Monitoring section for details.

13 PGOOD2

Open-Drain Power-Good Output for Buck 2. PGOOD2 is low if OUT2 is more than 15% (typ) below

the normal regulation point. PGOOD2 asserts low during soft-start and in shutdown. PGOOD2

becomes high impedance when OUT2 is in regulation. To obtain a logic signal, pullup PGOOD2 with

an external resistor connected to a positive voltage lower than 5.5V.

14 FSYNC

External Clock Synchronization Input. Synchronization to the controller operating frequency ratio is

1. Keep fSYNC a minimum of 10% greater than the maximum internal switching frequency for stable

operation. See the Switching Frequency/External Synchronization section.

15 FOSC Frequency Setting Input. Connect a resistor from FOSC to AGND to set the switching frequency of

the DC-DC converters.

16 COMP2 Buck 2 Error Amplier Output. Connect an RC network to COMP2 to compensate buck 2.

17 FB2

Feedback Input for Buck 2. Connect FB2 to BIAS for the 3.3V xed output or to a resistive divider

between OUT2 and GND to adjust the output voltage between 1V and 10V. In adjustable mode, FB2

regulates to 1V (typ). See the Setting the Output Voltage in Buck Converters section.

18 OUT2

Output Sense and Negative Current-Sense Input for Buck 2. When using the internal preset 3.3V

feedback-divider (FB2 = BIAS), the buck uses OUT2 to sense the output voltage. Connect OUT2 to

the negative terminal of the current-sense resistor. See the Current Limiting and Current-Sense Inputs

and Current-Sense Measurement sections.

19 CS2

Positive Current-Sense Input for Buck 2. Connect CS2 to the positive terminal of the current-sense

resistor. See the Current Limiting and Current-Sense Inputs and Current-Sense Measurement

sections.

20 PGND2 Power Ground for Buck 2

21 DL2 Low-Side Gate Drive Output for Buck 2. DL2 output voltage swings from VPGND2 to VBIAS.

22 LX2 Inductor Connection for Buck 2. Connect LX2 to the switched side of the inductor. LX2 serves as the

lower supply rail for the DH2 high-side gate drive.

23 DH2 High-Side Gate Drive Output for Buck 2. DH2 output voltage swings from VLX2 to VBST2.

24 BST2

Boost Capacitor Connection for High-Side Gate Voltage of Buck 2. Connect a high-voltage diode

between BIAS and BST2. Connect a ceramic capacitor between BST2 and LX2. See the High-Side

Gate-Driver Supply (BST_) section.

25 EN2 High-Voltage Tolerant, Active-High Digital Enable Input for Buck 2. Driving EN2 high enables

buck 2.

26 EN1 High-Voltage Tolerant, Active-High Digital Enable Input for Buck 1. Driving EN1 high enables

buck 1.

MAX16932/MAX16933 2.2MHz, 36V, Dual Buck

with 20µA Quiescent Current

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│

Pin Description (continued)

Detailed Description

The MAX16932/MAX16933 are automotive-rated dual-

output switching power supplies. These devices integrate

two synchronous step-down controllers and can provide

two independent controlled power rails as follows:

• A buck controller with a fixed 5V output voltage or an

adjustable 1V to 10V output voltage.

• A buck controller with a fixed 3.3V output voltage or an

adjustable 1V to 10V output voltage.

The two buck controllers can each provide up to 10A

output current and are independently controllable.

EN1 and EN2 enable the respective buck controllers.

Connect EN1 and EN2 directly to VBAT, or to power-

supply sequencing logic.

In skip mode, with no load and only buck 2 active, the

total supply current is reduced to 20µA (typ). When both

controllers are disabled, the total current drawn is further

reduced to 8µA (typ).

Fixed 5V Linear Regulator (BIAS)

The internal circuitry of the MAX16932/MAX16933

requires a 5V bias supply. An internal 5V linear regulator

(BIAS) generates this bias supply. Bypass BIAS with a

6.8µF or greater ceramic capacitor to guarantee stability

under the full-load condition.

The internal linear regulator can source up to 100mA

(150mA under EXTVCC switchover, see the EXTVCC

Switchover section). Use the following equation to estimate

the internal current requirements for the MAX16932/

MAX16933:

IBIAS = ICC + fSW(QG_DH1 + QG_DL1 +

QG_DH2 + QG_DL2) = 10mA to 50mA (typ)

where ICC is the internal supply current, 5mA (typ), fSW

is the switching frequency, and QG_ is the MOSFET’s

total gate charge (specification limits at VGS = 5V). To

minimize the internal power dissipation, bypass BIAS to

an external 5V rail.

EXTVCC Switchover

The internal linear regulator can be bypassed by connect-

ing an external supply (3V to 5.2V) or the output of one of

the buck converters to EXTVCC. BIAS internally switches

to EXTVCC and the internal linear regulator turns off. This

configuration has several advantages:

• It reduces the internal power dissipation of the

MAX16932/MAX16933.

• The low-load efficiency improves as the internal sup-

ply current gets scaled down proportionally to the duty

cycle.

If VEXTVCC drops below VTH,EXTVCC = 3V (min), the

internal regulator enables and switches back to BIAS.

Undervoltage Lockout (UVLO)

The BIAS input undervoltage lockout (UVLO) circuitry

inhibits switching if the 5V bias supply (BIAS) is below

its 2.9V (typ) UVLO falling threshold. Once the 5V bias

supply (BIAS) rises above its UVLO rising threshold and

EN1 and EN2 enable the buck controllers, the controllers

start switching and the output voltages begin to ramp up

using soft-start.

PIN NAME DESCRIPTION

27 BST1

Boost Capacitor Connection for High-Side Gate Voltage of Buck 1. Connect a high-voltage diode

between BIAS and BST1. Connect a ceramic capacitor between BST1 and LX1. See the High-Side

Gate-Driver Supply (BST_) section.

28 DH1 High-Side Gate-Drive Output for Buck 1. DH1 output voltage swings from VLX1 to VBST1.

— EP

Exposed Pad. Connect the exposed pad to ground. Connecting the exposed pad to ground does not

remove the requirement for proper ground connections to PGND1, PGND2, and AGND. The exposed

pad is attached with epoxy to the substrate of the die, making it an excellent path to remove heat from

the IC.

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Pin Description (continued)

Buck Controllers

The MAX16932/MAX16933 provide two buck controllers

with synchronous rectification. The step-down control-

lers use a PWM, current-mode control scheme. External

logic-level MOSFETs allow for optimized load-current

design. Fixed-frequency operation with optimal interleav-

ing minimizes input ripple current from the minimum to the

maximum input voltages. Output-current sensing provides

an accurate current limit with a sense resistor or power

dissipation can be reduced using lossless current sensing

across the inductor.

Soft-Start

Once a buck converter is enabled by driving the corre-

sponding EN_ high, the soft-start circuitry gradually ramps

up the reference voltage during soft-start time (tSSTART

= 6ms (typ)) to reduce the input surge currents during

startup. Before the device can begin the soft-start, the

following conditions must be met:

1) VBIAS exceeds the 3.4V (max) undervoltage-lockout

threshold.

2) VEN_ is logic-high.

Switching Frequency/External Synchronization

The MAX16932 provides an internal oscillator adjust-

able from 1MHz to 2.2MHz. The MAX16933 provides

an internal oscillator adjustable from 200kHz to 1MHz.

High-frequency operation optimizes the application for the

smallest component size, trading off efficiency to higher

switching losses. Low-frequency operation offers the best

overall efficiency at the expense of component size and

board space. To set the switching frequency, connect a

resistor RFOSC from FOSC to AGND. See TOC8 and

TOC9 (Switching Frequency vs. RFOSC) in the Typical

Operating Characteristics to determine the relationship

between switching frequency and RFOSC.

Buck 1 is synchronized with the internal clock-signal rising

edge, while buck 2 is synchronized with the clock-signal

falling edge.

The devices can be synchronized to an external clock by

connecting the external clock signal to FSYNC. A rising

edge on FSYNC resets the internal clock. Keep the FSYNC

frequency between 110% and 150% of the internal fre-

quency. The FSYNC signal should have a 50% duty cycle.

Light-Load E󰀩ciency Skip Mode (VFSYNC = 0V)

Drive FSYNC low to enable skip mode. In skip mode, the

devices stop switching until the FB voltage drops below

the reference voltage. Once the FB voltage has dropped

below the reference voltage, the devices begin switching

until the inductor current reaches 20% (skip threshold)

of the maximum current defined by the inductor DCR or

output shunt resistor.

Forced-PWM Mode (VFSYNC = High)

Driving FSYNC high prevents the devices from entering

skip mode by disabling the zero-crossing detection of

the inductor current. This forces the low-side gate-driver

waveform to constantly be the complement of the high-

side gate-drive waveform, so the inductor current revers-

es at light loads and discharges the output capacitor. The

benefit of forced PWM mode is to keep the switching

frequency constant under all load conditions. However,

forced-frequency operation diverts a considerable amount

of the output current to PGND, reducing the efficiency

under light-load conditions.

Forced-PWM mode is useful for improving load-transient

response and eliminating unknown frequency harmonics

that may interfere with AM radio bands.

Spread Spectrum

The MAX16932CATIS, MAX16932CATIU, and

MAX16933CATIS feature enhanced EMI performance.

They perform ±6% dithering of the switching frequency

to reduce peak emission noise at the clock frequency

and its harmonics, making it easier to meet stringent

emission limits.

When using an external clock source (i.e., driving the

FSYNC input with an external clock), spread spectrum is

disabled.

Buck 2 Switching Frequency

For the MAX16932ATIT and MAX16932CATIU, the

switching frequency of buck 2 is set to 1/2 of fSW (buck

1 switching frequency). When using these devices, the

external components of buck 2 should be sized to account

for the reduced switching frequency (see the Design

Procedure section).

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MOSFET Gate Drivers (DH_ and DL_)

The DH_ high-side n-channel MOSFET drivers are pow-

ered from capacitors at BST_ while the low-side drivers

(DL_) are powered by the 5V linear regulator (BIAS). On

each channel, a shoot-through protection circuit monitors

the gate-to-source voltage of the external MOSFETs to

prevent a MOSFET from turning on until the complemen-

tary switch is fully off. There must be a low-resistance,

low-inductance path from the DL_ and DH_ drivers to the

MOSFET gates for the protection circuits to work properly.

Follow the instructions listed to provide the necessary low-

resistance and low-inductance path:

• Use very short, wide traces (50 mils to 100 mils wide if

the MOSFET is 1in from the driver).

It may be necessary to decrease the slew rate for the

gate drivers to reduce switching noise or to compensate

for low-gate charge capacitors. For the low-side drivers,

use gate capacitors in the range of 1nF to 5nF from DL_

to GND. For the high-side drivers, connect a small 5Ω to

10Ω resistor between BST_ and the bootstrap capacitor.

Note: Gate drivers must be protected during shutdown,

at the absence of the supply voltage (VBIAS = 0V) when

the gate is pulled high either capacitively or by the leak-

age path on the PCB. Therefore, external gate pulldown

resistors are needed, to prevent making a direct path from

VBAT to GND.

High-Side Gate-Driver Supply (BST_)

The high-side MOSFET is turned on by closing an inter-

nal switch between BST_ and DH_ and transferring the

bootstrap capacitor’s (at BST_) charge to the gate of the

high-side MOSFET. This charge refreshes when the high-

side MOSFET turns off and the LX_ voltage drops down to

ground potential, taking the negative terminal of the capaci-

tor to the same potential. At this time the bootstrap diode

recharges the positive terminal of the bootstrap capacitor.

The selected n-channel high-side MOSFET determines the

appropriate boost capacitance values (CBST_ in the Typical

Operating Circuit) according to the following equation:

BST_ BST_

=∆

where QG is the total gate charge of the high-side

MOSFET and ΔVBST_ is the voltage variation allowed

on the high-side MOSFET driver after turn-on. Choose

ΔVBST_ such that the available gate-drive voltage is not

significantly degraded (e.g., ΔVBST_ = 100mV to 300mV)

when determining CBST_.

The boost capacitor should be a low-ESR ceramic

capacitor. A minimum value of 100nF works in most cases.

Current Limiting and Current-Sense Inputs

(OUT_ and CS_)

The current-limit circuit uses differential current-sense

inputs (OUT_ and CS_) to limit the peak inductor current.

If the magnitude of the current-sense signal exceeds the

current-limit threshold (VLIMIT1,2 = 80mV (typ)), the PWM

controller turns off the high-side MOSFET. The actual

maximum load current is less than the peak current-limit

threshold by an amount equal to half of the inductor ripple

current. Therefore, the maximum load capability is a

function of the current-sense resistance, inductor value,

switching frequency, and duty cycle (VOUT_/VIN).

For the most accurate current sensing, use a current-

sense shunt resistor (RSH) between the inductor and the

output capacitor. Connect CS_ to the inductor side of RSH

and OUT_ to the capacitor side. Dimension RSH such that

the maximum inductor current (IL,MAX = ILOAD,MAX+1/2

IRIPPLE,PP) induces a voltage of VLIMIT1,2 across RSH

including all tolerances.

For higher efficiency, the current can also be measured

directly across the inductor. This method could cause

up to 30% error over the entire temperature range and

requires a filter network in the current-sense circuit. See

the Current-Sense Measurement section.

Voltage Monitoring (PGOOD_)

The MAX16932/MAX16933 include several power moni-

toring signals to facilitate power-supply sequencing and

supervision. PGOOD_ can be used to enable circuits that

are supplied by the corresponding voltage rail, or to turn

on subsequent supplies.

Each PGOOD_ goes high (high impedance) when the

corresponding regulator output voltage is in regulation.

Each PGOOD_ goes low when the corresponding regula-

tor output voltage drops below 15% (typ) or rises above

15% (typ) of its nominal regulated voltage. Connect a

10kΩ (typ) pullup resistor from PGOOD_ to the relevant

logic rail to level-shift the signal.

PGOOD_ asserts low during soft-start, soft-discharge,

and when either buck converter is disabled (either EN1

or EN2 is low).

To ensure latchup immunity on the PGOOD1 pin,

in compliance with the AEC-Q100 guidelines, a

minimum resistance of 100Ω should be placed

between the PGOOD1 pin and any other external

components. All other pins are compliant with no

additional external components.

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Thermal-Overload, Overcurrent, and

Overvoltage and Undervoltage Behavior

Thermal-Overload Protection

Thermal-overload protection limits total power dissipation

in the devices. When the junction temperature exceeds

+170°C, an internal thermal sensor shuts down the devices,

allowing them to cool. The thermal sensor turns on the

devices again after the junction temperature cools by 20°C.

Overcurrent Protection

If the inductor current in the MAX16932/MAX16933

exceeds the maximum current limit programmed at CS_

and OUT_, the respective driver turns off. In an overcurrent

mode, this results in shorter and shorter high-side pulses.

A hard short results in a minimum on-time pulse every

clock cycle. Choose the components so they can with-

stand the short-circuit current if required.

Overvoltage Protection

The devices limit the output voltage of the buck

converters by turning off the high-side gate driver at

approximately 115% of the regulated output voltage. The

output voltage needs to come back in regulation before

the high-side gate driver starts switching again.

Design Procedure

Buck Converter Design Procedure

E󰀨ective Input Voltage Range in Buck Converters

Although the MAX16932/MAX16933 can operate

from input supplies up to 36V (42V transients) and

regulate down to 1V, the minimum voltage conversion ratio

(VOUT/VIN) might be limited by the minimum controllable

on-time. For proper fixed-frequency PWM operation and

optimal efficiency, buck 1 and buck 2 should operate in

continuous conduction during normal operating conditions.

For continuous conduction, set the voltage conversion

ratio as follows:

OUT ON(MIN) SW

Vt × f

where tON(MIN) is 50ns (typ) and fSW is the switching

frequency in Hz. If the desired voltage conversion does

not meet the above condition, pulse skipping occurs to

decrease the effective duty cycle. Decrease the switching

frequency if constant switching frequency is required. The

same is true for the maximum voltage conversion ratio.

The maximum voltage conversion ratio is limited by the

maximum duty cycle (95%).

OUT

IN DROP

0.95

VV <

−

where VDROP = IOUT (RON,HS + RDCR) is the sum of

the parasitic voltage drops in the high-side path and fSW

is the programmed switching frequency. During low drop

operation, the devices reduce fSW to 25% (max) of the

programmed frequency. In practice, the above condition

should be met with adequate margin for good load-tran-

sient response.

Setting the Output Voltage in Buck Converters

Connect FB1 and FB2 to BIAS to enable the fixed buck

controller output voltages (5V and 3.3V) set by a preset

internal resistive voltage-divider connected between

the output (OUT_) and AGND. To externally adjust the

output voltage between 1V and 10V, connect a resistive

divider from the output (OUT_) to FB_ to AGND (see

the Typical Operating Circuit). Calculate RFB_1 and

RFB_2 with the following equation:

OUT_

FB_1 FB_2 FB_

RR 1









= −









where VFB_ = 1V (typ) (see the Electrical Characteristics

table).

DC output accuracy specifications in the Electrical

Characteristics table refer to the error comparator’s thresh-

old, VFB_ = 1V (typ). When the inductor conducts continu-

ously, the devices regulate the peak of the output ripple,

so the actual DC output voltage is lower than the slope-

compensated trip level by 50% of the output ripple voltage.

In discontinuous conduction mode (skip or STDBY active

and IOUT < ILOAD(SKIP)), the devices regulate the valley

of the output ripple, so the output voltage has a DC regu-

lation level higher than the error-comparator threshold.

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Inductor Selection in Buck Converters

Three key inductor parameters must be specified for

operation with the MAX16932/MAX16933: inductance

value (L), inductor saturation current (ISAT), and DC

resistance (RDCR). To determine the optimum

inductance, knowing the typical duty cycle (D) is

important.

OUT OUT

IN IN OUT DS(ON) DCR

D OR D

V V I (R R )

= =

−+

if the RDCR of the inductor and RDS(ON) of the MOSFET

are available with VIN = (VBAT - VDIODE). All values should

be typical to optimize the design for normal operation.

Inductance

The exact inductor value is not critical and can be

adjusted in order to make trade-offs among size, cost,

efficiency, and transient response requirements.

• Lower inductor values increase LIR, which minimizes

size and cost and improves transient response at the

cost of reduced efficiency due to higher peak currents.

• Higher inductance values decrease LIR, which

increases efficiency by reducing the RMS current at

the cost of requiring larger output capacitors to meet

load-transient specifications.

The ratio of the inductor peak-to-peak AC current to DC

average current (LIR) must be selected first. A good initial

value is a 30% peak-to-peak ripple current to average-

current ratio (LIR = 0.3). The switching frequency, input

voltage, output voltage, and selected LIR then determine

the inductor value as follows:

IN OUT

SW OUT

(V V )xD

L[µH] f [MHz]x I x LIR

−

where VIN, VOUT, and IOUT are typical values (so that

efficiency is optimum for typical conditions).

Peak Inductor Current

Inductors are rated for maximum saturation current. The

maximum inductor current equals the maximum load

current in addition to half of the peak-to-peak ripple

current:

INDUCTOR

PEAK LOAD(MAX)

∆

= +

For the selected inductance value, the actual peak-to-peak

inductor ripple current (ΔIINDUCTOR) is calculated as:

OUT IN OUT

INDUCTOR

IN SW

V (V V )

IV xf xL

−

∆=

where ΔIINDUCTOR is in mA, L is in µH, and fSW is in kHz.

Once the peak current and the inductance are known, the

inductor can be selected. The saturation current should

be larger than IPEAK or at least in a range where the

inductance does not degrade significantly. The MOSFETs

are required to handle the same range of current without

dissipating too much power.

MOSFET Selection in Buck Converters

Each step-down controller drives two external logic-level

n-channel MOSFETs as the circuit switch elements. The

key selection parameters to choose these MOSFETs

include the items in the following sections.

Threshold Voltage

All four n-channel MOSFETs must be a logic-level type

with guaranteed on-resistance specifications at VGS =

4.5V. If the internal regulator is bypassed (for example:

VEXTVCC = 3.3V), then the n-channel MOSFETs should

be chosen to have guaranteed on-resistance at that gate-

to-source voltage.

Maximum Drain-to-Source Voltage (VDS(MAX))

All MOSFETs must be chosen with an appropriate VDS

rating to handle all VIN voltage conditions.

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Current Capability

The n-channel MOSFETs must deliver the average

current to the load and the peak current during switching.

Choose MOSFETs with the appropriate average current

at VGS = 4.5V or VGS = VEXTVCC when the internal

linear regulator is bypassed. For load currents below

approximately 3A, dual MOSFETs in a single package

can be an economical solution. To reduce switching noise

for smaller MOSFETs, use a series resistor in the BST_

path and additional gate capacitance. Contact the factory

for guidance using gate resistors.

Current-Sense Measurement

For the best current-sense accuracy and

overcurrent protection, use a ±1% tolerance current-

sense resistor between the inductor and output as

shown in Figure 1A. This configuration constantly

monitors the inductor current, allowing accurate

current-limit protection. Use low-inductance current-

sense resistors for accurate measurement.

Alternatively, high-power applications that do not require

highly accurate current-limit protection can reduce the

overall power dissipation by connecting a series RC

circuit across the inductor (Figure 1B) with an equivalent

time constant:



=



CSHL DCR

R1 R2

Figure 1. Current-Sense Configurations

COUT

CIN

INPUT (VIN)

A) OUTPUT SERIES RESISTOR SENSING

DH_

LX_

DL_

GND

CS_

OUT_

CEQ

DCR

INPUT (VIN)

B) LOSSLESS INDUCTOR SENSING

DH_

LX_

DL_

GND

CS_

OUT_

INDUCTOR

RCSHL = ( )RDCR

R1 + R2

RDCR = [ + ]

CEQ

MAX16932

MAX16933

MAX16932

MAX16933

RSENSE

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and:



= +





DCR EQ

L11

RC R1 R2

where RCSHL is the required current-sense resistor and

RDCR is the inductor’s series DC resistor. Use the

inductance and RDCR values provided by the inductor

manufacturer.

Carefully observe the PCB layout guidelines to ensure the

noise and DC errors do no corrupt the differential current-

sense signals seen by CS_ and OUT_. Place the sense

resistor close to the devices with short, direct traces,

making a Kelvin-sense connection to the current-sense

resistor.

Input Capacitor in Buck Converters

The discontinuous input current of the buck converter

causes large input ripple currents and therefore the input

capacitor must be carefully chosen to withstand the input

ripple current and keep the input voltage ripple within

design requirements. The 180° ripple phase operation

increases the frequency of the input capacitor ripple

current to twice the individual converter switching

frequency. When using ripple phasing, the worst-case

input capacitor ripple current is when the converter with

the highest output current is on.

The input voltage ripple is composed of ΔVQ (caused by

the capacitor discharge) and ΔVESR (caused by the ESR

of the input capacitor). The total voltage ripple is the sum

of ΔVQ and ΔVESR that peaks at the end of an on-cycle.

Calculate the input capacitance and ESR required for a

specific ripple using the following equation:

( )

−

∆

Ω= ∆













=∆

ESR

LOAD(MAX)

OUT

LOAD(MAX) IN

IN Q SW

ESR[ ] I

C [µF] V xf

where:

( )

−−

∆=

IN OUT OUT

PP IN SW

V V xV

IV xf xL

ILOAD(MAX) is the maximum output current in A, ΔIP-P is

the peak-to-peak inductor current in A, fSW is the switch-

ing frequency in MHz, and L is the inductor value in µH.

The internal 5V linear regulator (BIAS) includes an output

UVLO with hysteresis to avoid unintentional chattering

during turn-on. Use additional bulk capacitance if the

input source impedance is high. At lower input voltage,

additional input capacitance helps avoid possible under-

shoot below the undervoltage lockout threshold during

transient loading.

Output Capacitor in Buck Converters

The actual capacitance value required relates to the

physical size needed to achieve low ESR, as well as to

the chemistry of the capacitor technology. The capacitor

is usually selected by ESR and the voltage rating rather

than by capacitance value.

When using low-capacity filter capacitors, such as

ceramic capacitors, size is usually determined by the

capacity needed to prevent VSAG and VSOAR from

causing problems during load transients. Generally, once

enough capacitance is added to meet the overshoot

requirement, undershoot at the rising load edge is no

longer a problem (see the Transient Considerations

section). However, low-capacity filter capacitors typically

have high-ESR zeros that can affect the overall stability.

The total voltage sag (VSAG) can be calculated as follows:

∆

=×−

∆ −∆

LOAD(MAX)

SAG OUT IN MAX OUT

LOAD(MAX)

OUT

L( I )

V2C ((V D ) V )

I (t t)

The amount of overshoot (VSOAR) during a full-load to

no-load transient due to stored inductor energy can be

calculated as:

∆

≈

LOAD(MAX)

SOAR

OUT OUT

(I )L

V2C V

ESR Considerations

The output filter capacitor must have low enough

equivalent series resistance (ESR) to meet output

ripple and load-transient requirements, yet have high

enough ESR to satisfy stability requirements. When using

high-capacitance, low-ESR capacitors, the filter

capacitor’s ESR dominates the output voltage ripple. So

the output capacitor’s size depends on the maximum ESR

required to meet the output-voltage ripple (VRIPPLE(P-P))

specifications:

−=

RIPPLE(P P) LOAD(MAX)

V ESR x I x LIR

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In standby mode, the inductor current becomes

discontinuous, with peak currents set by the idle-mode

current-sense threshold (VCS,SKIP = 26mV (typ)).

Transient Considerations

The output capacitor must be large enough to absorb

the inductor energy while transitioning from no-load to

full-load condition without tripping the overvoltage fault

protection. The total output voltage sag is the sum of the

voltage sag while the inductor is ramping up and the volt-

age sag before the next pulse can occur. Therefore:

( )

∆

=−

∆ −∆

LOAD(MAX)

OUT SAG IN MAX OUT

LOAD(MAX)

SAG

C2V (V x D V )

I tt

where DMAX is the maximum duty factor (approximately

95%), L is the inductor value in µH, COUT is the output

capacitor value in µF, t is the switching period (1/fSW) in

µs, and Δt equals (VOUT/VIN) x t.

The MAX16932/MAX16933 use a peak current-mode

control scheme that regulates the output voltage by

forcing the required current through the external inductor,

so the controller uses the voltage drop across the DC

resistance of the inductor or the alternate series current-

sense resistor to measure the inductor current. Current-

mode control eliminates the double pole in the feedback

loop caused by the inductor and output capacitor result-

ing in a smaller phase shift and requiring less elaborate

error-amplifier compensation than voltage-mode control.

A single series resistor (RC) and capacitor (CC) is all

that is required to have a stable, high-bandwidth loop in

applications where ceramic capacitors are used for out-

put filtering (see Figure 2). For other types of capacitors,

due to the higher capacitance and ESR, the frequency

of the zero created by the capacitance and ESR is lower

than the desired closed-loop crossover frequency. To

stabilize a non-ceramic output capacitor loop, add another

compensation capacitor (CF) from COMP to AGND to

cancel this ESR zero.

The basic regulator loop is modeled as a power

modulator, output feedback divider, and an error amplifier

as shown in Figure 2. The power modulator has a DC

gain set by gmc x RLOAD, with a pole and zero pair set

by RLOAD, the output capacitor (COUT), and its ESR. The

loop response is set by the following equations:

= ×

MOD(dc) mc LOAD

GAIN g R

where RLOAD = VOUT/ILOUT(MAX) in Ω and gmc =1/(AV_CS

x RDC) in S. AV_CS is the voltage gain of the current-sense

amplifier and is typically 11V/V. RDC is the DC resistance of

the inductor or the current-sense resistor in Ω.

In a current-mode step-down converter, the output

capacitor and the load resistance introduce a pole at the

following frequency:

=π× ×

pMOD OUT LOAD

f2C R

The unity gain frequency of the power stage is set by

COUT and gmc:

=π×

UGAINpMOD

OUT

f2C

The output capacitor and its ESR also introduce a zero at:

=π× ×

zMOD OUT

f2 ESR C

When COUT is composed of “n” identical capacitors in

parallel, the resulting COUT = nxCOUT(EACH), and ESR =

ESR(EACH)/n. Note that the capacitor zero for a parallel

combination of alike capacitors is the same as for an

individual capacitor.

The feedback voltage-divider has a gain of GAINFB =

VFB/VOUT, where VFB is 1V (typ).

Figure 2. Compensation Network

CS_

OUT_

FB_

RESR

VREF

COUT

gmc = 1/(AVCS x RDC)

CURRENT MODE

POWER

MODULATION

ERROR

AMP

COMP_

gmea = 1200µS

30MΩ

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The transconductance error amplifier has a DC gain

of GAINEA(DC) = gm,EA x ROUT,EA, where gm,EA is

the error amplifier transconductance, which is 1200µS

(typ), and ROUT,EA is the output resistance of the error

amplifier, which is 30MΩ (typ) (see the Electrical

Characteristics table.)

A dominant pole (fdpEA) is set by the compensation

capacitor (CC) and the amplifier output resistance

(ROUT,EA). A zero (fZEA) is set by the compensation

resistor (RC) and the compensation capacitor (CC). There

is an optional pole (fPEA) set by CF and RC to cancel the

output capacitor ESR zero if it occurs near the crossover

frequency (fC, where the loop gain equals 1 (0dB)). Thus:

dpEA C OUT,EA C

f2 C (R R )

=π× × +

zEA

f2C R

=π× ×

pEA

f2CR

=π× ×

The loop-gain crossover frequency (fC) should be set

below 1/5th of the switching frequency and much higher

than the power-modulator pole (fpMOD). Select a value for

fC in the range:

pMOD C

<< ≤

At the crossover frequency, the total loop gain must be

equal to 1. So:

MOD(f ) EA(f )

OUT

GAIN GAIN 1

×× =

EA(f ) m,EA C

GAIN g R= ×

pMOD

MOD(f ) MOD(dc) C

GAIN GAIN f

= ×

Therefore:

MOD(f ) m,EA C

OUT

GAIN g R 1

× × ×=

Solving for RC:

OUT

Cm,EA FB MOD(f )

Rg V GAIN

=××

Set the error-amplifier compensation zero formed by RC

and CC at the fpMOD. Calculate the value of CC as follows:

2f R

pMOD C

=π× ×

If fzMOD is less than 5 x fC, add a second capacitor CF

from COMP to AGND. The value of CF is:

2f R

zMOD C

=π× ×

As the load current decreases, the modulator pole also

decreases; however, the modulator gain increases accord-

ingly and the crossover frequency remains the same.

Below is a numerical example to calculate the

compensation network component values of Figure 2:

AV_CS = 11V/V

RDCR = 15mΩ

gmc = 1/(AV_CS x RDC) = 1/(11 x 0.015) = 6.06

VOUT = 5V

IOUT(MAX) = 5.33A

RLOAD = VOUT/IOUT(MAX) = 5V/5.33A = 0.9375Ω

COUT = 2x47µF = 94µF

ESR = 9mΩ/2 = 4.5mΩ

fSW = 26.4/65.5kΩ = 0.403MHz

MOD(dc)

GAIN 6.06 0.9375 5.68

=×=

pMOD

f 1.8kHz

2 94µF 0.9375

= ≈

π× ×

pMOD C

<< ≤

1.8kHz f 80.6kHz<< ≤

select fC = 40kHz

zMOD

f 376kHz

2 4.5m 94µF

= ≈

π× Ω×

since fzMOD > fC:

RC ≈ 16kΩ

CC ≈ 5.6nF

CF ≈ 27pF

MAX16932/MAX16933 2.2MHz, 36V, Dual Buck

with 20µA Quiescent Current

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│

Applications Information

Layout Recommendations

Careful PCB layout is critical to achieve low switching

losses and clean, stable operation. The switching power

stage requires particular attention (Figure 3). If possible,

mount all the power components on the top side of the

board, with their ground terminals flush against one

another. Follow these guidelines for good PCB layout:

• Keep the high-current paths short, especially at the

ground terminals. This practice is essential for stable,

jitter-free operation.

• Keep the power traces and load connections short.

This practice is essential for high efficiency. Using

thick copper PCBs (2oz vs. 1oz) can enhance full-load

efficiency by 1% or more.

• Minimize current-sensing errors by connecting CS_

and OUT_. Use kelvin sensing directly across the

current-sense resistor (RSENSE_).

• Route high-speed switching nodes (BST_, LX_, DH_,

and DL_) away from sensitive analog areas (FB_,

CS_, and OUT_).

Layout Procedure

1) Place the power components first, with ground

terminals adjacent (low-side FET, CIN, COUT_, and

Schottky). If possible, make all these connections on

the top layer with wide, copper-filled areas.

2) Mount the controller IC adjacent to the low-side

MOSFET, preferably on the back side opposite NL_

and NH_ to keep LX_, GND, DH_, and the DL_ gate

drive lines short and wide. The DL_ and DH_ gate

traces must be short and wide (50 mils to 100 mils

wide if the MOSFET is 1in from the controller IC) to

keep the driver impedance low and for proper adaptive

dead-time sensing.

3) Group the gate-drive components (BST_ diode and

capacitor and LDO bypass capacitor BIAS) together

near the controller IC. Be aware that gate currents of

up to 1A flow from the bootstrap capacitor to BST_,

from DH_ to the gate of the external HS switch and

from the LX_ pin to the inductor. Up to 100mA of

current flow from the BIAS capacitor through the

bootstrap diode to the bootstrap capacitor. Dimension

those traces accordingly.

4) Make the DC-DC controller ground connections as

shown in Figure 3. This diagram can be viewed as

having two separate ground planes: power ground,

where all the high-power components go; and an

analog ground plane for sensitive analog components.

The analog ground plane and power ground plane

must meet only at a single point directly under the IC.

5) Connect the output power planes directly to the output

filter capacitor positive and negative terminals with

multiple vias. Place the entire DC-DC converter circuit

as close to the load as is practical.

Figure 3. Layout Example

INDUCTOR

COUT

CIN

INPUT

KELVIN-SENSE VIAS

UNDER THE SENSE RESISTOR

(REFER TO THE EVALUATION KIT)

GROUND

OUTPUT

LOW-SIDE

n-CHANNEL

MOSFET (NH)

HIGH-SIDE

n-CHANNEL

MOSFET (NL)

MAX16932/MAX16933 2.2MHz, 36V, Dual Buck

with 20µA Quiescent Current

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│

EAMP1

PGOOD

COMP

PGOOD1 COMP1

PGOOD LOW LEVEL

PGOOD HIGH LEVEL

FB1

OUT1

CS1

EN1

80 mV(TYP) MAX

DIFFERENTIAL INPUT

FEEDBACK

SELECT LOGIC

REF = 1V

CURRENT-LIMIT

THRESHOLD

OSCILLATOR

TIED HIGH (PWM MODE)

TIED LOW (SKIP MODE)

CLK2

CLK1

INTERNAL

SOFT-START

SLOPE

COMP LOGIC

CLK 180°

OUT-OF-PHASE

INTERNAL LINEAR

REGULATOR

SWITCHOVER

DC-DC1

CONTROL LOGIC

ZERO

CROSS

COMP

CSA1

PWM1

LX1

LX2

LX1

BIAS

CLK1 STEP-DOWN DC-DC1

GATE DRIVE

LOGIC

EN1 BST1

DH1

LX1

DL1

PGND1

PGND2

BIAS

EXTVCC

IF 3.1V <

VEXTVCC < 5.2V

PWM1

ZX1

SPREAD SPECTRUM

OPTION AVAILABLE WITH

INTERNAL CLOCK ONLY

EXTERNAL

CLOCK INPUT

FSYNC

SELECT LOGIC

DC-DC2 CONTROL LOGIC

SAME AS DC-DC1 ABOVE

FSYNC

FOSC

COMP2

FB2

OUT2

CS2

EN2

PGOOD2

AGND

CLK2 STEP-DOWN DC-DC2

GATE DRIVE

LOGIC

EN2 BST2

DH2

LX2

DL2

PWM2

ZX2

LX2

MAX16932

MAX16933

MAX16932/MAX16933 2.2MHz, 36V, Dual Buck

with 20µA Quiescent Current

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│

Block Diagram

MAX16932

MAX16933

PGOOD1FB1

FB2

*DCR SENSE IS ALSO AN OPTION.

DL1

DH1

LX1

BST1 L1

RCS1*

COUT1

OUT1

CS1

CIN

OUT1OUT1

PGOOD2

PGND1

LX2

EXTVCC

OUT1

DH2

DL2

VBAT

L2 RCS2*

RPGOOD1

COUT2

OUT2

CS2

BIAS

BST2

CS1CS1

EN1

EN2

OUT2

CS2CS2

OUT2

FSYNC

FOSC

COMP1

AGND

PGND2

COMP2

MAX16932/MAX16933 2.2MHz, 36V, Dual Buck

with 20µA Quiescent Current

www.maximintegrated.com Maxim Integrated

│

Typical Operating Circuit

Note: Insert the desired suffix letter (from Selector Guide) into the blank to indicate buck 2 switching frequency and spread

spectrum.

/V denotes an automotive qualified part.

+Denotes a lead(Pb)-free/RoHS-compliant package.

(SW) = Side-wettable TQFN package.

*EP = Exposed pad.

PART TEMP RANGE PIN-PACKAGE

MAX16932ATI_/V+ -40°C to +125°C 28 TQFN-EP*

MAX16932CATI_/V+ -40°C to +125°C 28 TQFN-EP*

MAX16932CATI_/VY+ -40°C to +125°C 28 (SW) TQFN-EP*

MAX16933ATI_/V+ -40°C to +125°C 28 TQFN-EP*

MAX16933CATI_/V+ -40°C to +125°C 28 TQFN-EP*

MAX16933CATI_/VY+ -40°C to +125°C 28 (SW) TQFN-EP*

PACKAGE

TYPE

PKG

CODE

OUTLINE

NO.

LAND

PATTERN

NO.

28 TQFN-EP T2855+5 21-0140 90-0025

28 (SW) TQFN-EP T2855Y+6 21-1000041 90-0026

PART BUCK 1 SWITCHING FREQUENCY

(fSW1)

BUCK 2 SWITCHING FREQUENCY

(fSW2)

SPREAD

SPECTRUM (%)

MAX16932ATIR/V+ 1MHz to 2.2MHz fSW1 —

MAX16932ATIT/V+ 1MHz to 2.2MHz 1/2fSW1 —

MAX16932CATIR/VY+ 1MHz to 2.2MHz fSW1 —

MAX16932CATIS/V+ 1MHz to 2.2MHz fSW1 6

MAX16932CATIS/VY+ 1MHz to 2.2MHz fSW1 6

MAX16932CATIU/V+ 1MHz to 2.2MHz 1/2fSW1 6

MAX16933ATIR/V+ 200kHz to 1MHz fSW1 —

MAX16933CATIR/VY+ 200kHz to 1MHz fSW1 —

MAX16933CATIS/V+ 200kHz to 1MHz fSW1 6

MAX16933CATIS/VY+ 200kHz to 1MHz fSW1 6

MAX16932/MAX16933 2.2MHz, 36V, Dual Buck

with 20µA Quiescent Current

www.maximintegrated.com Maxim Integrated

│

Package Information

For the latest package outline information and land patterns

(footprints), go to www.maximintegrated.com/packages. Note

that a “+”, “#”, or “-” in the package code indicates RoHS status

only. Package drawings may show a different suffix character, but

the drawing pertains to the package regardless of RoHS status.

Chip Information

PROCESS: BiCMOS

Selector Guide

Ordering Information

REVISION

NUMBER

REVISION

DATE DESCRIPTION PAGES

CHANGED

0 6/13 Initial release —

1 8/13 Duty Cycle Range in Electrical Characteristics changed to Maximum Duty Cycle and

min/typ/max values updated 3

2 2/14 Updated PGOOD1 latchup references 10, 13, 22

3 1/15 Updated Benets and Features section 1

4 7/15

Changed MAX16932ATIS/V+ to MAX16932BATIS/V+, MAX16932ATIU/V+ to

MAX16932BATIU/V+, and MAX16933ATIS/V+ to MAX16933BATIS/V+, updating

Electrical Characteristics, TOCs 25–27, Spread Spectrum and Buck 2 Switching

Frequency sections, and the Selector Guide; added MAX16932BATI_/V+ and

MAX16933BATI_/V+ future product variants to Ordering Information

3, 8, 12, 23

5 8/15 Added spread-spectrum percentage for the MAX16932BATIS/V+ in Selector Guide 23

6 1/16 Removed future product designations in Ordering Information 23

7 4/16 Added future products (MAX16932CATIS/V+, MAX16932CATIU/V+, and

MAX16933CATIS/V+) to the Selector Guide 23

8 6/16

Globally changed MAX16932B to MAX16932C and MAX16933B to MAX16933C in

the Electrical Characteristics, Typical Operating Characteristics, Spread Spectrum,

and Buck 2 Switching Frequency sections; removed the MAX16932BATIS/V+.

MAX16932BATIU/V+, and MAX16933BATIS/V+ variants and deleted all future product

asterisks in the Selector Guide; changed MAX16932BATI_V+ to MAX16932CATI_V+

and MAX16933BATI_V+ to MAX16933CATI_V+ in Ordering Information, and deleted

the future parts footnote at the bottom of the table

3, 9, 12, 23

9 6/17

Added MAX16932CATIR/VY+, MAX16932CATIS/VY+, MAX16933CATIR/VY+,

and MAX16933CATIS/VY+ to the Selector Guide as future products; added

MAX16932CATI_/VY+ and MAX16933CATI_/VY+ to Ordering Information, and 28

(SW) TQFN-EP to Package Information

10 9/17

Removed future product asterisks on the MAX16932CATIR/VY+,

MAX16932CATIS/VY+, MAX16933CATIR/VY+, and MAX16933CATIS/VY+ in the

Selector Guide

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses

are implied. Maxim Integrated reserves the right to change the circuitry and specications without notice at any time. The parametric values (min and max limits)

shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.

MAX16932/MAX16933 2.2MHz, 36V, Dual Buck

with 20µA Quiescent Current

│

Revision History

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MAX16932ATIU/V+T MAX16932ATIU/V+ MAX16932ATIR/V+ MAX16932ATIT/V+ MAX16932ATIS/V+

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MAX16933ATIR/V+T