March 1998
FDN337N
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description Features
Absolute Maximum Ratings TA = 25oC unless other wise noted
Symbol Parameter FDN337NUnits
VDSS Drain-Source Voltage 30 V
VGSS Gate-Source Voltage - Continuous ±8V
IDDrain/Output Current - Continuous 2.2 A
- Pulsed 10
PDMaximum Power Dissipation (Note 1a)0.5 W
(Note 1b) 0.46
TJ,TSTG Operating and Storage Temperature Range -55 to 150 °C
THERMAL CHARACTERISTICS
RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 250 °C/W
RθJC Thermal Resistance, Junction-to-Case (Note 1) 75 °C/W
FDN337N Rev.C
2.2 A, 30 V, RDS(ON) = 0.065 @ VGS = 4.5 V
RDS(ON) = 0.082 @ VGS = 2.5 V.
Industry standard outline SOT-23 surface mount
package using proprietary SuperSOTTM-3 design for
superior thermal and electrical capabilities.
High density cell design for extremely low RDS(ON).
Exceptional on-resistance and maximum DC current
capability.
SuperSOTTM-3 N-Channel logic level enhancement mode
power field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance. These devices are particularly suited for
low voltage applications in notebook computers, portable
phones, PCMCIA cards, and other battery powered circuits
where fast switching, and low in-line power loss are needed
in a very small outline surface mount package.
SOT-23 SuperSOTTM-8 SOIC-16
SO-8 SOT-223
SuperSOTTM-6
G
D
S
SuperSOT -3
TM
337
D
S
G
© 1998 Fairchild Semiconductor Corporation
Electrical Characteristics (TA = 25 OC unless otherwise noted )
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 30 V
BVDSS/TJBreakdown Voltage Temp. Coefficient ID = 250 µA, Referenced to 25 oC41 mV/ oC
IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V 1µA
TJ = 55°C 10 µA
IGSSF Gate - Body Leakage, Forward VGS = 8 V,VDS = 0 V 100 nA
IGSSR Gate - Body Leakage, Reverse VGS = -8 V, VDS = 0 V -100 nA
ON CHARACTERISTICS (Note)
VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA0.4 0.7 1V
VGS(th)/TJGate Threshold Voltage Temp. Coefficient ID = 250 µA, Referenced to 25 oC-2.3 mV/ oC
RDS(ON) Static Drain-Source On-Resistance VGS = 4.5 V, ID = 2.2 A 0.054 0.065
TJ =125°C 0.08 0.11
VGS = 2.5 V, ID = 2 A0.07 0.082
ID(ON) On-State Drain Current VGS = 4.5 V, VDS = 5 V 10 A
gFS Forward Transconductance VDS = 5 V, ID = 2.2 A 13 S
DYNAMIC CHARACTERISTICS
Ciss Input Capacitance VDS = 10 V, VGS = 0 V,
f = 1.0 MHz 300 pF
Coss Output Capacitance 145 pF
Crss Reverse Transfer Capacitance 35 pF
SWITCHING CHARACTERISTICS (Note)
tD(on)Turn - On Delay Time VDD = 5 V, ID = 1 A,
VGS = 4.5 V, RGEN = 6 4 10 ns
trTurn - On Rise Time 10 18 ns
tD(off) Turn - Off Delay Time 17 28 ns
tfTurn - Off Fall Time 4 10 ns
QgTotal Gate Charge VDS = 10 V, ID = 2.2 A,
VGS = 4.5 V 7 9 nC
Qgs Gate-Source Charge 1.1 nC
Qgd Gate-Drain Charge 1.9 nC
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
ISMaximum Continuous Drain-Source Diode Forward Current 0.42 A
VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = 0.42 A (Note)0.65 1.2 V
Note:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by
design while RθCA is determined by the user's board design.
Typical RθJA using the board layouts shown below on FR-4 PCB in a still air environment :
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
FDN337N Rev.C
a. 250oC/W when mounted on a
0.02 in2 pad of 2oz Cu. b. 270oC/W when mounted on
a 0.001 in2 pad of 2oz Cu.
FDN337N Rev.C
00.3 0.6 0.9 1.2 1.5
0
1
2
3
4
5
6
V , DRAIN-SOURCE VOLTAGE (V)
I , DRAIN-SOURCE CURRENT (A)
2.5
V = 4.5V
GS
2.0
1.5
DS
D
3.0
01234 5 6
0.8
1
1.2
1.4
1.6
1.8
2
I , DRAIN CURRENT (A)
DRAIN-SOURCE ON-RESISTANCE
V = 2.0V
GS
3.5
3.0
4.5
D
2.5
R DS(ON), NORMALIZED
Typical Electrical Characteristics
Figure 1. On-Region Characteristics.Figure 2. On-Resistance Variation with
Drain Current and Gate
-50 -25 025 50 75 100 125 150
0.6
0.8
1
1.2
1.4
1.6
T , JUNCTION TEMPERATURE (°C)
DRAIN-SOURCE ON-RESISTANCE
J
V = 4.5 V
GS
I = 2.2A
D
R , NORMALIZED
DS(ON)
Figure 3. On-Resistance Variation
with Temperature.
00.5 11.5 22.5
0
1
2
3
4
5
6
7
V , GATE TO SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
25°C
125°C
V = 5.0V
DS
GS
D
T = -55°C
J
Figure 5. Transfer Characteristics.
00.2 0.4 0.6 0.8 1
0.0001
0.001
0.01
0.1
0.5
2
4
V , BODY DIODE FORWARD VOLTAGE (V)
I , REVERSE DRAIN CURRENT (A)
T = 125°C
J
25°C
-55°C
V = 0V
GS
SD
S
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
12345
0
0.05
0.1
0.15
0.2
0.25
V , GATE TO SOURCE VOLTAGE (V)
GS
R , ON-RESISTANCE (OHM)
DS(ON)
125°C
25°C
I = 1.1A
D
FDN337N Rev.C
02468
0
1
2
3
4
5
Q , GATE CHARGE (nC)
V , GATE-SOURCE VOLTAGE (V)
g
GS
I = 2.2A
D
15V
V = 5V
DS
10V
0.1 0.5 1 2 510 20 50
0.01
0.03
0.1
0.3
1
2
5
10
20
V , DRAI N-SOURCE VOLTAGE (V)
I , DRAIN CURRENT (A)
DS
D
DC
1s
100ms
10s
1ms
RDS(ON) LIMIT
V = 4.5V
SINGLE PULSE
R =250 °C/W
T = 25°C
GS
A
θJA
10ms
0.0001 0.001 0.01 0.1 1 10 100 300
0
10
20
30
40
50
SINGLE PULSE TIME (SEC)
POWER (W)
SINGLE PULSE
R =270° C/W
T = 25°C
θJA
A
Figure 10. Single Pulse Maximum Power
Dissipation.
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in note 1b.
Transient thermal response will change depending on the circuit board design.
0.1 0.2 0.5 1 2 5 10 20
20
50
100
200
500
1000
V , DRAIN TO SOURCE VOLTAGE (V)
CAPACITANCE (pF)
DS
C
iss
f = 1 MHz
V = 0V
GS
C
oss
C
rss
Figure 8. Capacitance Characteristics.Figure 7. Gate Charge Characteristics.
Figure 9. Maximum Safe Operating Area.
Typical Electrical Characteristics (continued)
0.0001 0.001 0.01 0.1 110 100 300
0.001
0.002
0.005
0.01
0.02
0.05
0.1
0.2
0.5
1
t , TIME (sec)
TRANSIENT THERMAL RESISTANCE
R (t) = r(t) * R
R = 270 °C/W
Duty Cycle, D = t /t
1 2
θJA
θJA
θJA
T - T = P * R (t)
θJA
A
J
P(pk)
t
1 t
2
r(t), NORMALIZED EFFECTIVE
1
Single Pulse
D = 0.5
0.1
0.05
0.02
0.01
0.2
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
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not intended to be an exhaustive list of all such trademarks.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
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