FSQ500HL - Fairchild - Datasheet.Company

April 2012

FSQ500L • Rev. 1.0.3

FSQ500L — Compact, Green Mode, Fairchild Power Switch (FPS™)

FSQ500L

Compact, Green Mode, Fairchild Power Switch (FPS™)

Features

 Single Chip 700V SenseFET Power Switch

 Precision Fixed Operating Frequency: 130kHz

 No-load consumption 250mW at 265VAC with

Burst Mode and Down to 60mW with External Bias

 Internal Startup Switch

 Soft-Start Time Tuned by External Capacitor

 Under-Voltage Lockout (UVLO) with Hysteresis

 Pulse-by-Pulse Current Limit

 Overload Protection (OLP) and Internal Thermal

Shutdown Function (TSD) with Hysteresis

 Auto-Restart Mode

 No Need for Auxiliary Bias Winding

Applications

 Cost-Effective Linear Power Supplies Replacement

 Charger and Adapter for Mobile Phone, PDA, MP3,

and Cordless Phone

Related Resources

 AN4137 — Design Guidelines for Off-line Flyback

Converters Using Fairchild Power Switch (FPS™)

 AN4141 — Troubleshooting and Design Tips for

Fairchild Power Switch (FPS™) Flyback

Applications

 AN-4147 — Design Guidelines for RCD Snubber of

Flyback Converters

 AN-6075 — Compact Green Mode Adapter Using

FSQ500L for Low Cost

 AN-4138 — Design Considerations for Battery

Charger Using Green Mode Fairchild Power Switch

(FPS™)

 Evaluation Board: FEBFSQ500L_H257v1

Description

The FSQ500L is specially designed for a replacement of

linear power supplies with low cost. This device

combines current-mode Pulse Width Modulator (PWM)

with a senseFET. The integrated PWM controller

features include: a fixed oscillator, Under Voltage

Lockout (UVLO) protection, Overload Protection (OLP),

Leading-Edge Blanking (LEB), an optimized gate turn-

on/turn-off driver, Thermal Shutdown (TSD) protection

with hysteresis, and temperature-compensated

precision-current sources for loop compensation. When

compared to a linear power supply, the FSQ500L device

reduces total size and weight, while increasing

efficiency, productivity, and system reliability. This

device provides a basic platform for cost-effective

flyback converters.

Maximum Output Power(1)

230VAC ± 15%(2) 85-265VAC

Adapter(3) Open

Frame(4) Adapter(3) Open

Frame(4)

2.5W 3.0W 2.0W 2.5W

Notes:

1. The junction temperature can limit the maximum

output power.

2. 230VAC or 100/115VAC with doubler.

3. Typical continuous power in a non-ventilated

enclosed adapter measured at 50°C ambient.

4. Maximum practical continuous power in an open

frame design at 50°C ambient.

Ordering Information

Part Number Operating

Temperature Range Package Packing Method

FSQ500L -40°C to +85°C 4-Lead, Small Outline Package (SOT223-4L) Tape & Reel

FSQ500L • Rev. 1.0.3 2

FSQ500L — Compact, Green Mode, Fairchild Power Switch (FPS™)

Application Circuit Diagram

GNDVFB VCC

IN DC

OUT

PWM

Figure 1. Typical Application Circuit

Internal Block Diagram

OSC

Rsense

(0.3V)

OLP

TSD

LEB

IFB

R250ns

VREF UVLO

HV/REG

6.5V

HV/REG OFF

GND

VCC

VFB

VBURL/VBURH

VOLP

A/R

VCC VCC

Soft-Soft

7.7VZ

IDELAY

VSD

(BURST MODE:IFB/2)

Figure 2. Internal Block Diagram

FSQ500L • Rev. 1.0.3 3

FSQ500L — Compact, Green Mode, Fairchild Power Switch (FPS™)

Pin Assignments

GND

VCC VFBD

FSQ500L

Figure 3. Package / Pin Diagram

Pin Definitions

Pin # Name Description

1 D

High-voltage power senseFET drain connection. In addition, at startup, the internal high-voltage

current source supplies internal bias and charges the external capacitor connected to the VCC pin.

Once VCC reaches 6.0V, all internal blocks are activated. The internal high-voltage current source

is alive until VCC reaches 6.5V. After that, the internal high voltage current source turns on and off

irregularly to maintain VCC at 6.5V.

2 VCC

This pin is connected to a storage capacitor. A high-voltage regulator connected between pin 1 (D)

and this pin provides the supply voltage to the FSQ500L at startup and when switching during

normal operation. The FSQ500L eliminates the need for auxiliary bias winding and associated

external components.

3 VFB

This pin is internally connected to the non-inverting input of the PWM comparator. The collector of

an opto-coupler is typically tied to this pin. For stable operation, a capacitor should be placed

between this pin and GND. If the voltage of this pin reaches 4.5V, the overload protection triggers,

which shuts down the FPS.

4 GND This pin is the control ground and the senseFET source.

FSQ500L • Rev. 1.0.3 4

FSQ500L — Compact, Green Mode, Fairchild Power Switch (FPS™)

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

VDS Drain Pin Voltage(5) 700 V

VCC Supply Voltage 10 V

VFB Feedback Voltage Range -0.3 VCC V

PD Total Power Dissipation 0.78 W

IDM Drain Current Pulsed(6) 0.41 A

TJ Operating Junction Temperature -40 Internally Limited

°C

TSTG Storage Temperature -55 +150 °C

Notes:

5. LDMOS available drain voltage is -0.3V ~ 700V.

6. Repetitive rating: pulse width is limited by maximum junction temperature.

Thermal Impedance

Symbol Parameter Value Unit

θJA Junction-to-Ambient Thermal Resistance(7) +160 °C/W

Note:

7. Free-standing with no heat sink; minimum land pattern.

FSQ500L • Rev. 1.0.3 5

FSQ500L — Compact, Green Mode, Fairchild Power Switch (FPS™)

Electrical Characteristics

TJ = 25°C unless otherwise specified.

Symbol Parameter Condition Min. Typ. Max. Unit

SenseFET Section

BVDSS Drain-Source Breakdown Voltage VCC = 6.5V, VFB = 0V, ID = 150μA 700 V

IDSS Zero-Gate-Voltage Drain Current VCC = 6.5V, VFB = 0V, VDS = 560V 150 μA

RDS(ON) Drain-Source On-State Resistance TJ = 25°C, ID = 25mA 25 29

TJ = 100°C, ID = 25mA 35 41

CISS Input Capacitance(8) V

GS = 6.5V 42 pF

COSS Output Capacitance(8) V

DS = 40V, fS = 1MHz 25 pF

tr Rise Time(8) V

DS = 350V, ID = 25mA 100 ns

tf Fall Time(8) V

DS = 350V, lD = 25mA 50 ns

Control Section

fS Switching Frequency VCC = 6.5V, VFB = 1.0V 120 130 140 kHz

ΔfS Switching Frequency Variation(8) -25°C < TJ < 125°C ±5 ±7 %

IFB(Burst) Feedback Source Current VCC = 6.5V, VFB = 0V 98 110 122 μA

IFB(Normal) VCC = 6.5V 200 225 250 μA

DMAX Maximum Duty Ratio VCC = 6.5V, VFB = 4.0V 54 60 66 %

DMIN Minimum Duty Ratio VCC = 6.5V, VFB = 0V 0 %

VSTART UVLO Threshold Voltage VFB = 0V, VCC Sweep 5.5 6.0 6.5 V

VSTOP After Turn-on, VFB = 0V, VCC Sweep 4.5 5.0 5.5 V

VDLY_EN Shutdown Delay Current Enable

Voltage VFB = VSD, VCC Sweep from 6V 6.0 6.5 7.0 V

Burst-Mode Section

VBURH

Burst Mode Voltage VCC = 6.5V, VFB Sweep

0.75 0.80 0.85 V

VBURL 0.70 0.75 0.80 V

HYS 30 50 80 mV

Protection Section

ILIM Peak Current Limit di/dt = 150mA/µs 245 280 315 mA

VSD Shutdown Feedback Voltage VCC = 6.5V, VFB Sweep 4.1 4.5 4.9 V

IDELAY Shutdown Delay Current VCC = 6.5V, VFB = 4.0V 4 5 6 μA

tLEB Leading Edge Blanking Time(8) 250 ns

tCLD Current Limit Delay Time(8) 100 ns

TDS Thermal Shutdown Temperature(8) 130 140 150

°C

HYS 80

°C

Total Device Section

IOP-BURST Operating Supply Current (Control

Part Only)

VCC = 6.5V, VFB = 0V 360 430 500 μA

IOP-FB VCC = 6.5V, VFB = 4V 640 760 880 μA

ICH Startup Charging Current VCC = VFB = 0V, VDS = 40V 3.3 mA

VCCREG Supply Shunt Regulator VDS = 40V, VFB = 0V 6.0 6.5 7.0 V

VCCREG_

TSD Supply Shunt Regulator During

TSD(8) 5.2 5.7 6.2 V

Note:

8. These parameters, although guaranteed, are not 100% tested in production.

FSQ500L • Rev. 1.0.3 6

FSQ500L — Compact, Green Mode, Fairchild Power Switch (FPS™)

Typical Performance Characteristics

These characteristic graphs are measured at TA = 25°C.

Operating Supply Current (IOP) vs Temperature

370

390

410

430

450

470

490

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (℃)

IOP (μA)

Sw itching Frequency (f

) vs Temperature

120

125

130

135

140

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (℃)

(KHZ)

Figure 4. Operating Supply Current (IOP_Burst)

vs. Temperature

Figure 5. Switching Frequency (fS)

vs. Temperature

UVLO Threshold Voltage (V

START

) vs Temperature

5.5

5.7

5.9

6.1

6.3

6.5

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (℃)

START

(V)

UVLO Threshold Voltage (VSTOP) vs Temperature

4.5

4.7

4.9

5.1

5.3

5.5

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (℃)

VSTOP (V)

Figure 6. UVLO Threshold Voltage (VSTART)

vs. Temperature

Figure 7. UVLO Threshold Voltage (VSTOP)

vs. Temperature

Burst Mode Voltage (V

BURH

) vs Temperature

750

770

790

810

830

850

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (℃)

BURH

(mV)

Burst Mode Voltage (V

BURL

) vs Temperature

700

720

740

760

780

800

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (℃)

BURL

(mV)

Figure 8. Burst-Mode Voltage (VBURH)

vs. Temperature

Figure 9. Burst-Mode Voltage (VBURL)

vs. Temperature

FSQ500L • Rev. 1.0.3 7

FSQ500L — Compact, Green Mode, Fairchild Power Switch (FPS™)

Typical Performance Characteristics (Continued)

These characteristic graphs are measured at TA = 25°C.

Maximum Duty Ratio (D

MAX

) vs Temperature

56.0

57.0

58.0

59.0

60.0

61.0

62.0

63.0

64.0

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (℃)

MAx

(%)

Shutdown Feedback Voltage (V

) vs Temperature

4.0

4.2

4.4

4.6

4.8

5.0

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (℃)

(V)

Figure 10. Maximum Duty Ratio (DMAX) vs. Temperature Figure 11. Shutdown Feedback Voltage (VSD)

vs. Temperature

Peak Current Limit (I

LIM

) vs Temperature

240.0

250.0

260.0

270.0

280.0

290.0

300.0

310.0

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (℃)

LIM

(mA)

Shutdown Delay Current (I

DELAY

) vs Temperature

4.5

4.7

4.9

5.1

5.3

5.5

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (℃)

DELAY

(μA)

Figure 12. Peak Current Limit (ILIM) vs. Temperature Figure 13. Shutdown Delay Current (IDELAY)

vs. Temperature

Supply Shunt Regulator (V

CCREG

) vs Temperature

6.0

6.2

6.4

6.6

6.8

7.0

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (℃)

CCRGE

(V)

Figure 14. Supply Shunt Regulator (VCCREG)

vs. Temperature

FSQ500L • Rev. 1.0.3 8

FSQ500L — Compact, Green Mode, Fairchild Power Switch (FPS™)

Functional Description

1. Startup and VCC Regulation: At startup, an internal

high-voltage current source supplies the internal bias

and charges the external capacitor (CA) connected to

the VCC pin, as illustrated in Figure 15. An internal high-

voltage regulator (HV/REG) located between the D and

VCC pins regulates the VCC to be 6.5V and supplies

operating current. Therefore, FSQ500L needs no

auxiliary bias winding.

VREF UVLO

HV/REG

6.5V

VCC

Transformer

ICH

ISTART

Figure 15. Startup Block

2. Feedback Control: FSQ500L employs current mode

control, as shown in Figure 16. An opto-coupler (such as

the FOD817A) and shunt regulator (such as the KA431)

are typically used to implement the feedback network.

Comparing the feedback voltage with the voltage across

the Rsense resistor makes it possible to control the

switching duty cycle. When the reference pin voltage of

the regulator exceeds the internal reference voltage of

2.5V, the opto-coupler LED current increases, pulling

down the feedback voltage and reducing the duty cycle.

This typically happens when the line input voltage

increases or the output load current decreases.

2.1 Pulse-by-Pulse Current Limit: Because current

mode control is employed, the peak current through the

senseFET is limited by the non-inverting input of PWM

comparator (VFB*), as shown in Figure 16. Assuming

that 225µA current source flows only through the

internal resistor (8R + R = 12kΩ), the cathode voltage of

diode D2 is about 2.7V. Since D1 is blocked when the

feedback voltage (VFB) exceeds 2.7V, the maximum

voltage of the cathode of D2 is clamped at this voltage,

clamping VFB*. Therefore, the peak value of the current

through the senseFET is limited.

2.2 Leading-Edge Blanking (LEB): At the instant the

internal senseFET is turned on, a high-current spike

occurs through the senseFET, caused by primary-side

capacitance and secondary-side rectifier reverse

recovery. Excessive voltage across the Rsense resistor

would lead to incorrect feedback operation in the current

mode PWM control. To counter this effect, the FPS

employs a leading-edge blanking (LEB) circuit. This

circuit inhibits the PWM comparator for a short time (tLEB

= 250ns) after the senseFET turns on.

2OSC

VCC

IDELAY IFB

VSD

Gate

driver

OLP

D1 D2

VFB*

VFB

KA431

FOD817A

Rsense

SenseFET

VCC

Figure 16. Pulse Width Modulation (PWM) Circuit

3. Protection Circuits: The FSQ500L has two self-

protective functions: overload protection (OLP) and

thermal shutdown (TSD). While OLP is implemented as

auto-restart mode, there is no switching when TSD

triggers. Once the overload condition is detected,

switching is terminated, the senseFET remains off, and

HV/REG turns off. This causes VCC to fall. When VCC

falls below the under voltage lockout (UVLO) stop

voltage of 5.0V, the protection is reset and the startup

circuit charges the VCC capacitor. When VCC reaches the

start voltage of 6.0V, the FSQ500L resumes its normal

operation. If the fault condition is still not removed, the

senseFET and HV/REG remain off and VCC drops to

VSTOP again. In this manner, the auto-restart can

alternately enable and disable the switching of the

power senseFET until the fault condition is eliminated,

as shown in Figure 17.

Because these protection circuits are fully integrated

into the IC without external components, reliability is

improved without increasing cost.

Fault

situation

5.0V

6.0V

VCC

VDS

OLP

occurs OLP

removed

Normal

operation

Normal

operation

Power

6.5V

Figure 17. Auto Restart Protection Waveforms

FSQ500L • Rev. 1.0.3 9

FSQ500L — Compact, Green Mode, Fairchild Power Switch (FPS™)

3.1 Overload Protection (OLP): Overload is defined as

the load current exceeding its normal level due to an

unexpected abnormal event. In this situation, the

protection circuit should trigger to protect the SMPS.

However, even when the SMPS is in the normal

operation, the overload protection circuit can be

triggered during the load transition. To avoid this

undesired operation, the overload protection circuit is

designed to trigger after a specified time to determine

whether the situation is transient or a true overload.

Because of the pulse-by-pulse current limit capability,

the maximum peak current through the senseFET is

limited and, therefore, the maximum input power is

restricted with a given input voltage. If the output

consumes more than this maximum power, the output

voltage (VO) decreases below the set voltage. This

reduces the current through the opto-coupler LED,

which also reduces the opto-coupler transistor current,

thus increasing the feedback voltage (VFB). If VFB

exceeds 2.7V, D1 is blocked and the 5µA current source

starts to charge CB slowly up to VCC. In this condition,

VFB continues increasing until it reaches 4.5V, when the

switching operation is terminated, as shown in Figure

18. The delay time for shutdown is the time required to

charge CB from 2.7V to 4.5V with 5µA. In general, a 10

~ 50ms delay time is typical for most applications. This

protection is implemented in auto restart mode.

VFB

2.7V

4.5V

Overload protection

T12= CB*(4.5-2.7)/IDELAY

T1T2

Figure 18. Overload Protection

3.2 Thermal Shutdown (TSD): The senseFET and the

control IC in one package makes it easy for the control

IC to detect an abnormal over temperature of the

senseFET. When the temperature exceeds

approximately 140°C, the thermal shutdown triggers.

When TSD triggers, delay current is disabled, switching

operation stops, and VCC through the internal high-

voltage current source is set to 5.7V from 6.5V, as

shown in Figure 19. Since TSD signal prohibits the

senseFET from switching, there is no switching until the

junction temperature decreases sufficiently. If the

junction temperature is lower than 60°C typically, TSD

signal is removed and VCC is set to 6.5V again. While

VCC increases from 5.7V to 6.5V, the soft-start function

makes the senseFET turn on and off with no voltage

and/or current stress.

Fault

situation

5.7V

6.0V

VCC

VDS

TSD

occurs

TSD

removed

Normal

operation

Normal

operation

Power

6.5V

Figure 19. Over-Temperature Protection (OTP)

4. Soft-Start: The soft-start time is tuned by an external

VCC capacitor (CA), which increases PWM comparator

non-inverting input voltage together with the senseFET

current slowly after it starts up. Before VCC reaches

VSTART, CA is charged by the current ICH-ISTART, where ICH

and ISTART are described in Figure 15. After VCC reaches

VSTART, all internal blocks are activated, so that the

current consuming inside IC becomes IOP. Therefore, CA

is charged by the current ICH-IOP, which makes the

increasing slope of VCC become sluggish. VCC is shifted

by 6.0V negatively (it is performed in soft-start block in

Figure 2), and then VCC -6.0V is an input of one of the

input terminals of the PWM comparator. The drain

current follows VCC -6.0V instead of the VFB* because of

the low-dominant feature of the PWM comparator. The

soft-start time can be made long or short by selecting

CA, as described in Figure 20. During tS/S, IDELAY is

disabled to avoid unwanted OLP. Typically, tS/S is

around 4.6ms with 27µF of CA.

VCC

VSTART

VSTOP

VCCREG

t1t2

t1=CA×6V/(ICH-ISTART) tS/S=CA×0.5V/(ICH-IOP)

6.5V

tS/S

Figure 20. Soft-Start Function

The peak value of the drain current of the power

switching device is progressively increased to establish

the correct working conditions for transformers,

inductors, and capacitors. The voltage on the output

capacitors is progressively increased with the intention

of smoothly establishing the required output voltage. It

also helps to prevent transformer saturation and reduce

stress on the secondary diode during startup.

FSQ500L • Rev. 1.0.3 10

FSQ500L — Compact, Green Mode, Fairchild Power Switch (FPS™)

5. Burst Operation: To minimize power dissipation in

standby mode, the FPS enters burst-mode operation.

During the burst mode operation, IFB(Burst) decreases half

of IFB(Normal). As the load decreases, the feedback

voltage decreases. As shown in Figure 21, the device

automatically enters burst mode when the feedback

voltage drops below VBURL (750mV). At this point,

switching stops and the output voltages start to drop at a

rate dependent on standby current load. This causes the

feedback voltage to rise. Once it passes VBURH (800mV),

switching resumes. The feedback voltage then falls and

the process repeats. Burst mode alternately enables

and disables switching of the power senseFET, reducing

switching loss in standby mode.

VFB

VDS

0.75V

0.80V

IDS

Voset

time

Switching

disabled

t1t2t3

Switching

disabled t4

Figure 21. Burst-Mode Operation

FSQ500L • Rev. 1.0.3 11

FSQ500L — Compact, Green Mode, Fairchild Power Switch (FPS™)

Package Dimensions

Figure 22. 4-Lead, Small Outline Package (SOT223-4L)

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package specifications do not expand the terms of Fairchild’ s worldwide terms and conditions, specifically the

warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

FSQ500L • Rev. 1.0.3 12

FSQ500L — Compact, Green Mode, Fairchild Power Switch (FPS™)