ANYFLOW 5500
PRODUCT OVERVIEW
NETWORKS
Product Description:
The AnyFlow 5500 Network Processor is the first member of the AnyFlow 5000 family. It provides network
equipment vendors with a software-programmable silicon “engine” that breaks through the performance
barrier of RISC-based switches and routers while enabling the extensive features and functionality
previously missing in ASIC-based switches and routers. The instruction set of the AnyFlow 5500 contains the
base-level functionality to examine, modify and make wire-speed switching decisions at Layers 2 through 7
of the OSI model, while simultaneously providing Per-Flow Queuing™, packet/cell internetworking, and
multicast capabilities. These base level instructions can be combined in an infinite number of ways by the
higher level software of network equipment vendors to build highly differentiated switches and routers with
a throughput of up to 20 Gbps. The AnyFlow 5500 provides support for 10/100 Mbps Ethernet, Gigabit
Ethernet, HDLC, Packet Over Sonet (POS) and ATM interfaces.
A Flexible and Feature-Rich Chip Set
Figure 1: A logical representation - Features of the AF5500 and BitStream Network Processors
MMC Networks’ AF5500 chip set implements the complete core
functionality of high-performance, feature-rich combined packet and cell
switches. The chip set is architected to provide seamless internetworking
between the cell and packet worlds, through its powerful Per-Flow
Queuing™ and Per-Flow Scheduling™ technologies.
The flexibility of the chip set’s architecture makes it an optimum choice for
a wide variety of applications, including enterprise, workgroup and access
switches and routers. Indeed, the chip set can be configured to switch
ATM cells, route IP packets, multicast disparate connections and apply
queuing and scheduling algorithms that ensure differentiated quality of
service for thousands of flows with sophisticated fairness techniques such as weighted fair queuing.
Ingress
Processing
Switching
Queuing
Scheduling
Egress
Processing
Route Lookup
Classification
Set Precedence
Access Lists
Statistics
NAT….
Packet and Cell
Non-blocking
Unicast and Multicast
Per Flow Queues
Packet Reassembly
Shared Memory
Dynamic Discard Thresholds
Bandwidth Allocation
Hierarchical Weighted Fair Queuing
Differentiated QoS
Encapsulation
Statistics…
Ingress
Egress
ANYFLOW 5500 PRODUCT OVERVIEW
NETWORKS
Simplifying Switch Componentry
Based on MMC Networks’ ViX™ interconnect architecture, the AF5500 delivers full-duplex, non-blocking
bandwidth from 2.5 Gbps to 20 Gbps. A typical 2.5 Gbps switch can be designed with a single AF5500 chip
set, as illustrated in Figure 2 below.
Figure 2: AF5500 Architecture - A 2.5 Gbps switch showing ATM and Fast Ethernet interfaces
The constituent parts of a 2.5 Gbps AF5500 comprise:
• One Control Module containing:
• Modular Switch Cont roller 1 and 2 (MSC1, MSC2)
• Per-Flow Queuing Controller (PFQ)
• Per-Flow Scheduler (PFS)
• Four Port Interfaces made up of:
• Up to f our Por t I nter fa ces (P IF2s) , w ith f ou r po r ts of OC-3 ATM or on e p ort o f OC- 12 c ATM ea ch
• Up to four Fast Ether net Port Interf aces (EPIFs) , with four por ts of 10bT/1 00bT Ether net each
• Up to t wo Giga bit Po r t In terf ace s, wit h one p ort of 1 000 bT E the r net e ach
• Two Memory Access Buffers (MBUF2s)
• ViX™ Interconnect logic
• Associated ancillary components including low-speed synchronous SRAM, user-specified CPU, standard
physical interface circuitry, address-generation logic
Larger switches, with capacities of up to 20 Gbps, can be built by simply combining multiple 2.5 Gbps blocks.
Memory
Control
Memory
Data
Note: Two Fast Ethernet BitStream Processors can be replaced by one Gigabit Ethernet BitStream Processor.
Control Module
MSC1 PFQ
MSC2 PFS
MBUF2 MBUF2
PIF2 PIF2 EPIF EPIF
Control
Memory
ViX - Patented Interconnect Architecture
4 x MII
4 x MII
ATM UTOPIA II
Multi-PHY ATM UTOPIA II
Mult i-PHY 10/100 Ethernet 10/100 Ethernet
Control
Memory
ANYFLOW 5500 PRODUCT OVERVIEW
MMC Networks
1143 E. Arques Avenue
Sunnyvale, CA 94086
For more information, please call (408) 731-1600. Or visit http://www.mmcnet.com
NETWORKS
AnyFlow5500 Advantages
BitStream Processing – Enables seamless packet interfaces on the AF5500, with inherent segmentation and
reassembly. Compliments ATM cell processing with versatile packet processing.
ViX Interconnect – Eliminates the need for a high-speed memory bus and replaces it with much simpler,
low-cost point-to-point connections. This means that the switch’s cost ramps in a linear fashion as the
number of ports increases, as opposed to non-ViX architectures where the cost increases exponentially.
Per-Flow Queuing – Ensures that each traffic flow is managed as a separate entity, wherein it is queued and
scheduled independently from the other flows. Congestion experienced by one flow is prevented from
interfering with the traffic conditions of other flows and thus quality of service is maintained.
Traffic Scheduling – Provides hardware scheduling of traffic on a Per-Flow basis through the support of the
following cell- and packet-based algorithms: rate, strict priority, weighted fair queuing and weighted round
robin.
Virtual SAR – Expensive external Segmentation and Reassembly (SAR) devices are not required when using
the AF5500. Instead, the SARing function is inherent in the chip set; it is a natural consequence of the way in
which the AF5500 accomplishes Per-Flow Queuing and Scheduling. Thus the term Virtual SAR.
Point-to-Point Multicast Connections – Traffic received on one input flow can be sent to one or more output
flows, either on separate output ports (physical multicast) or on the same output port (logical multicast).
Snooping – The AF5500 can output a duplicate flow to any port with an attached network protocol analyzer,
eliminating the need to move the analyzer from one switch port to another.
Flow Merging – Packets entering on separate ports can be merged to exit from a single port, as is needed in
MultiProtocol Label Switching (MPLS).
Subports and Macroports – In addition to standard OC-3/OC-12 ATM and 10/100 Ethernet ports, the
AF5500 can handle multiple slower speed pipes, such as T1, Fractional T1 and DS-0, aggregated into a single
physical port. Conversely, multiple ports can be aggregated into a single high-speed pipe. For example, up to
16 OC-3 ATM ports can be combined into a single OC-48 ATM port.
