TL/L/10222
DM54LS491A/DM74LS491A 10-Bit Counter
July 1989
DM54LS491A/DM74LS491A
10-Bit Counter
General Description
The ten-bit counter can count up, count down, set, and load
2 LSB’s, 2 MSB’s and 6 middle bits high or low as a group.
All operations are synchronous with the clock. SET over-
rides LOAD, COUNT and HOLD. LOAD overrides COUNT.
COUNT is conditional on CIN, otherwise it holds.
All outputs are enabled when OE is low, otherwise HIGH-Z.
The 24 mA IOL outputs are suitable for driving RAM/PROM
address lines in video graphics systems.
Features
YCRT vertical and horizontal timing generation
YBus-structured pinout
YLow current PNP inputs reduce loading
YTRI-STATEÉoutputs
Y24-pin SKINNYDIP saves space
Connection Diagram
Top View
TL/L/10222–1
Order Number DM54LS491AJ, DM74LS491AJ, DM74LS491AN or DM74LS491AV
See NS Package Number J24F, N24C or V28A
Function Table
OE CK SET LD CNT CIN UP D9– D0 Q9– Q0 Operation
H X X X X X X X Z Hi-Z
L
u
H X X X X X H Set all HIGH
L
u
L L X X X D D LOAD D
L
u
L H H X X X Q HOLD
L
u
L H L H X X Q HOLD
L
u
L H L L L X Q Plus 1 Count Up
L
u
L H L L H X Q Minus 1 Count Down
TRI-STATEÉis a registered trademark of National Semiconductor Corporation.
C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage, VCC 7V
Input Voltage 5.5V
Off-State Output Voltage 5.5V
Storage Temperature b65§Ctoa
150§C
ESD Tolerance l1000V
Czap e100 pF
Rzap e1500X
Test Method: Human Body Model
Test Specification: NSC SOP 5-028
Recommended Operating Conditions
Symbol Parameter Military Commercial Units
Min Typ Max Min Typ Max
VCC Supply Voltage 4.5 5 5.5 4.75 5 5.25 V
TAOperating Free-Air Temperature b55 25 0 25 75 §C
TCOperating Case Temperature 125 §C
Electrical Characteristics Series 24A Over Recommended Operating Temperature Range
Symbol Parameter Conditions Min Typ Max Units
VIH High Level Input Voltage (Note 2) 2 V
VIL Low Level Input Voltage (Note 2) 0.8 V
VIC Input Clamp Voltage VCC eMin, II eb
18 mA b0.8 b1.5 V
VOH High Level Output Voltage VCC eMin IOH eb
2 mA MIL
VIL e0.8V 2.4 2.9 V
IOH eb
3.2 mA COM
VIH e2V
VOL Low Level Output Voltage VCC eMin IOL e12 mA MIL
VIL e0.8V 0.3 0.5 V
IOL e24 mA COM
VIH e2V
IOZH Off-State Output Current VCC eMax VOe2.4V 100 mA
VIL e0.8V
IOZL (Note 3) VOe0.4V b100 mA
VIH e2V
IIMaximum Input Current VCC eMax, VIe5.5V 1 mA
IIH High Level Input Current VCC eMax, VIe2.4V 25 mA
(Note 3)
IIL Low Level Input Current VCC eMax, VIe0.4V b0.04 b0.25 mA
(Note 3)
IOS Outut Short-Circuit Current VCC e5V VOe0V (Note 4) b30 b70 b130 mA
ICC Supply Current VCC eMax 135 180 mA
Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do not mean that the device may be operated at
these values.
Note 2: These are absolute voltages with respect to the ground pin on the device and include all overshoots due to system and/or tester noise. Do not attempt to
test these values without suitable equipment.
Note 3: I/O leakage as the worst case of IOZX or IIX, e.g., IIL and IOZL.
Note 4: During IOS measurement, only one output at a time should be grounded. Permanent damage otherwise may result.
2
Switching Characteristics Over Recommended Operating Conditions
Symbol Parameter Test Condition Military Commercial Units
Min Typ Max Min Typ Max
tSSetup Time from Input 40 20 30 20 ns
tWWidth of Clock High 20 7 15 7 ns
Low 35 15 25 15 ns
tHHold Time 0 b15 0 b15 ns
tCLK Clock to Output CLe50 pF 10 25 10 15 ns
tpzx Output Enable Delay CLe50 pF 19 35 19 30 ns
tpxz Output Disable Delay CLe5pF 1535 1530 ns
f
MAX Maximum Frequency 15.3 32 22.2 32 MHz
Test Load
TL/L/10222–2
MIL COM’L
R1 e390 R1 e200
R2 e750 R2 e390
Schematic of Inputs and Outputs
TL/L/10222–3
Test Waveforms
Set-up and Hold
TL/L/10222–4
Note A: VTe1.5V.
Note B: CLincludes probe and jig capacitance.
Note B: In the examples above, the phase relationships between inputs and
outputs have been chosen arbitrarily.
Pulse Width
TL/L/10222–5
Enable and Disable
TL/L/10222–6
3
Logic Diagram
10-Bit Up/Down Counter
TL/L/10222–7
4
Physical Dimensions inches (millimeters)
24-Pin Narrow Ceramic Dual-In-Line Package (J)
Order Number DM54LS491AJ or DM74LS491AJ
NS Package Number J24F
24-Pin Narrow Plastic Dual-In-Line Package (N)
Order Number DM74LS491AN
NS Package Number N24C
5
DM54LS491A/DM74LS491A 10-Bit Counter
Physical Dimensions inches (millimeters)
28-Lead Plastic Chip Carrier (V)
Order Number DM74LS491AV
NS Package Number V28A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
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Corporation Europe Hong Kong Ltd. Japan Ltd.
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