DM54LS491A/DM74LS491A 10-Bit Counter General Description Features The ten-bit counter can count up, count down, set, and load 2 LSB's, 2 MSB's and 6 middle bits high or low as a group. All operations are synchronous with the clock. SET overrides LOAD, COUNT and HOLD. LOAD overrides COUNT. COUNT is conditional on CIN, otherwise it holds. All outputs are enabled when OE is low, otherwise HIGH-Z. The 24 mA IOL outputs are suitable for driving RAM/PROM address lines in video graphics systems. Y Y Y Y Y CRT vertical and horizontal timing generation Bus-structured pinout Low current PNP inputs reduce loading TRI-STATEE outputs 24-pin SKINNYDIP saves space Connection Diagram Top View TL/L/10222 - 1 Order Number DM54LS491AJ, DM74LS491AJ, DM74LS491AN or DM74LS491AV See NS Package Number J24F, N24C or V28A Function Table OE CK SET LD CNT CIN UP D9 - D0 Q9 - Q0 Operation H L L L L L L X X H L L L L L X X L H H H H X X X H L L L X X X X H L L X X X X X L H X X D X X X X Z H D Q Q Q Plus 1 Q Minus 1 Hi-Z Set all HIGH LOAD D HOLD HOLD Count Up Count Down u u u u u u TRI-STATEE is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/L/10222 RRD-B30M115/Printed in U. S. A. DM54LS491A/DM74LS491A 10-Bit Counter July 1989 Absolute Maximum Ratings (Note 1) ESD Tolerance Czap e 100 pF Rzap e 1500X Test Method: Human Body Model Test Specification: NSC SOP 5-028 If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage, VCC 7V Input Voltage Off-State Output Voltage Storage Temperature 5.5V 5.5V b 65 C to a 150 C l 1000V Recommended Operating Conditions Symbol Military Parameter VCC Supply Voltage TA Operating Free-Air Temperature TC Operating Case Temperature Commercial Units Min Typ Max Min Typ Max 4.5 5 5.5 4.75 5 5.25 V b 55 25 0 25 75 C 125 C Electrical Characteristics Series 24A Over Recommended Operating Temperature Range Symbol Parameter Conditions Min VIH High Level Input Voltage (Note 2) VIL Low Level Input Voltage (Note 2) VIC Input Clamp Voltage VCC e Min, II e b18 mA VOH High Level Output Voltage VCC e Min VIL e 0.8V VIH e 2V IOH e b2 mA VCC e Min VIL e 0.8V VIH e 2V IOL e 12 mA MIL IOL e 24 mA COM Off-State Output Current (Note 3) VCC e Max VIL e 0.8V VIH e 2V Maximum Input Current IIH VOL Low Level Output Voltage Typ Max 2 IOH e b3.2 mA Units V b 0.8 0.8 V b 1.5 V MIL COM 2.4 2.9 0.5 V VO e 2.4V 100 mA VO e 0.4V b 100 mA VCC e Max, VI e 5.5V 1 mA High Level Input Current (Note 3) VCC e Max, VI e 2.4V 25 mA IIL Low Level Input Current (Note 3) VCC e Max, VI e 0.4V b 0.04 b 0.25 mA IOS Outut Short-Circuit Current VCC e 5V b 70 b 130 mA ICC Supply Current VCC e Max 135 180 mA IOZH IOZL II VO e 0V (Note 4) 0.3 V b 30 Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. They do not mean that the device may be operated at these values. Note 2: These are absolute voltages with respect to the ground pin on the device and include all overshoots due to system and/or tester noise. Do not attempt to test these values without suitable equipment. Note 3: I/O leakage as the worst case of IOZX or IIX, e.g., IIL and IOZL. Note 4: During IOS measurement, only one output at a time should be grounded. Permanent damage otherwise may result. 2 Switching Characteristics Over Recommended Operating Conditions Symbol Parameter Military Test Condition Min Typ Commercial Max Min Typ Units Max tS Setup Time from Input 40 20 30 20 ns tW Width of Clock High 20 7 15 7 ns Low 35 15 25 15 ns 0 b 15 0 b 15 tH Hold Time tCLK Clock to Output CL e 50 pF 10 25 10 15 ns tpzx Output Enable Delay CL e 50 pF 19 35 19 30 ns tpxz Output Disable Delay CL e 5 pF 15 35 15 30 ns fMAX Maximum Frequency 15.3 Test Load 32 22.2 32 ns MHz Schematic of Inputs and Outputs MIL R1 e 390 R2 e 750 COM'L R1 e 200 R2 e 390 TL/L/10222-2 TL/L/10222 - 3 Test Waveforms Set-up and Hold Pulse Width TL/L/10222 - 5 TL/L/10222 - 4 Enable and Disable Note A: VT e 1.5V. Note B: CL includes probe and jig capacitance. Note B: In the examples above, the phase relationships between inputs and outputs have been chosen arbitrarily. TL/L/10222 - 6 3 Logic Diagram 10-Bit Up/Down Counter TL/L/10222 - 7 4 Physical Dimensions inches (millimeters) 24-Pin Narrow Ceramic Dual-In-Line Package (J) Order Number DM54LS491AJ or DM74LS491AJ NS Package Number J24F 24-Pin Narrow Plastic Dual-In-Line Package (N) Order Number DM74LS491AN NS Package Number N24C 5 DM54LS491A/DM74LS491A 10-Bit Counter Physical Dimensions inches (millimeters) 28-Lead Plastic Chip Carrier (V) Order Number DM74LS491AV NS Package Number V28A LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 1111 West Bardin Road Arlington, TX 76017 Tel: 1(800) 272-9959 Fax: 1(800) 737-7018 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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