HD74CBT3253T - Renesas Technology / Hitachi Semiconductor

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April 1, 2003

To all our customers

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HD74CBT3253

Dual 1-of-4 FET Multiplexer / Demultiplexer

ADE-205-616A (Z)

Rev.1

May 2001

Description

The HD74CBT3253 is a dual 1-of-4 high-speed TTL-compatible FET multiplexer / demultiplexer. The

low on-state resistance of the switch allows connections to be made with minimal propagation delay.

1OE, 2OE, S0, and S1 select the appropriate B output for the A-input data.

Features

• Minimal propagation delay through the switch.

• 5 Ω switch connection between two ports.

• TTL-compatible input levels.

• Ultra low quiescent power.

-Ideally suited for notebook applications.

HD74CBT3253

Rev.1, May 2001, page 2 of 2

Function Table

Inputs

1OE

OEOE

OE 2OE

OEOE

OE S1 S0 Function

X H X X Disconnect 1A and 2A

H X X X Disconnect 1A and 2A

L L L L 1A to 1B1 and 2A to 2B1

L L L H 1A to 1B2 and 2A to 2B2

L L H L 1A to 1B3 and 2A to 2B3

L L H H 1A to 1B4 and 2A to 2B4

H: High level

L: Low level

X: Immaterial

Pin Arrangement

1OE

1B4

1B3

1B2

1B1

GND

VCC

2B4

2B3

2B2

2B1

(Top view)

HD74CBT3253

Rev.1, May 2001, page 3 of 3

Absolute Maximum Ratings

Item Symbol Ratings Unit Conditions

Supply voltage range VCC −0.5 to 7.0 V

Input voltage range *1 V

I −0.5 to 7.0 V

Input clamp current IIK −50 mA VI < 0

Continuous output current IO 128 mA VO = 0 to VCC

Continuous current through

VCC or GND

ICC or IGND ±100 mA

Maximum power dissipation

at Ta = 25°C (in still air) *2

PT 500 mW TSSOP

Storage temperature Tstg −65 to 150 °C

Notes: The absolute maximum ratings are values which must not individually be exceeded, and

furthermore, no two of which may be realized at the same time.

1. The input and output voltage ratings may be exceeded even if the input and output clamp-current

ratings are observed.

2. The maximum package power dissipation was calculated using a junction temperature of 150°C.

Recommended Operating Conditions

Item Symbol Min Max Unit Conditions

Supply voltage range VCC 4.0 5.5 V

Input voltage range VI 0 5.5 V

Output voltage range VI/O 0 5.5 V

Input transition rise or fall rate ∆t / ∆v 0 5 ns / V VCC = 4.5 to 5.5 V

Operating free-air temperature Ta −40 85 °C

Note: Unused or floating inputs must be held high or low.

HD74CBT3253

Rev.1, May 2001, page 4 of 4

Block Diagram

1B1

1B2

1B3

1B4

2B1

2B2

2B3

2B4

2A 9

1A 7

1OE

2OE

HD74CBT3253

Rev.1, May 2001, page 5 of 5

DC Electrical Characteristics

(Ta = −40 to 85°C)

Item Symbol VCC (V) Min Typ *1 Max Unit Test conditions

Clamp diode voltage VIK 4.5   −1.2 V IIN = −18 mA

Input voltage VIH 4.0 to 5.5 2.0   V

IL 4.0 to 5.5   0.8

On-state switch

resistance *2

RON 4.5  5 7 Ω V

IN = 0 V,

IIN = 64 mA

4.5  5 7 VIN = 0 V,

IIN = 30 mA

4.5  10 15 VIN = 2.4 V,

IIN = 15 mA

Input current IIN 0 to 5.5   ±1.0 µA VIN = 5.5 V or GND

Off-state leakage

current

IOZ 5.5   ±1.0 µA 0 ≤ A, B ≤ VCC

Quiescent supply

current

ICC 5.5   3 µA VIN = VCC or GND,

IO = 0 mA

Increase in ICC

per input *3

∆ICC 5.5   2.5 mA One input at 3.4 V,

other inputs at VCC or

GND

Notes: For condition shown as Min or Max use the appropriate values under recommended operating

conditions.

1. All typical values are at VCC = 5 V (unless otherwise noted), Ta = 25°C.

2. Measured by the voltage drop between the A and B terminals at the indicated current through the

switch. On-state resistance is determined by the lower voltage of the two (A or B) terminals.

3. This is the increase in supply current for each input that is at the specified TTL voltage level

rather than VCC or GND.

Capacitance

(Ta = 25°C)

Item Symbol VCC (V) Min Typ Max Unit Test conditions

Control input

capacitance

CIN 5.0  3.5  pF VIN = 0 or 3 V

Input / output A port CI/O (OFF) 5.0  15  pF VO = 0 or 3 V

capacitance B port 5.0  5  OE = VCC

Note: This parameter is determined by device characterization is not production tested.

HD74CBT3253

Rev.1, May 2001, page 6 of 6

Switching Characteristics

(Ta = −40 to 85°C)

• VCC = 4.0 V

Item

Symbol

Min

Max

Unit

Test

conditions

FROM

(Input)

(Output)

Propagation delay

time *1

tPLH

tPHL

 0.35 ns CL = 50 pF

RL = 500 Ω

A or B B or A

Propagation delay

time

tPLH

tPHL

 6.6 ns CL = 50 pF

RL = 500 Ω

S A

Enable time tZH

tZL

 7.1 ns CL = 50 pF

RL = 500 Ω

S B

 7.3 OE A or B

Disable time tHZ

tLZ

 7.9 ns CL = 50 pF

RL = 500 Ω

S B

 7.3 OE A or B

• VCC = 5.0±0.5 V

Item

Symbol

Min

Max

Unit

Test

conditions

FROM

(Input)

(Output)

Propagation delay

time *1

tPLH

tPHL

 0.25 ns CL = 50 pF

RL = 500 Ω

A or B B or A

Propagation delay

time

tPLH

tPHL

1.6 6.2 ns CL = 50 pF

RL = 500 Ω

S A

Enable time tZH

tZL

1.3 6.3 ns CL = 50 pF

RL = 500 Ω

S B

1.4 6.4 OE A or B

Disable time tHZ

tLZ

1.1 7.4 ns CL = 50 pF

RL = 500 Ω

S B

2.3 7.0 OE A or B

Note: 1. The propagation delay is the calculated RC time constant of the typical on-state resistance of the

switch and the specified load capacitance, when driven by an ideal voltage source (zero output

impedance).

HD74CBT3253

Rev.1, May 2001, page 7 of 7

Test Circuit

OPEN

CL = 50 pF

500 Ω

Load circuit for outputs

Symbol

t / t

PLH PHL

t / t

ZH HZ

t / t

ZL LZ

OPEN

7 V

500 Ω

See under table

GND

Note: 1. CL includes probe and jig capacitance.

HD74CBT3253

Rev.1, May 2001, page 8 of 8

Waveforms – 1

Input

10 %

1.5 V 1.5 V

90 %

90 % 3 V

GND

10 %

Output 1.5 V 1.5 V

tPLH

tPHL

VOL

Waveforms – 2

Waveform - B

Notes: 1. All input pulses are supplied by generators having the following characteristics :

PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.

2. Waveform - A is for an output with internal conditions such that the output is low except

when disabled by the output control.

3. Waveform - B is for an output with internal conditions such that the output is high except

when disabled by the output control.

4. The output are measured one at a time with one transition per measurement.

Waveform - A

VOH

VOL

V + 0.3 V

V - 0.3 V

Output

Control 10 % 10 %

1.5 V 1.5 V

90 %

90 % 3 V

3.5 V

GND

1.5 V

tHZ

tLZ

tZH

tZL

HD74CBT3253

Rev.1, May 2001, page 9 of 9

Package Dimensions

Hitachi Code

JEDEC

EIAJ

Mass

(reference value)

TTP-16DA



0.05 g

*Dimension including the plating thickness

Base material dimension

0.50 ± 0.10

0° − 8°

*0.17 ± 0.05

6.40 ± 0.20

0.10

1.10 Max

0.13 M

0.65

16 9

4.40

5.00

5.30 Max

0.07+0.03

−0.04

0.65 Max

1.0

0.20 ± 0.06

+ 0.08

− 0.07

*0.22

0.15 ± 0.04

As of January, 2001

Unit: mm

HD74CBT3253

Rev.1, May 2001, page 10 of 10

Disclaimer

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,

Hitachi bears no responsibility for problems that may arise with third party’s rights, including

intellectual property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have

received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,

contact Hitachi’s sales office before using the product in an application that demands especially high

quality and reliability or where its failure or malfunction may directly threaten human life or cause risk

of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,

traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly

for maximum rating, operating supply voltage range, heat radiation characteristics, installation

conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used

beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable

failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-

safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other

consequential damage due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without

written approval from Hitachi.

7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor

products.

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