KAI-0373 768 (H) x 484 (V) Interline CCD Image Sensor Description The KAI-0373 is a high-performance silicon charge-coupled device (CCD) designed for video image sensing and electronic still photography. The device is built using an advanced true two-phase, double-polysilicon, NMOS CCD technology. The p+npn- photodetector elements eliminate image lag and reduce image smear while providing anti-blooming protection and electronic-exposure control. The total chip size is 9.9 (H) mm x 7.7 (V) mm. The KAI-0373 comes in monochrome versions, with an option with microlens for sensitivity improvement. www.onsemi.com Table 1. GENERAL SPECIFICATIONS Parameter Typical Value Architecture Interline Transfer CDD; Progressive Scan Number of Active Pixels 768 (H) x 484 (V) Number of Outputs 1 Pixel Size 11.6 mm(H) x 13.6 mm (V) Active Image Size 8.91 mm (H) x 6.58 mm (V), 11.1 mm (Diagonal), 2/3 Optical Format Aspect Ratio 3:2 Output Sensitivity 9 mV/e- Photometric Sensitivity KAI-0373-ABA 2.2 V/lux-sec Charge Capacity 55 ke- Maximum Pixel Clock Speed 14.32 MHz Maximum Frame Rate 30 fps Package Type CerDIP Package Size 0.800 [20.32 mm] Width 1.200 [30.48 mm] Length Package Pins 24 Package Pin Spacing 0.100 (2.54 mm) Figure 1. KAI-0373 Interline CCD Image Sensor Features * * * * * * * High Resolution High Sensitivity High Dynamic Range Low Noise Architecture High Frame Rate Binning Capability for Higher Frame Rate Electronic Shutter Application * Intelligent Traffic Systems * Surveillance ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. NOTE: All Parameters are specified at T = 40C unless otherwise noted. (c) Semiconductor Components Industries, LLC, 2015 March, 2015 - Rev. 4 1 Publication Order Number: KAI-0373/D KAI-0373 ORDERING INFORMATION Table 2. ORDERING INFORMATION Part Number Description KAI-0373-AAA-CP-BA Monochrome, No Microlens, CERDIP Package (Sidebrazed), Taped Clear Cover Glass (No Coatings), Standard Grade KAI-0373-ABA-CB-AE Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed), Sealed Clear Cover Glass (No Coatings), Engineering Grade KAI-0373-ABA-CB-BA Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed), Sealed Clear Cover Glass (No Coatings), Standard Grade KAI-0373-ABA-CP-BA Monochrome, Telecentric Microlens, CERDIP Package (Sidebrazed), Taped Clear Cover Glass (No Coatings), Standard Grade Marking Code KAI-0373-AAA Serial Number KAI-0373-ABA Serial Number See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com. www.onsemi.com 2 KAI-0373 DEVICE DESCRIPTION Architecture fV2B fV1B fV1B fV2A fV2A fV1A fV1A KAI-0373 Usable Active Image Area 768 (H) x 484 (V) 11.6 mm x 13.6 mm Pixels 12 Dark Columns fV2B LTSH VRD fR VLG VDD VOUT VSS CCC CCC 5 Dark Rows 768 Active Pixels/Line 8 768 12 CC II II CC 2 fH1 fH2 = 791 Pixels/Line WELL SUBS OG Figure 2. Block Diagram Charge Transport The KAI-0373 consists of 371, 712 photodiodes, 768 vertical (parallel) CCD shift registers (VCCDs), one horizontal (serial) CCD shift register and one output amplifier. The advanced, progressive-scan architecture of the device allows the entire image area to be read out in a single scan. The pixels are arranged in a 768 (H) x 484 (V) array in which an additional 12 columns and 5 rows of light shielded pixels are added as dark reference. The accumulated or integrated charge from each photodiode is transported to the output by a three step process. The charge is first transported from the photodiodes to the VCCDs by applying a large positive voltage to the phase-one vertical clock (fV2). This reads out every row, or line, of photodiodes into the VCCDs. The charge is then transported from the VCCDs to the HCCDs line by line. Finally, the HCCDs transport these rows of charge packets to the output structures pixel by pixel. On each falling edge of the horizontal clock, fH2, these charge packets are dumped over the output gate (OG, Figure 3) onto the floating diffusion (FD Figure 3). Both the horizontal and vertical shift registers use traditional two-phase complementary clocking for charge transport. Transfer to the horizontal CDD begins when fV2 is brought low (and fV1 high) causing a line of charge to transfer from fV2 to fV1 and subsequently into the horizontal register. The sequence completes when fV1 is brought low before the horizontal CCD reads the first line of charge. Image Acquisition An electronic representation of an image is formed when incident photons falling on the sensor plane create electron-hole pairs within the individual silicon photodiodes. These photoelectrons are collected locally by the formation of potential wells at each photosite. Below photodiode saturation, the number of photoelectrons collected at each pixel is linearly dependent on light level and exposure time and non-linearly dependent on wavelength. When the photodiode's charge capacity is reached, excess electrons are discharged into the substrate to prevent blooming. www.onsemi.com 3 KAI-0373 Output Structure voltage off chip with slightly less than unity gain. The translation from the charge domain to the voltage domain is quantified by the output sensitivity or charge to voltage conversion in terms of mV/e-. After the signal has been sampled off-chip, the reset clock (fR) removes the charge from the floating diffusion and resets its potential to the reset-drain voltage (VRD). Charge packets contained in the horizontal register are dumped pixel by pixel, onto the floating diffusion output node whose potential varies linearly with the quantity of charge in each packet. The amount of potential change is determined by the expression DVFD = DQ / CFD. A three stage source-follower amplifier is used to buffer this signal VDD fR FD VRD SUB VOUT WELL VLG VSS FD = Floating Diffusion Figure 3. Output Structure Electronic Shutter Application of the large shutter pulse must be avoided during the horizontal register readout or an image artifact will appear due to feedthrough. The shutter pulse VES must be "hidden" in the horizontal retrace interval. The integration time is changed by skipping the shutter pulse from one horizontal retrace interval to another. The smear specification is not met under electronic shutter operation. Under constant light intensity and spot size, if the electronic exposure time is decreased, the smear signal will remain the same while the image signal will decrease linearly with exposure. Smear is quoted as a percentage of the image signal and so the percent smear will increase by the same factor that the integration time has decreased. This effect is basic to interline devices. Extremely bright light can potentially harm solid state imagers such as Charge-Coupled Devices (CCDs). Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions. The KAI-0373 provides a structure for the prevention of blooming which may be used to realize a variable exposure time as well as performing the anti-blooming function. The anti-blooming function limits the charge capacity of the photodiode by draining excess electrons vertically into the substrate (hence the name Vertical Overflow Drain or VOD). This function is controlled by applying a large potential to the device substrate (device terminal SUB). If a sufficiently large voltage pulse (VES 40 V) is applied to the substrate, all photodiodes will be emptied of charge through the substrate, beginning the integration period. After returning the substrate voltage to the nominal value, charge can accumulate in the diodes and the charge packet is subsequently readout onto the VCCD at the next occurrence of the high level on fV2. The integration time is then the time between the falling edges of the substrate shutter pulse and fV2. This scheme allows electronic variation of the exposure time by a variation in the clock timing while maintaining a standard video frame rate. www.onsemi.com 4 KAI-0373 negative that fH1 and fH2 during sensor operation and during camera power turn on. This sensor, like most other MOS-based image sensors, is extremely sensitive to electrostatic discharge (ESD) damage. The handling and environment of the sensor must be controlled to protect this device from ESD damage. On-Chip Gate Protection Gates OG, fR, VLG, VSS, fH1 and fH2 are internally connected to transistors as shown in Figure 4 to provide active ESD protection. For the protection to work, pin 11 (Horizontal ESD well) and pin 13 (Vertical ESD well) must be biased to -10 V. The ESD bias must be at least 1 V more PIN CONNECTION GATE Snap-Back Field FET Horizontal ESD Well Figure 4. Internal Protection Circuit for fH1 and fH2 www.onsemi.com 5 KAI-0373 Physical Description Pin Description and Device Orientation OG 1 24 fV2A fR 2 23 fV1A VRD 3 22 fV2B 21 fV1B Pixel 1, 1 VSS 4 VLG 5 20 WELL VOUT 6 VDD 19 SUB 7 18 LTSH WELL 8 17 fV1A fH2 9 16 fV2A fH1 10 15 fV1B ESD 11 14 fV2B NC 12 13 ESD Pin 1 Locator Side View of Package 1 2 3 4 5 Figure 5. Pin Description Table 3. PIN DESCRIPTION Pin Name Description Pin Name ESD Horizontal ESD Well Description 1 OG Output Gate 13 2 fR Reset Clock 14 fV2B Vertical CCD Clock - Phase 2 fV1B Vertical CCD Clock - Phase 1 3 VRD Reset Drain 15 4 VSS Output Amplifier Return 16 fV2A Vertical CCD Clock - Phase 2 Output Amplifier Load Gate 17 fV1A Vertical CCD Clock - Phase 1 Video Output 18 LTSH Lightshield Output Amplifier Supply 19 SUB Substrate 5 VLG 6 VOUT 7 VDD 8 WELL Ground 20 WELL Ground 9 fH2 Horizontal CCD Clock - Phase 2 21 fV1B Vertical CCD Clock - Phase 1 10 fH1 Horizontal CCD Clock - Phase 1 22 fV2B Vertical CCD Clock - Phase 2 11 ESD Horizontal ESD Well 23 fV1A Vertical CCD Clock - Phase 1 12 NC No Connect 24 fV2A Vertical CCD Clock - Phase 2 1. The pins are on a 0.100 spacing. 2. Pins 14, 16, 22, and 24 must be connected together - only one Phase 2 clock driver is required. 3. Pins 15, 17, 21, and 23 must be connected together - only one Phase 1 clock driver is required. www.onsemi.com 6 KAI-0373 IMAGING PERFORMANCE All following values were derived for the KAI-0373-ABA series devices (with microlens array) using nominal operating conditions and the recommended timing. Unless otherwise stated, readout time = 33 ms, integration time = 33 ms, no electronic shutter pulse is applied, and sensor temperature = 40C. Correlated double sampling of the output is assumed and recommended. Defects are excluded from the following tests and the signal output is referenced to the dark pixels at the end of each line unless otherwise specified. Specifications Table 4. CCD Description Symbol Min. Nom. Max. Unit Ne-SAT 55 - - ke- Output Saturation Signal VSAT 500 - - mV Photodiode Dark Current ID - - 0.5 nA Charge Transfer Efficiency CTE - 0.99999 - Horizontal CCD Frequency fH - 14.3 - Image Lag IL - Negligible - Blooming Margin XAB - 300 - Smear Smr - 0.01 0.04 Saturation Signal - VCCD Notes 1, 2, 6 2, 3 MHz 4, 6 % 5 1. VSAT is the mean value at saturation as measured at the output of the device with XAB = 300. This value is guaranteed only when VSUB = VAB as indicated on the sensor package. VSAT can be varied by adjusting VSUB. 2. Measured at the sensor output. 3. With stray load capacitance of CL = 10pF between the output and AC ground. 4. XAB represents the increase above the saturation-irradiance level (HSAT) that the device can be exposed to before blooming of the vertical shift register will occur. It should be noted that VOUT rises above VSAT for irradiance levels above HSAT. 5. Measured under 10% (~48 lines) image height illumination with white light source and without electronic shutter operation and below VSAT. 6. It should be noted that there is a tradeoff between XAB and VSAT. Table 5. OUTPUT AMPLIFIER @ VDD = 15 V, VSS = 0.5 V Description Symbol Min. Nom. Max. Unit Output DC Offset VODC 5 6.3 7.5 V Power Dissipation PD - 75 - mW f-3db 100 - - MHz Output Amplifier Bandwidth Sensitivity (Output Referred) Off-Chip Load DVO/DN - 9 - mV/e- CL - - 10 pF Notes 1 1. With stray output load capacitance of CL = 10 pF between output and AC ground. Table 6. GENERAL Description Total Sensor Noise Dynamic Range Symbol Min. Nom. Max. Unit Notes Ne-TOTAL - 55 - e- rms 1 DR - 60 - dB 2 1. Includes amplifier noise, dark pattern noise and dark current shot noise at data rates of 14 MHz. 2. Uses 20 Log (Ne-SAT / Ne-TOTAL) where Ne-SAT refers to the vertical CCD saturation signal. www.onsemi.com 7 KAI-0373 Table 7. ELECTRO-OPTICAL FOR KAI-0373-ABA MONOCHROME WITH MICROLENS Description Symbol Min. Nom. Max. Unit Notes ESAT - 0.044 - mJ/cm2 1 QE - 35 - % 2 Photoresponse Non-Uniformity PRNU - - 2 % rms 3 Photoresponse Non-Linearity PRNL - - 2 % RS - - 10 % Saturation Exposure Peak Quantum Efficiency Photoresponse Shading 4 1. For l = 530 nm wavelength, and NSAT = 55 ke-. 2. Refer to typical values from Figure 8. 3. For a 100 x 100 pixel region under uniform illumination with output signal equal to 80% of saturation signal. Saturation signal, VSAT, is the output voltage at the knee of the output vs illumination curve as shown in Figure 6. 4. This is the global variation in chip output across the entire chip measured at 80% saturation and is expressed as a percentage of the mean pixel value. Saturation signal, VSAT, is the output voltage at the knee of the output vs illumination curve as shown in Figure 6. 800 700 (HSAT, VSAT) Output Signal - VOUT - (mV) 600 500 400 300 200 100 0 0 0.1 0.2 0.3 0.4 0.5 0.6 Sensor Plane Irradiance - H - (arb) Figure 6. Typical KAI-0373 Photoresponse www.onsemi.com 8 0.7 0.8 KAI-0373 Defect Definitions All values are derived under normal operating conditions at 40C operating temperature. Table 8. DEFECT DEFINITIONS Defect Type Defect Definition Number Allowed Notes Defective Pixel Under uniform illumination with mean pixel output of 400 mV, a defective pixel deviates by more than 15% from the mean value of all active pixels in its section. 5 1, 2 Bright Defect Under dark field conditions, a bright defect deviates more than 15 mV from the mean value of all pixels in its section. 0 1, 2 Cluster Defect Two or more vertically or horizontally adjacent defective pixels. 0 2 1. Sections are 256 (H) x 242 (V) pixel groups, which divide the imager into six equal areas as shown below. 2. Test conditions: Junction Temperature = 40C, Integration Time = 33 ms and Readout Time = 33 ms. (1,484) (768,484) (1,1) (768,1) Figure 7. www.onsemi.com 9 KAI-0373 TYPICAL PERFORMANCE CURVES 40% 35% Quantum Efficiency (%) 30% 25% 20% 15% 10% 5% 0% 400 450 500 550 600 650 700 750 800 850 900 950 1000 Wavelength (nm) Figure 8. Monochrome with Microlens Quantum Efficiency 14.0 12.0 Quantum Efficiency (%) 10.0 8.0 6.0 4.0 2.0 0.0 300 350 400 450 500 550 600 650 700 750 800 850 900 950 Wavelength (nm) Figure 9. Monochrome, No Microlens, No Cover Glass Quantum Efficiency www.onsemi.com 10 1000 1050 KAI-0373 OPERATION Absolute Maximum Ratings Absolute maximum rating is defined as a level or condition that should not be exceeded at any time per the description. If the level or the condition is exceeded, the device will be degraded and may be damaged. Table 9. ABSOLUTE MAXIMUM RATINGS Rating Description Temperature (@ 10% 5% RH) Voltage (Between Pins) Min. Max. Unit Notes Operation to Specification 25 40 C Operation Without Damage -25 55 C Storage -25 70 C SUB-WELL 0 50 V 1, 3 VRD, VDD, and VSS-WELL 0 25 V 2 All Clocks - WELL - 17 V 2 fV1 - fV2 - 17 V 2 fH1 - fH2 - 17 V 2 fH1, fH2 - fV2 - 17 V 2 fH2 - OG - 17 V 2 All Clocks - LTSH - 17 V 2 VLG, OG - WELL - 17 V 2 2 All Gates - LTSH - 17 V Current Output Bias Current (IDD) - 10 mA Capacitance Output Load Capacitance (CLOAD) - 10 pF Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Under normal operating conditions the substrate voltage should be above +7 V, but may be pulsed to 40 V for electronic shuttering. 2. Care must be taken in handling so as not to create static discharge which may permanently damage the device. 3. Refer to Application Note Using Interline CCD Image Sensors s in High Intensity Visible Lighting Conditions. DC Bias Operating Conditions Table 10. DC BIAS OPERATING CONDITIONS Description Symbol Min. Nom. Max. Unit Output Gate OG 1.5 2 2.5 V Reset Drain VRD 10 10.5 11 V Output Amplifier Return VSS 0.4 0.5 0.6 V Output Amplifier Load Gate VLG 1.7 2 2.5 V Output Amplifier Supply Notes VDD 14.5 15 15.5 V Well WELL - 0 - V Lightshield LTSH - 0 - V Substrate SUB 7 VAB 25 V 1, 4 Output Bias Current IOUT 3 5 7 mA 2 ESD Bias ESD - -10 - V 3 1. The operating value of the substrate voltage, VAB, will be marked on the shipping container for each device. The substrate is clocked in electronic shutter mode operation. A shutter pulse with voltage less than 50 V for less than 100 ms is allowed. See AC Clock Level Conditions and AC Timing Requirements. Well and substrate biases should be established before other gate and diode potentials are applied. 2. A 1.8 kW resistor between VOUT and ground is recommended to obtain IOUT = 5 mA. VOUT must not be shorted to ground. 3. Pins 11 and 13 are biased to -10 V. The ESD bias must be at least 1 V more negative than fH1 and fH2 during sensor operation AND during camera power turn on. 4. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions. www.onsemi.com 11 KAI-0373 AC Operating Conditions Table 11. CLOCK LEVELS Symbol Min. Nom. Max. Unit Notes Vertical CCD Clocks - High Description fV1H, fV2H 14.5 14.7 15 V 1 Vertical CCD Clocks - Mid fV1M, fV2M -0.5 -0.2 0 V 1 Vertical CCD Clocks - Low fV1L, fV2L -9 -8 -7 V 1 Horizontal CCD Clocks - High fH1H, fH2H 1 2 3 V 1 Horizontal CCD Clocks - Low fH1L, fH2L -10 -9 -8 V 1 Reset Clock - High fRH 7 8 9 V Reset Clock - Low fRL 2 3 4 V VES (SUB) 40 42 45 V For Electronic Shutter Pulse Only 2, 3 1. For best results, the CCD clock swings must be maintained at (or greater than) the values indicted by the nominal level conditions noted above. 2. This pulse, used only for electronic shutter mode operation, is applied to the substrate, as described in the Electronic Shutter section of this document. Dynamic resistance is 3 kW and typical DC current is 3 mA at VSUB = 40 V. 3. Refer to Application Note Using Interline CCD Image Sensors in High Intensity Visible Lighting Conditions. Clock Line Capacitances Table 12. CLOCK LINE CAPACITANCES Description Symbol Typical Unit Vertical CCD Clocks - Well C fV1, fV2 (A, B combined) 10 nF VCCD Clock Phase 1 - VCCD Clock Phase 2 C fV1 - fV2 (A, B combined) 1.5 nF Horizontal CCD Clocks - Well C fH1, fH2 150 pF HCCD Clock Phase 1 - HCCD Clock Phase 2 C fH1 - fH2 60 pF C fR 5 pF C SUB 400 pF Reset Clock - Well For Electronic Shutter Pulse www.onsemi.com 12 KAI-0373 TIMING Table 13. REQUIREMENTS AND CHARACTERISTICS Description Symbol Min. Nom. Max. Unit Vertical High Level Duration tfVH Vertical Transfer Time tfV 5 17 20 ms - 2.8 - ms Vertical Pedestal Delay tfVPD 10 - - ms Horizontal Delay tfHD 5.3 - - ms Reset Duration tfR 15 20 25 ns Horizontal Clock Frequency ffH - - 14.32 MHz Notes 1 tL - 63.5 - ms tfVD 200 - - ns tfHVES 1 - - ms Clamp Delay tCD - - - ns 2 Sample Delay tSD - - - ns 2 Electronic Shutter Pulse Duration tES 4 5 - ms 3 Line Time Vertical Delay Horizontal Delay with Electronic Shutter 1. The rising edge of fR should be coincident with the rising edge of fH2, within 5 ns. 2. The clamp delay and sample delay should be adjusted for optimum results. 3. This pulse is used only with electronic shuttering and should not be used during horizontal readout. The electronic shutter pulse should be hidden in the horizontal retrace interval. Frame Timing 525 fV1 (A&B) fV2 (A&B) Integration Time = tINT VES (SUB) (Electronic Shutter Mode Only) tL fV1 (A&B) tfVPD tfVPD 1 Line Time = tL = 63.5 ms tfVH Vertical Overclocking NOTE: When no electronic shutter is used, the integration time is equal to the frame time. Figure 10. Frame Timing www.onsemi.com 13 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 525 524 523 fV2 (A&B) KAI-0373 Line Timing 1 Line= 791 Pixels tL = 63.5 ms tfV fV1 fV2 tfHD tfVD fH1 fH2 55.31 ms fR Line Content Empty Shift Register Phases Dark Reference Pixels Figure 11. Line Timing www.onsemi.com 14 789 790 791 777 778 9 10 1 fH1/fH2 Count Photoactive Pixels KAI-0373 Pixel Timing 1 Count = 1 Pixel 69.8 ns fH1 fH2 fR tfR Reference Signal VOUT CLAMP tCD SAMPLE Signal tSD Video after Correlated Double Sampling (Inverted) Reference Figure 12. Pixel Timing Electronic Shutter Timing tfVH tfV fV2 tfHD tfVD fH1 tfHVES VES (SUB) tES tINT Figure 13. Electronic Shutter Timing www.onsemi.com 15 KAI-0373 CCD Clock Waveform Conditions Table 14. CCD CLOCK WAVEFORM CONDITIONS Symbol tWH tWL tR tF Unit Note Vertical CCD Clocks - Phase 1 Description fV1M 2.8 59.8 0.6 0.3 ms 1 Vertical CCD Clocks - Phase 2 fV2M 60 2.5 0.5 0.5 ms 1 Vertical CCD Clocks - Phase 2, High fV2H 17 - 0.5 0.5 ms 1 Horizontal CCD Clocks - Phase 1 fH1 25 27 8.5 8.5 ns 1 Horizontal CCD Clocks - Phase 2 fH2 25 27 8.5 8.5 ns 1 fR 20 40 4 5 ns 1 VES (SUB) 5 - 0.2 0.2 ms 1 Reset Clock For Electronic Shutter Pulse Only 1. Typical values measured with clocks connected to image sensor device. tR tWH tF High 100% 90% tWL 10% Low 0% Figure 14. CCD Clock Waveform www.onsemi.com 16 KAI-0373 STORAGE AND HANDLING Table 15. STORAGE CONDITIONS Item Description Min. Max. Unit Conditions Notes Temperature 25 40 C @ 10% 5% RH 1, 2 Humidity 105 865 % RH @ 362C Temp. 1, 2 Operation without Damage Temperature -25 55 C @ 10% 5% RH 2, 3 Storage Temperature -25 70 C @ 10% 5% RH 2, 4 Humidity - 905 % RH @ 492C Temp. 2, 4 Operation to Specification 1. The image sensor shall meet the specifications of this document while operating at these conditions. 2. The tolerance on all relative humidity values is provided due to limitations in measurement instrument accuracy. 3. The image sensor shall continue to function but not necessarily meet the specifications of this document while operating at the specified conditions. 4. The image sensor shall meet the specifications of this document after storage for 15 days at the specified conditions. For information on ESD and cover glass care and cleanliness, please download the Image Sensor Handling and Best Practices Application Note (AN52561/D) from www.onsemi.com. For quality and reliability information, please download the Quality & Reliability Handbook (HBD851/D) from www.onsemi.com. For information on device numbering and ordering codes, please download the Device Nomenclature technical note (TND310/D) from www.onsemi.com. For information on environmental exposure, please download the Using Interline CCD Image Sensors in High Intensity Lighting Conditions Application Note (AND9183/D) from www.onsemi.com. For information on Standard terms and Conditions of Sale, please download Terms and Conditions from www.onsemi.com. For information on soldering recommendations, please download the Soldering and Mounting Techniques Reference Manual (SOLDERRM/D) from www.onsemi.com. www.onsemi.com 17 KAI-0373 MECHANICAL INFORMATION Completed Assembly Notes: 1. See Ordering Information for Marking Code. 2. Cover Glass is manually placed and visually aligned over die - location accuracy is not guaranteed. 3. Units: Inches [mm]. Figure 15. Completed Assembly www.onsemi.com 18 KAI-0373 Die to Package Alignment Figure 16. Die to Package Alignment www.onsemi.com 19 KAI-0373 Glass 4X C 0.020 EPOXY 8X C 0.008 Notes: 1. Dust/Scratch Count: 10 microns max 2. Epoxy Thickness: 0.002 - 0.005 3. Glass: Schott D-263T eco or equivalent 4. Units: Inches Figure 17. Glass Drawing www.onsemi.com 20 KAI-0373 Glass Transmission 100 90 80 Transmission (%) 70 60 50 40 30 20 10 0 200 300 400 500 600 700 800 900 Wavelength (nm) Figure 18. Glass Transmission ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5817-1050 www.onsemi.com 21 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative KAI-0373/D Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: ON Semiconductor: KAI-0373-AAA-CP-BA KAI-0373-ABA-CP-BA KAI-0373-ABA-CB-BA KAI-0373-EBA-CB-BA