LMX2531LQ3010E
Evaluation Board Operating Instructions
National Semiconductor Corporation
Timing Devices Business Group
10333 North Meridian
Suite 400
Indianapolis, IN 46290
LMX25313010EVAL Instructions Rev 6.24.2009
LMX2531LQ3010E EVALUATION BOARD OPERATING INSTRUCTIONS
Table of Contents
Table of Contents ................................................................................................................ 2
Loop Filter .......................................................................................................................... 3
Quick Setup ......................................................................................................................... 3
Troubleshooting .................................................................................................................. 4
SOFTWARE DOES NOT COMMUNICATE WITH THE EVALUATION BOARDS ....................................................... 4
PART RESPONDS TO PROGRAMMING, BUT DOES NOT LOCK TO THE CORRECT FREQUENCY ............................ 4
CLOSE-IN PHASE NOISE IS WORSE THAN EVALUATION BOARD INSTRUCTIONS SHOW .................................... 4
FAR-OUT PHASE NOISE IS WORSE THAN EVALUATION BOARD INSTRUCTIONS SHOW .................................... 5
Device Data ......................................................................................................................... 5
PHASE NOISE ............................................................................................................................................... 6
FREE-RUNNING VCO PHASE NOISE (INTERNAL DIVIDE BY 2 DISABLED) .................................................... 7
FREE-RUNNING VCO PHASE NOISE (INTERNAL DIVIDE BY 2 ENABLED) ..................................................... 8
FRACTIONAL SPURS (INTERNAL DIVIDE BY 2 DISABLED) ............................................................................ 9
FRACTIONAL SPURS (INTERNAL DIVIDE BY 2 ENABLED) ........................................................................... 10
INTEGER SPURS (INTERNAL DIVIDE BY 2 DISABLED) ................................................................................. 11
INTEGER SPURS (INTERNAL DIVIDE BY 2 ENABLED) .................................................................................. 12
IN-BAND FACTIONAL SPURS INTEGER SPURS (INTERNAL DIVIDE BY 2 DISABLED) .................................... 13
IN-BAND FACTIONAL SPURS INTEGER SPURS (INTERNAL DIVIDE BY 2 ENABLED) ..................................... 14
Inter-modulation Spurs ............................................................................................. 15
CodeLoader Settings ......................................................................................................... 16
SELECT DEVICE .......................................................................................................................................... 16
BITS/PINS ................................................................................................................................................... 18
PLL/VCO .................................................................................................................................................. 19
REGISTERS ................................................................................................................................................. 20
PORT SETUP ............................................................................................................................................... 21
Schematic .......................................................................................................................... 22
Bill of Materials ................................................................................................................ 23
Top Layer .......................................................................................................................... 24
Mid Layer 1 "Ground Plane" ............................................................................................ 25
Mid Layer 2 "Power" ........................................................................................................ 26
Bottom Layer "Signal" ...................................................................................................... 27
Top Build Diagram ........................................................................................................... 28
2
LMX2531LQ3010E EVALUATION BOARD OPERATING INSTRUCTIONS
Loop Filter
Loop Band width 13.8 kHz Kφ 1440 uA (16X)
Phase Margin 54.5 ° FPD 10 MHz
Crystal Frequency 10 MHz Output Frequency 2910 to 3132 MHz (DIV2=0)
1455 to 1566 MHz (DIV2=1)
Supply Voltage 3.0 Volts VCO Gain 13 to 29 MHz/Volt
VCO
CPout
open
100 nF
1KΩ
100 pF 100 pF
20 KΩ20 KΩ
Vtune
Quick Setup
• Install the CodeLoad er software which is available at www.national.com/timing/software/.
• Attach the parallel cable or USB <--> uWire cable to the computer and the evaluation board.
• Connect 3.0 volts t o the Vcc connector.
• Connect the Fout connector to a spectrum analy zer or pha se noise analyzer.
• Connect a cl ean 10 MHz source to the OSCin pi n. Typically, the 10 MHz out put from the back
of the RF test equipment is a good sou rce. Signal generators te nd to be very noisy and should
be used with caution. If a signal generator is used, the signal generator phase noise
contribution can be reduced by setting the signal to 80 MHz and dividing this down to a phase
detector frequency of 10 MHz.
• Set up the CodeLoa der softwa re.
o Select the proper part from t he menu as Sele ct Part->PLL+V CO->LMX2531LQ3 010E
o Select the proper mode f rom the Mode menu.
o Load the part by pressing Ctrl+L or selecting Keyboard Controls->Load Device from
the menu.
• It is recommended to en sure proper communicatio n with the device.
o Click the REG _RST bit on the bit s/pins page and o bserve the current go to 0 mA.
o Unclick the REG_ RST bit AND press Ctrl +L. The curre nt should be approximately
35 mA.
o If device does not respon d to this, consult t he troubleshooting secti on.
3
LMX2531LQ3010E EVALUATION BOARD OPERATING INSTRUCTIONS
Troubleshooting
Sof tware does not communicate with the evaluation boards
LPT or USB Mode
• Ensure a valid signal is presented to the OSCin connector. If a signal generator is used,
ensure the RF is ON.
• Consult the CodeLoad er instruction s for more detailed i nformation o n communication issu es.
LPT Mode (Uses Par allel Port Cable)
• Ensure that CodeLoader i s selected to LPT mode on the Port Setup tab
• Ensure the proper port number is selected (LPT1, LPT2, LPT3). CodeLoader does NOT
automatically detect this.
• Ensure the LPT cable is securely connected to the com puter and boa rd.
• Exit and Restart CodeLoad er.
• Ensure the parallel port is in the correct mode.
o Windows ofte n requires Administrative ac cess to write to the parallel po rt.
o Ensure that the parallel port is set to “Enabled” in windows device manager.
o A reboot upon installation of CodeLoader is sometimes necessary to get the parallel
port to work.
o Standard mode is the most reliable. This can be set in the BIOS mode of the
computer as “Normal”, “Out put Only”, or “AT.”
USB Mode (Uses USB <--> uWir e Interface Board, NS ID = USB2UWIRE)
• On the menu, sele ct LPT/USB->Version to verify communication with the board.
• Ensure the Green LE Ds are lit on the USB boa rd.
• Ensure there are no conflicts with other USB devices an d reinstall the boa rd.
Part responds to programming, but does not lock to the correct
frequency
• Ensure that there is a valid signal presented to the OSCin connector. If a signal gen erator is
used, ensure that the RF is set to O N.
• If using the lower frequency band (DIV2=1), the VCO frequency in CodeLoader should be
twice the frequency at the Fo ut pin.
• Ensure that the VCO FREQUENCY CAL bi ts on the Bits/Pins tab are correct.
• Ensure that the loop filter is optimi zed if th e charge pump curre nt, phase detecto r frequen cy, or
loop filter values have been changed from their original settings. Ensure that the integrated
loop filter components on CodeLoader are set to their proper settings.
Close-in phase noise is worse than evaluation board instructions
show
• Ensure the signal presented to OSCin connector is clean. Try another source, or if it is a
signal generator, try using a higher frequency and dividing it down to the phase detector
frequency.
• Ensure the OSCin si gnal after the con necting cable provides sufficient po wer level.
• If the phase detector frequency or charge pump current are lowered from their original settings,
the in-band phase noise can be degraded, even if the loop filter is re-designed for the same
loop bandwi dth.
• If the loop bandwidth i s decreased, in-band ph ase noise can be degraded
4
LMX2531LQ3010E EVALUATION BOARD OPERATING INSTRUCTIONS
Far-out Phase noise is worse than evaluation board instructions
show
• Ensure the measurement equipment noise floor is not limiting the measurement. For
spectrum analyzers, the noise floor at a particular setting can be measured by removing the
RF input signal
• If the settings are changed from what the board was designed for, ensure the delta-sigma
modulator is not increasing the far-out noise. To determine this, tune to an integer channel
and set the ORDER bit to “Reset Mod ula tor”. The far o ut phase noi se sh ould n ot decre ase. If
it does, try a loop filter with m ore attenuation or sele ct a lower ord er delta-sigma modu lator.
Device Data
The next few pages show data collected from the LMX2 531LQ3010 evaluati on board.
5
LMX2531LQ3010E EVALUATION BOARD OPERATING INSTRUCTIONS
Phase Noise
Output Frequency = 3010.25 MHz
Internal Divide by 2 Disabled (DIV2=0)
Output Frequency = 1505.125 MHz
Internal Divide by 2 Enabled (DIV2=1)
6
LMX2531LQ3010E EVALUATION BOARD OPERATING INSTRUCTIONS
Free-Running VCO Phase Noise (Internal Divide by 2 Disabled)
Fout = ~2910 MHz
The plots to the left show the true phase
noise capability of the VCO. In order to
take these plots, the E5052 phase nose
analyzer was used. The method was to
lock the PLL to the proper frequency, then
disable the EN_PLL, EN_PLLLDO1,
EN_PLLLDO2, EN_DIGLDO, and
EN_OSC bits. The eq uipme nt needs to be
able to track the VCO phase noise to
measure in this way, and one can not let
the VCO drift too far off in f requency. If this
kind of equipment is not available, the
VCO phase noise can also be measured
by making a very narrow loop bandwidth
filter.
Fout = ~3010 MHz
Fout = ~3130 MHz
7
LMX2531LQ3010E EVALUATION BOARD OPERATING INSTRUCTIONS
Free-Running VCO Phase Noise (Internal Divide by 2 Enabled)
Fout = ~1455 MHz (~2910 MHz/2)
The plots to the left show the true phase
noise capability of the VCO. In order to
take these plots, the E5052 phase nose
analyzer was used. The method was to
lock the PLL to the proper frequency, then
disable the EN_PLL, EN_PLLLDO1,
EN_PLLLDO2, EN_DIGLDO, and
EN_OSC bits. The eq uipme nt needs to be
able to track the VCO phase noise to
measure in this way, and one can not let
the VCO drift too far off in f requency. If this
kind of equipment is not available, the
VCO phase noise can also be measured
by making a very narrow loop bandwidth
filter.
When divide by 2 is enabled, the phase
noise at lower offsets is about 6 dB better;
but at high offsets, the phase noise
improvement may be less because the
divider is noise floor is adding to the phase
noise.
Fout = ~1505 MHz (~3010 MHz/2)
Fout = ~1565 MHz (~3130 MHz/2)
8
LMX2531LQ3010E EVALUATION BOARD OPERATING INSTRUCTIONS
Fractional S purs (Internal Divide by 2 Disab led)
The -58.9 dBc fractional spur at 250 kHz offset is
at a worst case frequ ency of 2910.25 MHz. The
-74.6 dBc sub-fractional spur at 125 kHz offset is
also visible.
Worst case channels occur at exactly one
channel spacing above or below a multiple of the
crystal frequency.
The -71.8 dBc fractional spur at 250 kHz offset is
at a worst case frequ ency of 3010.25 MHz. The
-74.9 dBc sub-fractional spur at 125 kHz offset is
also visible.
Worst case channels occur at exactly one
channel spacing above or below a multiple of the
crystal frequency.
The -63.6 dBc fractional spur at 250 kHz offset is
at a worst case frequ ency of 3130.25 MHz. The
-77.2 dBc sub-fractional spur at 125 kHz offset is
also visible.
Worst case channels occur at exactly one
channel spacing above or below a multiple of the
crystal frequency.
9
LMX2531LQ3010E EVALUATION BOARD OPERATING INSTRUCTIONS
Fractional S purs (Internal Divide by 2 Enabled)
The -65.2 dBc fractional spur at 250 kHz offset is
at a worst case frequency of 1455.125 M Hz. Th e
-77.8 dBc sub-fractional spur at 125 kHz offset is
also visible.
The -73.1 dBc fractional spur at 250 kHz offset is
at a worst case frequency of 1505.125 M Hz. Th e
-77.6 dBc sub-fractional spur at 125 kHz offset is
also visible.
The -73.5 dBc fractional spur at 250 kHz offset is
at a worst case frequency of 1565.125 M Hz. Th e
-81.9 dBc sub-fractional spur at 125 kHz offset is
also visible.
10
LMX2531LQ3010E EVALUATION BOARD OPERATING INSTRUCTIONS
Integer S purs (Internal Divide by 2 Disabled)
The integer spur at 10 MHz offset at an Fout
frequency of 2910 MHz is -84.2 dB c.
The integer spur at 10 MHz offset at an Fout
frequency of 3010 MHz is -85.0 dB c.
The integer spur at 10 MHz offset at an Fout
frequency of 3130 MHz is -83.3 dB c.
11
LMX2531LQ3010E EVALUATION BOARD OPERATING INSTRUCTIONS
Integer S purs (Internal Divide by 2 Enabled )
The integer spur at 10 MHz offset at an Fout
frequency of 1455 MHz is -84.3 dB c.
The integer spur at 10 MHz offset at an Fout
frequency of 1505 MHz is -84.1 dB c.
The integer spur at 10 MHz offset at an Fout
frequency of 1565 MHz is -84.1 dB c.
12
LMX2531LQ3010E EVALUATION BOARD OPERATING INSTRUCTIONS
In-band Factional S purs Integer Spurs (Intern al Divide by 2 Disabled)
The In-band fractional spur at 5 kHz offset at an
Fout frequency of 291 0.005 MHz is -46.0 d Bc.
ORDER = 4th Order Modulat or
Fractional numerato r = 500
Fractional denominato r = 1,000,000
The In-band fractional spur at 5 kHz offset at an
Fout frequency of 301 0.005 MHz is -31.2 d Bc.
ORDER = 4th Order Modulat or
Fractional numerato r = 500
Fractional denominato r = 1,000,000
The In-band fractional spur at 5 kHz offset at an
Fout frequency of 313 0.005 MHz is -32.6 d Bc.
ORDER = 4th Order Modulat or
Fractional numerato r = 500
Fractional denominato r = 1,000,000
13
LMX2531LQ3010E EVALUATION BOARD OPERATING INSTRUCTIONS
In-band Factional S purs Integer Spurs (Intern al Divide by 2 Enabled)
The In-band fractional spur at 5 kHz offset at an
Fout frequency of 145 5.0025 MHz is -46.3 dBc.
ORDER = 4th Order Modulat or
Fractional numerato r = 500
Fractional denominato r = 1,000,000
The In-band fractional spur at 5 kHz offset at an
Fout frequency of 150 5.0025 MHz is -39.0 dBc.
ORDER = 4th Order Modulat or
Fractional numerato r = 500
Fractional denominato r = 1,000,000
The In-band fractional spur at 5 kHz offset at an
Fout frequency of 156 5.0025 MHz is -37.3 5 dBc.
ORDER = 4th Order Modulat or
Fractional numerato r = 500
Fractional denominato r = 1,000,000
14
LMX2531LQ3010E EVALUATION BOARD OPERATING INSTRUCTIONS
Inter-modulation Spurs
The LMX2531 featu res an o utput divider which may divide the VCO frequency by two. The result is an
Fout frequency half the VCO frequency. When this VCO divider i s enabled a spur will occur between a
multiple of the phase d etector frequency an d the Fout frequency.
In the example below the phase detector frequency (FPD) is 10 MHz. The VCO freq uenc y is 3020.0 05
MHz. The divide by two is enab led and the out put frequency (Fout) is 1510.0025 MHz
1510 MHz = 1 0 MHz * 151, whi ch is a mult iple of the FPD.
1510.0025 MHz is t he divided outp ut frequency.
Therefore a spur wi ll occur at 2.5 kHz offset = (1510. 0025 – 1510 MHz)
If the frequency was set to 1 509.9975 MH z there would be a sp ur at 2.5 kHz becaus e:
1510 MHz = 1 0 MHz * 151, whi ch is a mult iple of the FPD.
1509.9975 MHz is t he divided outp ut frequency.
Therefore a spur wi ll occur at 2.5 kHz offset = (1509. 9975 – 1510 MHz)
Technically there are spurs at caused by mixing with all multiples of the phase detector frequency but
they will be far away from the carrier and the loop filt er will eliminate them.
The spur shown below at 2.5 kHz off from 1510.0025 MHz is an example of inter-modulation that
occurs. This only happen s when the VCO divider is enabled.
15
LMX2531LQ3010E EVALUATION BOARD OPERATING INSTRUCTIONS
CodeLoader Settings
Select Device
CodeLoader runs many devices. When CodeLoader is first started, it is
necessary to select the correct device.
16
LMX2531LQ3010E EVALUATION BOARD OPERATING INSTRUCTIONS
Select Mode
There can be different modes defined for a particular part. A mode can be
recalled easily from the menu. This restores bit settings and frequencies, but not
the Port Setup information. For the CodeLoader program, the default reference
oscillator used for these instructions was 10 MHz, but there is a mode for a 61.44
MHz oscillator as well. If the bits become scrambled, their original state may be
recalled by choosing the appropriate mode.
17
LMX2531LQ3010E EVALUATION BOARD OPERATING INSTRUCTIONS
Bit s/Pins
The Bits/Pins tab displays many of the bits used to program the part. Right
mouse click any bit to view more information about what this does.
18
LMX2531LQ3010E EVALUATION BOARD OPERATING INSTRUCTIONS
PLL/VCO
The PLL/VCO tab shows all the important PLL controls. Reference Oscillator
should be programmed to the reference frequency connected to the OSCin of the
evaluation board. R Counter, Phase Detector Frequency, N Counter, and
Charge Pump Gain should be set to provide the desired output frequency with an
optimized loop filter. The desired VCO frequency may also be entered directly
into the VCO frequency box.
The LMX2531 also has an output divider which can be enabled by change divide
value from 1 to 2 by Fout frequency box. Be sure to load the device (Ctrl+L) after
changing this divider to allow the VCO to calibrate for optimal phase noise
performance.
19
LMX2531LQ3010E EVALUATION BOARD OPERATING INSTRUCTIONS
Registers
The Registers tab shows the literal bits that are being s ent to the part. These are
the registers every time the PLL is loaded by using the menu command or Ctrl+L.
R5 (INIT1) and R5 (INIT 2) are just the R5 register being used to properly
initialize the part. So a single Ctrl+L will load the part.
20
LMX2531LQ3010E EVALUATION BOARD OPERATING INSTRUCTIONS
Port Setup
The port setup tells CodeLoader what information goes where. If this is wrong,
the part will not program. Although LPT1 is usually correct, CodeLoader does
NOT automatically detect the correct port. On some laptops, it may be LPT3.
21
LMX2531LQ3010E EVALUATION BOARD OPERATING INSTRUCTIONS
22
Schematic
R6
R16 R15 R13 R12 R11
R2_LF
R8
C7
C2pLF
C2_LF
C1_LF
R14
C8
1 2
3 4
5 6
7 8
910
uWIRE
R10
C6
R2pLF
C16
FRAME
Fout
Vcc
R21
R19
R20
C1
R2
C12
C2
VccVCO
VccDIG
VccPLL
VccBUF
R3
C3
C17
R4
C9
C4
R5
C5
OSCin
VccVCO
VccPLL
VccBUF
C13
C18
C20
R7
R23
R22
Ftest/LD
C15
C22
R1
R9
TRIGGER
GND
1 2
3 4
5 6
7 8
POWER
C24
C14
C11
C19
C21
C23
Note that Any Com ponent with Designator 100 or Higher is on the Bottom Side of the Board
C10
Vcc
Vcc
R18
R24
R17
C105
C100
C101
C103
C104
C102
VccDIG
VccDIG
1
NC
2
GND
3
NC
4
NC
5
NC/VregBUF
6
NC
7
DATA
8
CLK
9
LE
10
CE
11
NC
12
NC
13
NC
14
NC
15
VccVCO
16
VregVCO
17
VrefVCO
18
GND 19
GND 20
Fout 21
VccBUF 22
Vtune 23
CPout 24
FLout 25
VregPLL1 26
VccPLL 27
GND 34
NC 29
Ftest/LD 30
OSCin 31
OSCin* 32
Test 33
NC 35
VregDIG 36
VregPLL2 28
SLG1
37
SLG2
38
U1
LMX2531LQA
LMX2531LQ3010E EVALUATION BOARD OPERATING INSTRUCTIONS
23
Bill of Materials
Bill of Materials LMX2531_HF Revision 3.28.2008
Item QTY Manufacturer Part # Size Tol Voltage Material Value Designators
0 20 n/a Open Capacitors C1_LF, C2pLF, C2, C3, C4, C5, C9,
C11, C14, C17, C18, C19, C21, C24,
C100, C101, C102, C103, C104, C105
7 Open Resistors R2pLF,R7, R8, R17, R19, R21, R24
1 Open Miscellaneous Ftest/LD
1 1 Kemet C0603C101J5GAC 603 5% 50V C0G 100pF C16
2 2 Kemet C0603C103J5RAC 603 5% 50V X7R 10nF C10, C23
3 1 Kemet C0805C104K5RACTU 805 5% 25V C0G 100nF C2_LF
4 6 Kemet C0603C104J3RAC 603 5% 25V X7R 100nF C6, C7, C12, C15, C22, C20
5 1 Kemet C0603C105K4RAC 603 10% 16V X5R 1uF C8
6 1 Kemet C0603C475K9PAC 603 10% 6.3V X5R 4.7uF C13
7 1 Kemet C0805C106K8PAC 805 10% 10V X5R 10uF C1
8 1 Vishay CRCW0603000ZRT1 603 5% 0.1W Thick Film 0
Ω
R20
9 2 Panasonic P.22AHCT-ND 603 10% 0.1W Thick Film 0.22
Ω
R22, R23
10 2 Vishay CRCW06033R3JRT1 603 5% 0.1W Thick Film 3.3
Ω
R1, R18
11 4 Vishay CRCW0603100JRT1 603 5% 0.1W Thick Film 10
Ω
R2, R3, R4, R5
12 1 Vishay CRCW0603510JRT1 603 5% 0.1W Thick Film 51Ω R6
13 1 Vishay CRCW0603102JRT1 603 5% 0.1W Thick Film 1K
Ω
R2_LF
14 4 Vishay CRCW0603103JRT1 603 5% 0.1W Thick Film 10K
Ω
R9, R11, R13, R15
15 4 Vishay CRCW0603123JRT1 603 5% 0.1W Thick Film 12K
Ω
R10, R12, R14, R16
16 1 Comm Con
Connectors HTSM3203-8G2 2X4 n/a n/a Metal/Plastic Header POWER
17 1 FCI Electronics 52601-S10-8 2X5 n/a n/a Metal/Plastic Header uWire
18 3 Johnson Components 142-0701-851 SMA n/a n/a Metal SMA Fout, OSCin, Vcc
19 1 National
Semiconductor LMX2531LQEBPCB n/a n/a n/a FR4 PCB Board n/a
62 mil Thick 1st Layer 10 mils
20 1 National
Semiconductor LMX2531 LLP36 n/a 2.7 Silicon LMX2531 U1
21 4 Com Con Connectors CCIJ255G 2-Pin n/a n/a Metal/Plastic Shunt Place Across:
POWER: 1-2, 3-4, 5-6, 7-8
22 4 SPC Technology SPCS-8 0.156" n/a n/a Nylon Nylon Standoffs Place in 4 Holes in Corners of Board
LMX2531LQ3010E EVALUATION BOARD OPERATING INSTRUCTIONS
T op Layer
24
LMX2531LQ3010E EVALUATION BOARD OPERATING INSTRUCTIONS
Mid Layer 1 "Ground Plane"
(15 mils below top FR4 layer)
25
LMX2531LQ3010E EVALUATION BOARD OPERATING INSTRUCTIONS
Mid Layer 2 "Power"
26
LMX2531LQ3010E EVALUATION BOARD OPERATING INSTRUCTIONS
Bottom Layer "Signal"
Note: Total Board Thickness = 61 m ils
27
LMX2531LQ3010E EVALUATION BOARD OPERATING INSTRUCTIONS
28
Top Build Diagram
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