1
Data sheet acquired from Harris Semiconductor
SCHS157C
Features
• Buffered Inputs
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating T emperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
Pinout
CD54HC166, CD54HCT166
(CERDIP)
CD74HC166, CD74HCT166
(PDIP, SOIC)
TOP VIEW
Description
The ’HC166 and ’HCT166 8-bit shift register is fabricated
with silicon gate CMOS technology. It possesses the low
power consumption of standard CMOS integrated circuits,
and can operate at speeds comparable to the equivalent low
power Schottky device.
The ’HCT166 is functionally and pin compatible with the
standard ’LS166.
The 166 is an 8-bit shift register that has fully synchronous
serial or parallel data entry selected by an active LOW Parallel
Enable (PE) input. When the PE is LOW one setup time before
the LOW-to-HIGH clock transition, parallel data is entered into
the register. When PE is HIGH, data is entered into the internal
bit position Q0 from Serial Data Input (DS), and the remaining
bits are shifted one place to the right (Q0 →Q1 →Q2, etc.)
with each positive-going clock transition. For expansion of the
register in parallel to serial converters, the Q7 output is con-
nected to the DS input of the succeeding stage.
The clock input is a gated OR structure which allows one
input to be used as an active LOW Clock Enable (CE) input.
The pin assignment for the CP and CE inputs is arbitrary and
can be reversed for layout convenience. The LOW-to-HIGH
transition of CE input should only take place while the CP is
HIGH for predictable operation.
A LOW on the Master Reset (MR) input overrides all other
inputs and clears the register asynchronously, forcing all bit
positions to a LOW state.
Ordering Information
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
DS
D0
D1
D2
D3
CE
GND
CP
VCC
D7
Q7
D6
D5
D4
MR
PE
PART NUMBER TEMP. RANGE (oC) PACKAGE
CD54HC166F3A -55 to 125 16 Ld CERDIP
CD54HCT166F3A -55 to 125 16 Ld CERDIP
CD74HC166E -55 to 125 16 Ld PDIP
CD74HC166M -55 to 125 16 Ld SOIC
CD74HC166MT -55 to 125 16 Ld SOIC
CD74HC166M96 -55 to 125 16 Ld SOIC
CD74HCT166E -55 to 125 16 Ld PDIP
CD74HCT166M -55 to 125 16 Ld SOIC
CD74HCT166MT -55 to 125 16 Ld SOIC
CD74HCT166M96 -55 to 125 16 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
February 1998 - Revised October 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
CD54HC166, CD74HC166,
CD54HCT166, CD74HCT166
High-Speed CMOS Logic
8-Bit Parallel-In/Serial-Out Shift Register
[
/Title
(
CD74
H
C166
,
C
D74
H
CT16
6
)
/
Sub-
j
ect
(
High
S
peed
C
MOS
L
ogic
8
-Bit
P
aral-
l
el-
I
n/Seri
2
Functional Diagram
TRUTH TABLE
INPUTS INTERNAL
Q STATES OUTPUT
Q7
MASTER
RESET PARALLEL
ENABLE CLOCK
ENABLE CLOCK SERIAL
PARALLEL
D0 D7 Q0 Q1
LXXXXXLLL
H X L L X X Q00 Q10 Q0
HLL↑X a...h a b h
HHL↑H X H Q0n Q6n
HHL↑L X L Q0n Q6n
HXH↑X X Q00 Q10 Q70
H= High Voltage Level
L= Low Voltage Level
X= Don’t Care
↑= Transition from Low to High Level
a...h = The level of steady-state input at inputs D0 thru D7, respectively.
Q00, Q10, Q70 = The level of Q0, Q1, or Q7, respectively, before the indicated steady-state input conditions were established.
Q0n, Q6n = The le v el of Q0 or Q6, respectiv ely, before the most recent ↑ transition of the clock.
8 - REGISTERS
PARALLEL ENABLE CIRCUIT
D0 D1 D2 D3 D4 D5 D6 D7
PE
DS
CP
CE
MR
D0 D7
Q7
CD54HC166, CD74HC166, CD54HCT166, CD74HCT166
3
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, IO
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Resistance (Typical, Note 1) θJA (oC/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
PARAMETER SYMBOL
TEST
CONDITIONS
VCC (V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HC TYPES
High Level Input
Voltage VIH - - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input
Voltage VIL - - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level Output
Voltage
CMOS Loads
VOH VIH or
VIL -0.02 2 1.9 - - 1.9 - 1.9 - V
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
High Level Output
Voltage
TTL Loads
-4 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 6 5.48 - - 5.34 - 5.2 - V
Low Level Output
Voltage
CMOS Loads
VOL VIH or
VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC or
GND -6--±0.1 - ±1-±1µA
CD54HC166, CD74HC166, CD54HCT166, CD74HCT166
4
Quiescent Device
Current ICC VCC or
GND 0 6 - - 8 - 80 - 160 µA
HCT TYPES
High Level Input
Voltage VIH - - 4.5 to
5.5 2-- 2 - 2 - V
Low Level Input
Voltage VIL - - 4.5 to
5.5 - - 0.8 - 0.8 - 0.8 V
High Level Output
Voltage
CMOS Loads
VOH VIH or
VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V
High Level Output
Voltage
TTL Loads
-4 4.5 3.98 - - 3.84 - 3.7 - V
Low Level Output
Voltage
CMOS Loads
VOL VIH or
VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
4 4.5 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current IIVCC to
GND 0 5.5 - - ±0.1 - ±1-±1µA
Quiescent Device
Current ICC VCC or
GND 0 5.5 - - 8 - 80 - 160 µA
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
∆ICC
(Note 2) VCC
-2.1 - 4.5 to
5.5 - 100 360 - 450 - 490 µA
NOTE:
2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS
VCC (V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HCT Input Loading Table
INPUT UNIT LOADS
DS, D0-D7 0.2
PE 0.35
CP, CE 0.5
MR 0.2
NOTE: Unit Load is ∆ICC limit specified in DC Electrical
Specifications table, e.g., 360µA max at 25oC.
Prerequisite For Switching Specifications
PARAMETER SYMBOL VCC (V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN MAX MIN MAX MIN MAX
HC TYPES
Clock Frequency
(Figure 1) fMAX 26-5-4-MHz
4.5 30 - 25 - 20 - MHz
6 35 - 29 - 23 - MHz
CD54HC166, CD74HC166, CD54HCT166, CD74HCT166
5
MR Pulse Width
(Figure 1) tw2 100 - 125 - 150 - ns
4.5 20 - 25 - 30 - ns
617-21-26-ns
Clock Pulse Width
(Figure 1) tW2 80 - 100 - 120 - ns
4.5 16 - 20 - 24 - ns
614-17-20-ns
Set-up Time
Data and CE to Clock
(Figure 5)
tSU 2 80 - 100 - 120 - ns
4.5 16 - 20 - 24 - ns
614-17-20-ns
Hold Time
Data to Clock
(Figure 5)
tH21-1-1-ns
4.51-1-1-ns
61-1-1-ns
Removal Time
MR to Clock
(Figure 5)
tREM 20-0-0-ns
4.50-0-0-ns
60-0-0-ns
Set-up Time
PE to CP
(Figure 5)
tSU 2 145 - 180 - 220 - ns
4.5 29 - 36 - 44 - ns
625-31-38-ns
Hold Time
PE to CP or CE
(Figure 5)
tH20-0-0-ns
4.50-0-0-ns
60-0-0-ns
HCT TYPES
Clock Frequency (Figure 2) fMAX 4.5 25 - 20 - 16 - MHz
MR Pulse Width (Figure 2) tw4.5 35 - 44 - 53 - ns
Clock Pulse Width (Figure 2) tw4.5 20 - 25 - 30 - ns
Set-up Time Data and CE to
Clock (Figure 6) tSU 4.5 16 - 20 - 24 - ns
Hold Time Data to Clock
(Figure 6) tH4.50-0-0-ns
Removal Time MR to Clock
(Figure 6) tREM 4.50-0-0-ns
Set-up Time PE to CP (Figure 6) tSU 4.5 30 - 38 - 45 - ns
Hold Time PE to CP or CE
(Figure 6) tH4.50-0-0-ns
Switching Specifications Input tr, tf = 6ns
PARAMETER SYMBOL TEST
CONDITIONS VCC (V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSTYP MAX MAX MAX
HC TYPES
Propagation Delay,
Clock to Output (Figure 3) tPLH, tPHL CL= 50pF 2 - 160 200 240 ns
4.5 - 32 40 48 ns
CL= 15pF 5 13 - - - ns
CL = 50pF 6 - 27 34 41 ns
Prerequisite For Switching Specifications (Continued)
PARAMETER SYMBOL VCC (V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN MAX MIN MAX MIN MAX
CD54HC166, CD74HC166, CD54HCT166, CD74HCT166
6
Output Transition Time
(Figure 3) tTLH, tTHL CL= 50pF 2 - 75 95 110 ns
4.5 - 15 19 22 ns
6 - 13 16 19 ns
Propagation Delay
MR to Output
(Figure 3)
tPHL CL= 50pF 2 - 160 200 240 ns
4.5 - 32 40 48 ns
6 - 27 34 41 ns
Input Capacitance CI---1010 10pF
Power Dissipation
Capacitance
(Notes 3, 4)
CPD - 5 41 - - - pF
HCT TYPES
Propagation Delay,
Clock to Output
(Figure 4)
tPLH, tPHL CL= 50pF 4.5 - 40 50 60 ns
Output Transition Time
(Figure 4) tTLH, tTHL CL= 50pF 4.5 - 15 19 22 ns
Propagation Delay
MR to Output (Figure 4) tPHL CL= 50pF 4.5 - 40 50 60 ns
Input Capacitance CI---1010 10pF
NOTES:
3. CPD is used to determine the dynamic power consumption, per gate.
4. PD=CPD VCC2fi+∑(CLVCC2+f
O) where fi= Input Frequency, fO= Output Frequency, CL= Output Load Capacitance, VCC = Supply
Voltage.
Switching Specifications Input tr, tf = 6ns (Continued)
PARAMETER SYMBOL TEST
CONDITIONS VCC (V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSTYP MAX MAX MAX
Test Circuits and Waveforms
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
CLOCK 90% 50%
10% GND
VCC
trCLtfCL
50% 50%
tWL tWH
10%
tWL + tWH =fCL
I
CLOCK 2.7V 1.3V
0.3V GND
3V
trCL= 6ns tfCL= 6ns
1.3V 1.3V
tWL tWH
0.3V
tWL + tWH =fCL
I
CD54HC166, CD74HC166, CD54HCT166, CD74HCT166
7
FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
Test Circuits and Waveforms (Continued)
tPHL tPLH
tTHL tTLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
VCC
tr = 6ns tf = 6ns
90%
tPHL tPLH
tTHL tTLH
2.7V
1.3V
0.3V
1.3V
10%
INVERTING
OUTPUT
INPUT
GND
3V
tr = 6ns tf = 6ns
90%
trCLtfCL
GND
VCC
GND
VCC
50%
90%
10%
GND
CLOCK
INPUT
DATA
INPUT
OUTPUT
SET, RESET
OR PRESET
VCC 50%
50%
90%
10%
50%
90%
tREM
tPLH
tSU(H)
tTLH tTHL
tH(L)
tPHL
IC CL
50pF
tSU(L)
tH(H)
trCLtfCL
GND
3V
GND
3V
1.3V
2.7V
0.3V
GND
CLOCK
INPUT
DATA
INPUT
OUTPUT
SET, RESET
OR PRESET
3V 1.3V
1.3V
1.3V
90%
10%
1.3V
90%
tREM
tPLH
tSU(H)
tTLH tTHL
tH(L)
tPHL
IC CL
50pF
tSU(L)
1.3V
tH(H)
1.3V
CD54HC166, CD74HC166, CD54HCT166, CD74HCT166
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
CD54HC166F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
CD54HCT166F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
CD74HC166E ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CD74HC166EE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CD74HC166M ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC166M96 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC166M96E4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC166M96G4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC166ME4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC166MG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC166MT ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC166MTE4 ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC166MTG4 ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT166E ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CD74HCT166EE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
CD74HCT166M ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT166M96 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT166M96E4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT166M96G4 ACTIVE SOIC D 16 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT166ME4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT166MG4 ACTIVE SOIC D 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT166MT ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT166MTE4 ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT166MTG4 ACTIVE SOIC D 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HCT166TM96Q1 OBSOLETE SOIC D 16 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
PACKAGE OPTION ADDENDUM
www.ti.com 15-Oct-2009
Addendum-Page 1
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 15-Oct-2009
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
CD74HC166M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD74HCT166M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Mar-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC166M96 SOIC D 16 2500 333.2 345.9 28.6
CD74HCT166M96 SOIC D 16 2500 333.2 345.9 28.6
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Mar-2008
Pack Materials-Page 2
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