© 2000 Fairchild Semiconductor Corporation DS006397 www .fairchildsemi.com
August 1986
Revised April 2000
DM74LS161A • DM74LS163A Synchronous 4-Bit Binary Counters
DM74LS161A • DM74LS163A
Synchronous 4-Bit Binary Counters
General Descript ion
These synchr onous, presetta ble counters featu re an inter-
nal car ry lo ok- ahe ad for a ppli ca tion i n high -sp eed co unting
designs. The DM74LS161A and DM74LS163A are 4-bit
binary counters. The carry output is decoded by means of
a NOR gate, thus preventing spikes during the normal
counting mode of operation. Synchronous operation is pro-
vided by having all flip-flops clocked simultaneously so that
the outputs change coincident with each other when so
instructed by the count-enable inputs and internal gating.
This mode of operation eliminates the output counting
spikes which are normally associated with asynchronous
(ripple clock) counters. A buffered clock input triggers the
four flip-flops on the rising (positive-going) edge of the
clock input waveform.
These counters are fully programmable; that is, the outputs
may be preset to either level. As presetting is synchronous,
setting up a low level at the load in pu t disab les th e co unter
and causes th e outputs to agree with the setup data aft er
the next cl ock p ulse, re gardle ss of the le vels of th e ena ble
input. The clear function for the DM74LS161A is asynchro-
nous; and a low level at the clear input se ts all four of the
flip-flop outputs LOW, regardless of the levels of clock,
load, or enable inputs. The clear function for the
DM74LS1 63A is synch ronous; a nd a low l evel at the clear
inputs sets all four of the flip-flop outputs LOW after the
next clock pulse, regardless of the levels of the enable
inputs. This synchronous clear allows the count length to
be modified easily, as decoding the maximum count
desired can be accomplished with one external NAND
gate. The gate output is connected to the clear input to
synchronously clear the counter to all low outputs.
The carry look-ahead circuitry provides for cascading
counters for n-bit synchronous applications without addi-
tional gating. Instrumental in accomplishing this function
are two count-enable inputs and a ripple carry output.
Both count-enable inputs (P and T) must be HIGH to count,
and inp ut T i s fed for ward to e nab l e th e rip ple ca rr y output.
The ripple carry output thus enabled will produce a high-
level output pulse with a duration approximately equal to
the high-level portion of the QA output. This high-level over-
flow ripple carry pulse can be used to enable successive
cascaded stages. HIGH-to-LOW level transitions at the
enable P or T inputs may occur, regardless of the logic
level of the clock.
These counters feature a fully independent clock circuit.
Changes made to control inputs (enable P or T or load) that
will modify the operating mode have no effect until clocking
occurs . The funct ion of the counte r (whether enable d, dis-
abled, loading, or counting) will be dictated solely by the
conditi ons meeting the stable set-u p and hold times.
Features
■Synchronously programmable
■Internal look-ahead for fast counting
■Carry output for n-bit cascading
■Synchronous counting
■Load control line
■Diode-clamped inputs
■Typical propagation time, clock to Q output 14 ns
■Typical clock frequency 32 MHz
■Ty pical power dissipation 93 mW
Ordering Code:
Devices also available in Tape and R eel. Speci fy by appending the s uffix let t er “X” to the o rdering c ode.
Order Number Package Number Package Description
DM74LS161AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS161AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
DM74LS163AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS163AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
www.fairchildsemi.com 2
DM74LS161A • DM74LS163A
Connection Diagram
Logic Diagram
DM74LS163A
The DM 74LS161A is si m ilar, howev er, the clea r buffer is connected directly to the flip-flops.
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DM74LS161A • DM74LS163A
Parameter Measurement Information
Switching Time Waveforms
The inpu t p uls es are supplied by generat ors having th e f ollowing c haracteristics:
PRR ≤ 1 MHz, duty cycle ≤ 50%, ZOUT ≈ 50Ω, tR ≤ 10 ns, tF ≤ 10 ns.
Vary PRR to me as ure fMAX.
Outputs QD and carry are tested at tN+16 where tN is the bit time w hen all out puts are LO W.
VREF = 1.5V.
Switching Time Waveforms
The input pulses are supplied by g enerators having the follow ing charac te ris t ics:
PRR ≤ 1 MHz, duty cycle ≤ 50%, ZOUT ≈ 50Ω, tR ≤ 6 ns, tF ≤ 6 ns. Vary PRR to measure fMAX.
Enable P and enable T setup times are measu red at tN+0.
VREF = 1.3V.
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DM74LS161A • DM74LS163A
Timing Diagr am
LS16 1A, LS163A Synchronous Binary Counters
Typical Clear, Preset, Count and Inhibit Sequences
Sequence:
(1) Clear outputs to zero
(2) P res et to binary twelv e
(3) Count to thirteen, fourteen, fifteen, zero, one, and two
(4) Inhibit
5 www.fairchildsemi.com
DM74LS161A • DM74LS163A
Absolute Maximum Ratings(Note 1) Note 1: The “A bsol ute M axim um Ratin gs” are those valu es b eyo nd which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Re comm ended Operat ing Co ndition s” table will de fine the cond itions
for actu al device operation.
DM74LS161A Recommended Operating Conditions
Note 2: CL = 15 pF, RL = 2 kΩ, TA = 25°C and VCC = 5.5V.
Note 3: CL = 50 pF, RL = 2 kΩ, TA = 25°C and VCC = 5.5V.
Supply Voltage 7V
Input Voltage 7V
Operating Free Air Temperature Range 0°C to +70°C
Storage Temperature Range −65°C to +150°C
Symbol Parameter Min Nom Max Units
VCC Supply Voltage 4.75 5 5.25 V
VIH HIGH Level Input Voltage 2 V
VIL LOW Level Input Voltage 0.8 V
IOH HIGH Level Output Current −0.4 mA
IOL LOW Level Output Current 8 mA
fCLK Clock Frequency (Note 2) 0 25 MHz
Clock Frequency (Note 3) 0 20 MHz
tWPulse Width Clo ck 20 6 ns
(Note 2) Clear 20 9
Pulse Width Clo ck 25 ns
(Note 3) Clear 25
tSU Setup Time Data 20 8
(Note 2) Enable P 25 17 ns
Load 25 15
Setup Time Data 20
(Note 3) Enable P 30 ns
Load 30
tHHold Time Data 0 −3ns
(Note 2) Others 0 −3
Hold Time Data 5 ns
(Note 3) Others 5
tREL Clear Release Time (Note 2) 20 ns
Clear Release Time (Note 3) 25 ns
TAFree Air Operating Temperature 0 70 °C
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DM74LS161A • DM74LS163A
DM74LS161A Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Note 4: All typic als are at VCC = 5V, TA = 25°C.
Note 5: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 6: ICCH is measured w it h the loa d H I GH , th en again with the loa d LOW, with all other inputs HI GH and all out puts OP EN .
Note 7: ICCL is measured w it h t he clock input HIGH , th en again w it h t he clock input LOW, with all oth er input s L OW and all ou tp ut s OPEN.
DM74LS161A Switching Characteristics
at VCC = 5V and TA = 25°C
Symbol Parameter Conditions Min Typ Max Units
(Note 4)
VIInput Clamp Voltage VCC = Min, I I = −18 mA −1.5 V
VOH HIGH Level VCC = Min, IOH = Max 2.7 3.4 V
Output Voltage VIL = Max, VIH = Min
VOL LOW Level VCC = Min, IOL = Max 0.35 0.5
Output Voltage VIL = Max, VIH = Min V
IOL = 4 mA, VCC = Min 0.25 0.4
IIInput Current @ Max VCC = Max Enable T 0.2
Input Voltage VI = 7V Clock 0.2 mA
Load 0.2
Others 0.1
IIH HIGH Level VCC = Max Enable T 40
Input Current VI = 2.7V Clock 40 µA
Load 40
Others 20
IIL LOW Level VCC = Max Enable T −0.8
Input Current VI = 0.4V Clock −0.8 mA
Load −0.8
Others −0.4
IOS Short Circuit Output Current VCC = Max (Note 5) −20 −100 mA
ICCH Supply Current with Outputs HIGH VCC = Max (Note 6) 18 31 mA
ICCL Supply Current with Outputs LOW VCC = Max (Note 7) 19 32 mA
From (Input) RL = 2 kΩ
Symbol Parameter To (Output) CL = 15 pF CL = 50 pF Uni ts
Min Max Min Max
fMAX Maximum Clock Frequency 25 20 MHz
tPLH Propagation Delay Time Clock to 25 30 ns
LOW-to-HIGH Level Output Ripple Carry
tPHL Propagation Delay Time Clock to 30 38 ns
HIGH-to-LOW Level Output Ripple Carry
tPLH Propagation Delay Time Clock to Any Q 22 27 ns
LOW-to-HIGH Level Output (Load HIGH)
tPHL Propagation Delay Time Clock to Any Q 27 38 ns
HIGH-to-LOW Level Output (Load HIGH)
tPLH Propagation Delay Time Clock to Any Q 24 30 ns
LOW-to-HIGH Level Output (Load LOW)
tPHL Propagation Delay Time Clock to Any Q 27 38 ns
HIGH-to-LOW Level Output (Load LOW)
tPLH Propagation Delay Time Enable T to 14 27 ns
LOW-to-HIGH Level Output Ripple Carry
tPHL Propagation Delay Time Enable T to 15 27 ns
HIGH-to-LOW Level Output Rip ple Carry
tPHL Propagation Delay Time Clear to 28 45 ns
HIGH-to-LOW Level Output Any Q
7 www.fairchildsemi.com
DM74LS161A • DM74LS163A
DM74LS163A Recommended Operating Conditions
Note 8: CL = 15 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V.
Note 9: CL = 50 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V.
DM74LS163A Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Note 10: All typic als are at VCC = 5V, TA = 25°C.
Note 11: Not more th an one out put shoul d be shor te d at a t im e, and the duration sh ould not ex c eed one sec ond.
Note 12: ICCH is measured w it h t he load H IG H , th en again wit h t he load LOW, with all other inputs HIGH and all outputs OPEN .
Note 13: ICCL is meas ured wit h th e c lock input HIGH , then again with the c lock inpu t LO W, with all ot her input s LOW and all outpu t s O PEN.
Symbol Parameter Min Nom Max Units
VCC Supply Voltage 4.75 5 5.25 V
VIH HIGH Level Input V oltag e 2 V
VIL LOW Level Input Voltage 0.8 V
IOH HIGH Level Output Current −0.4 mA
IOL LOW Level Output Current 8 mA
fCLK Clock Frequency (Note 8) 0 25 MHz
Clock Frequency (Note 9) 0 20 MHz
tWPulse Width Clock 20 6 ns
(Note 8) Clear 20 9
Pulse Width Clock 25 ns
(Note 9) Clear 25
tSU Setup Time Data 20 8
(Note 8) Enable P 25 17 ns
Load 25 15
Setup Time Data 20
(Note 9) Enable P 30 ns
Load 30
tHHold Time Data 0 −3ns
(Note 8) Others 0 −3
Hold Time Data 5 ns
(Note 9) Others 5
tREL Clear Release Time (Note 8) 20 ns
Clear Release Time (Note 9) 25 ns
TAFree Air Operating Temperature 0 70 °C
Symbol Parameter Conditions Min Typ
(Note 10) Max Units
VIInput Clamp Voltage VCC = Min, II = −18 m A −1.5 V
VOH HIGH Level VCC = Min, IOH = Max 2.7 3.4 V
Output Voltage VIL = Max, VIH = Min
VOL LOW Level VCC = Min, IOL = Max 0.35 0.5
Output Voltage VIL = Max, VIH = Min V
IOL = 4 mA, VCC = Min 0.25 0.4
IIInput Current @ Max VCC = Max Enable T 0.2
Input V oltag e VI = 7V Clock, Clear 0.2 mA
Load 0.2
Others 0.1
IIH HIGH Level VCC = Max Enable T 40
Input Current VI = 2.7V Load 40 µA
Clock, Clear 40
Others 20
IIL LOW Level VCC = Max Enable T −0.8
Input Current VI = 0.4V Clock, Clear −0.8 mA
Load −0.8
Others −0.4
IOS Short Circuit Output Current VCC = Max (Note 11) −20 −100 mA
ICCH Supply Current with Outputs HIGH VCC = Max (Note 12) 18 31 mA
ICCL Supply Current with Outputs LOW VCC = Max (Note 13) 18 32 mA
www.fairchildsemi.com 8
DM74LS161A • DM74LS163A
DM74LS163A Switching Characteristics
at VCC = 5V and TA = 25°C
Note 14: The propagation delay c lear to outp ut is m easured f rom t he clock input transit ion.
From (Input) RL = 2 kΩ
Symbol Parameter To (Output) CL = 15 pF CL = 50 pF Units
Min Max Min Max
fMAX Maximum Clock Frequency 25 20 MHz
tPLH Propagation Delay Time Clock to 25 30 ns
LOW-to-HIGH Level Output Ripple Carry
tPHL Propagation Delay Time Clock to 30 38 ns
HIGH-to-LOW Level Output Ripple Carry
tPLH Propagation Delay Time Clock to Any Q 22 27 ns
LOW-to-HIGH Level Output (Load HIGH)
tPHL Propagation Delay Time Clock to Any Q 27 38 ns
HIGH-to-LOW Level Output (Load HIGH)
tPLH Propagation Delay Time Clock to Any Q 24 30 ns
LOW-to-HIGH Level Output (Load LOW)
tPHL Propagation Delay Time Clock to Any Q 27 38 ns
HIGH-to-LOW Level Output (Load LOW)
tPLH Propagation Delay Time Enable T to 14 27 ns
LOW-to-HIGH Level Output Ripple Carry
tPHL Propagation Delay Time Enable T to 15 27 ns
HIGH-to-LOW Level Output Ripple Carry
tPHL Propagation Delay Time Clear to Any Q 28 45 ns
HIGH-to-LOW Level Output (Note 14)
9 www.fairchildsemi.com
DM74LS161A • DM74LS163A
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
www.fairchildsemi.com 10
DM74LS161A • DM74LS163A Synchronous 4-Bit Binary Counters
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does no t assume any responsibility for use of any circuitry de scribed, no circuit patent licenses ar e implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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device or system whose failure to perform can be rea-
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device or system, or to affect its safety or effectiveness.
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