5-1
FAST AND LS TTL DATA
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
The SN54/74LS112A dual JK flip-flop features individual J, K, clock, and
asynchronous set and clear inputs to each flip-flop. When the clock goes
HIGH, the inputs are enabled and data will be accepted. The logic level of the
J and K inputs may be allowed to change when the clock pulse is HIGH and
the bistable will perform according to the truth table as long as minimum set-up
and hold time are observed. Input data is transferred to the outputs on the
negative-going edge of the clock pulse.
LOGIC DIAGRAM (Each Flip-Flop)
Q5(9)
CLEAR (CD)
15(14)
J
3(11)
Q
6(7)
SET (SD)
4(10)
K
2(12)
1(13)
CLOCK (CP)
MODE SELECT — TRUTH TABLE
OPERATING MODE
INPUTS OUTPUTS
OPERATING
MODE
SDCDJ K Q Q
Set
Reset (Clear)
*Undetermined
Toggle
Load “0” (Reset)
Load “1” (Set)
Hold
L
H
L
H
H
H
H
H
L
L
H
H
H
H
X
X
X
h
l
h
l
X
X
X
h
h
l
l
H
L
H
q
L
H
q
L
H
H
q
H
L
q
* Both outputs will be HIGH while both SD and CD are LOW, but the output states
are unpredictable if SD and CD go HIGH simultaneously.
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input (or output)
l, h (q) = one set-up time prior to the HIGH to LOW clock transition.
SN54/74LS112A
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16 1
16
1
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
16 1
D SUFFIX
SOIC
CASE 751B-03
LOGIC SYMBOL
VCC = PIN 16
GND = PIN 8
4
3
1
2
15
5
6
SD
J
CP
KCDQ
Q
10
11 9
1312
14
7
SD
J
CP
KCDQ
Q
5-2
FAST AND LS TTL DATA
SN54/74LS112A
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 54
74 4.5
4.75 5.0
5.0 5.5
5.25 V
TAOperating Ambient Temperature Range 54
74 –55
025
25 125
70 °C
IOH Output Current — High 54, 74 –0.4 mA
IOL Output Current — Low 54
74 4.0
8.0 mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Sbl
P
Limits
Ui
T C di i
Symbol Parameter Min Typ Max Unit Test Conditions
VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for
All Inputs
VIL
Input LOW Voltage
54 0.7
V
Guaranteed Input LOW Voltage for
V
IL
I
npu
t
LOW
V
o
lt
age 74 0.8
V
pg
All Inputs
VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
V
O HIGH V l
54
25
35
V
V MIN I MAX V V
VOH
Output HIGH Voltage
54
2
.
5
3
.
5
V
VCC = MIN, IOH = MAX, VIN = VIH
V
OH
Output
HIGH
Voltage
74 2.7 3.5 V
CC ,OH ,IN IH
or VIL per T ruth Table
VOL
Output LOW Voltage
54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,
VIN =V
IL or VIH
V
OL
O
u
t
pu
t
LOW
V
o
lt
age 74 0.35 0.5 V IOL = 8.0 mA
V
IN =
V
IL or
V
IH
per T ruth Table
IIH
J, K
Set, Clear
Clock
20
60
80 µA VCC = MAX, VIN = 2.7 V
I
IH
npu
urren
J, K
Set, Clear
Clock
0.1
0.3
0.4 mA VCC = MAX, VIN = 7.0 V
IIL Input LOW Current J, K
Clear, Set, Clk –0.4
–0.8 mA VCC = MAX, VIN = 0.4 V
IOS Short Circuit Current (Note 1) –20 –100 mA VCC = MAX
ICC Power Supply Current 6.0 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Sbl
P
Limits
Ui
T C di i
Symbol Parameter Min Typ Max Unit Test Conditions
fMAX Maximum Clock Frequency 30 45 MHz
V50V
tPLH Propagation Delay, Clock 15 20 ns VCC = 5.0 V
C
L
= 15
p
F
PLH
tPHL
pg y,
Clear, Set to Output 15 20 ns
CL
=
15
pF
AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Sbl
P
Limits
Ui
T C di i
Symbol Parameter Min Typ Max Unit Test Conditions
tWClock Pulse Width High 20 ns
V50V
tWClear, Set Pulse Width 25 ns
VCC =50V
tsSetup T ime 20 ns
V
CC =
5
.
0
V
thHold T ime 0 ns