Multiline ATU-C
Analog Front End IC
Digital Interface
V0.1.0
DataPath Systems, Inc.
04/22/2000
For further information, please contact:
Cormac Conroy 408-365-6073 cconroy@DataPathSystems.Com
Phil Welsh 408-365-6058 pwelsh@DataPathSystems.Com
FAX: 408-365-0530
Mailing address: 5883 Rue Ferrari, Suite 10, San Jose, CA 95138
DataPath Systems, Inc. Multiline ADSL ATU-C Analog Front End IC Digital Interface V0.1.0 04/22/2000
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1 General Description
This document describes the digital interfaces for future DataP ath multi-channel CO ADSL AFE’s
f or product gener ations following after the previously-announced DPS8002 dual CO AFE — e.g.,
potentially quad, hex, octal etc.
☛Note: in this document, the number of channels is N, and the
designated numbering scheme for the N channels is: 0, 1, ..., N–1.
To simplify the notation, the symbol M is used as follows: M = N–1.
e.g. For a quad AFE: N=4 and M=3, for an octal N=8 and M=7.
The digital data interface for the TX and RX data consists of 3N signals: N groups of 3.
For each channel, the TX data consists of a 2-bit data stream at 17.6 MHz, to suppor t a
2.208 MHz incoming TX data rate, with a 16-bit DAC word.
For each channel, the RX data consists of a 1-bit data stream either (a) at 17.6 MHz, to support
up to 1.104 MHz outgoing data rate, or (b) at 8.832 MHz, to suppor t a 552 kHz outgoing data
rate, with a 16-bit ADC word.
The chip requires a single low-jitter 35.328 MHz clock to be applied at the MCLK pin. All clock
generation is performed internally and all converter and S/H clocks in both RX and TX paths are
directly derived from MCLK. An independent asynchronous 4-wire serial port is used for control
of gains, attenuations, modes etc.
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2 Digital Interface Functionality
MCLK
(35.328 MHz)
TX0[1:0]
(17.664 MHz)
RX0
(17.664 MHz
2
TXM[1:0]
WCLK
(1.104 MHz
Serial
to
Parallel
/
Parallel
to
Serial
16
16
AFE Internal SignalsAFE I/O’s
1.1 MS/s
DAC/TX path
2.2 MHz
ADC/RX path
Serial port control
or 8.832 MHz)
(1M.664 MHz)
2
RXM
(17.664 MHz
or 8.832 MHz)
1
1
...
or 552 kS/s
16
16
1.1 MS/s
DAC/TX path
2.2 MHz
ADC/RX path
or 552 kS/s
Channel 0
Channel M
...
4
Channel 0
Channel M
or 552 kHz)
To DSP
M = N – 1
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3 Digital Pin Function Description
In the following table: DI = digital input, DO = digital output, DIO = digital I/O.
Pin Name Type Pin Function Description
MCLK DI Master reference clock input: 35.328 MHz
WCLK DO Strobe / frame-sync digital output
TXM[1:0],...,TX0[1:0] DI TX digital inputs
RXM,...,RX0 DO RX digital outputs
S_DOUT DO Serial port data output from IC
S_CLK DI Serial port clock input to IC
S_EN DI Serial port enable input to IC
S_DIN DI Serial port data input to IC
RESETB DI Resets internal state of chip (active low)
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4 Digital Interfaces
4.1 ADC and DAC Digital Interfaces
1The incoming word for each AFE TX channel is 2 bits wide at 17.664 MHz. This is to
suppor t a 2.2 MHz data rate for each TX channel. Inter nally, the data is upsampled to
4.4 MHz before going to the 4.4 MHz DAC for each channel.
2The outgoing word for each AFE RX channel is 1 bit wide at 17.664 MHz. This is to
suppor t up to a 1.1 MS/s ADC for each channel. For a 552 kS/s ADC, the RX digital
outputs run at 8.832 MHz.
3Below in Fig. 1 is a diagram showing explicitly the way two DAC words are transmitted to
the AFE during the same time that one ADC word is received for 1.104 MS/s ADC
operation; Fig. 2 sho ws the case of 552 kS/s ADC oper ation where the RX digital outputs
are changing at an 8.832 MHz rate.
4TX0[1:0],..., TXM[1:0] are the TX digital inputs to the AFE, two per channel, for channels
0, ..., M, respectively.
RX0, ..., RXM are the RX outputs from the AFE, one per channel, for channels 0, ..., M,
respectively.
DA0[15:0], ..., DAM[15:0], are the internal 16-bit DAC words for channels 0, ..., M,
respectively.
AD0[15:0], ..., ADM[15:0] are the internal 16-bit ADC words for channels 0, ..., M,
respectively.
5In all the DA0[], ..., DAM[], and AD0[], ..., ADM[] words: bit 15 is the MSB and bit 0 is the
LSB.
6There is another signal called “WCLK” which is a star t-of-word mar ker and is always at
either 1.104 MHz or 552 kHz. WCLK is an output from the AFE; it may be viewed as a
“star t of words” signal and should be used by the DSP to align the outgoing transmit
digital data and incoming receive data. WCLK transitions only on the rising edge of the
17.664 MHz clock, and is therefore aligned also to the r ising edge of the 35.328 MHz
clock.
7WCLK is drawn as a 1/16 duty cycle clock for convenience. However, it is
implemented as a 50% duty cycle clock. So, the interpretation is that the start of the
16-bit RX data frame is indicated by the simultaneous r ising edges of MCLK and WCLK.
There is one WCLK rising edge for each ADC word.
8MCLK is the master clock input to the AFE and is always at 35.328 MHz. This clock is
immediately divided down to 17.664 MHz. The diagram also shows the internally
generated 17.664 MHz clock. Data is transmitted from the AFE on the rising edge of the
17.664 MHz and sampled by the AFE on the falling edge of the 17.664 MHz clock.
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9It is understood that the DSP samples the RX data on the falling edge of a 17.664 MHz
clock (generated presumably inside the DSP). This allows the RX data from the AFE to
have more delay than if they were sampled by the falling edge of the 35.328 MHz clock.
10 WCLK and MCLK are common between all the channels . Thus, the entire digital interface
f or the N receiv e and N transmit channels is implemented using 3N data lines , 1 clock line
(MCLK), and 1 frame-sync / start-of-word signal (WCLK).
11 The state of the interface after power-on is undefined: the interface resets itself on the
next 16-bit frame (i.e., the first complete frame) following power-on.
12 There is no tristate control on the outputs.
13 The chip does not support an incoming TX data rate of 1.1 MHz (f or a G.lite TX running at
Nyquist).
14 With respect to electrical levels, the AFE digital inputs are both 3.3V CMOS and TTL
compatible, and the HIGH level on the ADC outputs is set by the power supply voltage
VDD_ADIO. It will always be possible to set the digital output HIGH level to a separate
voltage. With respect to the threshold or trigger level for digital inputs to the AFE,
DataPath guarantees that they operate correctly with a HIGH level of 2.5 V.
15 In practice, because of variable propagation delays on a PCB etc., the DSP cannot wait
for the rising edge of WCLK to send out the TX data — it needs to recogniz e ahead of
time and send out the data in advance — for example 1/2 clock earlier.
16 Both 2’s complement and offset binar y for mats are available independently for the RX
data and the TX data. However, all RX channels must use the same for mat, and all TX
channels must use the same format.
17 All of the above modes, sample rates etc. are controlled by on-chip control registers,
accessible thru the 4-wire serial control por t. The details of these registers will be
described in the relevant product Advance Data Sheet.
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A timing diagram for the AFE interface with 1.104 MS/s ADC’s is shown below.
Fig. 1 Detailed RX/TX sequence for digital interface in N-channel ATU-C AFE (M = N–1).
(Internal)
WCLK
(17.664 MHz) ...
56.6 ns
...
...
...
...
...
...
...
RX0
TX0[1]
TX0[0]
RXM
TXM[2]
TXM[0]
DA0[15]
DA0[7]
AD0[0]
DA0[13]
DA0[5]
DA0[14]
DA0[6]
AD0[13]
DA0[15]
DA0[7]
AD0[7]
One 16-bit ADC sample
Two 16-bit DAC words
DA0[8]
DA0[0]
AD0[8]
DA0[9]
DA0[1]
AD0[9]
DA0[8]
DA0[0]
AD0[15] AD0[14]
DA0[14]
DA0[6]
AD0[14]
DA0[15]
DA0[7]
AD0[15]
DAM[15]
DAM[7]
ADM[0]
DAM[13]
DAM[5]
DAM[14]
DAM[6]
ADM[13]
DAM[15]
DAM[7]
ADM[7]
DAM[8]
DAM[0]
ADM[8]
DAM[9]
DAM[1]
ADM[9]
DAM[8]
DAM[0]
ADM[15] ADM[14]
DAM[14]
DAM[6]
ADM[14]
DAM[15]
DAM[7]
ADM[15]
MCLK
(35.328 MHz)
...
...
...
...
...
...
...
...
......
First DAC word Second DAC word
Falling edge location
not critical.
(1.104 MHz)
...... ...
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A timing diagram for the AFE interface with 552 kS/s ADC’s is shown below.
Fig. 2 Detailed RX/TX sequence for digital interface in N-channel ATU-C AFE (M = N – 1).
(Internal)
WCLK
(17.664 MHz) ...
56.6 ns
...
...
...
...
RX0
TX0[1]
TX0[0]
RXM
TXM[2]
TXM[0]
DA0[15]
DA0[7]
AD0[0]
DA0[14]
DA0[6]
AD0[14]
DA0[15]
DA0[7]
One 16-bit ADC sample
Four 16-bit DAC words
DA0[8]
DA0[0]
DA0[9]
DA0[1]
DA0[8]
DA0[0]
AD0[15]
DA0[14]
DA0[6]
DA0[15]
DA0[7]
MCLK
(35.328 MHz)
...
...
...
...
...
...
First DAC word Fourth DAC word
Falling edge location
not critical.
(552 kHz)
...... ...
AD0[15]
...
...
...
DAM[15]
DAM[7]
ADM[0]
DAM[14]
DAM[6]
ADM[14]
DAM[15]
DAM[7]
DAM[8]
DAM[0]
DAM[9]
DAM[1]
DAM[8]
DAM[0]
ADM[15]
DAM[14]
DAM[6]
DAM[15]
DAM[7]
...
...
...
...
ADM[15]
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The following are the detailed timing specifications for the various digital interfaces.
RX Output Timing
Fig. 3 RX Output timing. Conditions: load capacitance = 20 pF, VOH = 3.3 V
Parameter Symbol Min Typ Max Units
MCLK high to Data Valid TD1 15 ns
MCLK/2
RXi
TD1
MCLK
WCLK
(Internal)
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TX Input Timing
Fig. 4 TX input timing. Conditions: load capacitance = 20 pF, VOH = 3.3 V
Parameter Symbol Min Typ Max Units
TX inputs setup time TSU1 7 10 14 ns
TX inputs hold time TH1 7 10 14 ns
DAC
Inputs
TSU1 TH1
TXi[1:0]
MCLK/2
MCLK
(Internal)
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4.2 Serial Port Interface
4.2.0 Introduction
The serial por t interface controls the read/write to the registers on the chip. The interface
consists of an active-low enable input pin (S_EN), a serial clock input pin (S_CLK), a data input
pin (S_DIN) and a data output pin (S_DOUT). The timing diagram of the operation of the serial
port is shown in Fig. 5. After S_EN is asserted, chip-select (CS), serial port register address
(A5-A0) and read/write control bit (R/W) are serially clocked in at the rising edge of S_CLK.
☞Note that in order to allow for future register address space expansion, this scheme
uses a 6-bit register address, different from all previous DataPath ADSL AFE’s, which
used a 5-bit address.
For a write operation (R/W=1), the addressed register is updated upon receiving the 16-bit data
(D15-D0). For a read operation ( R/W=0), the 16-bit contents of the addressed register is
sequentially shifted out at the S_DOUT pin at the f alling edge of S_CLK. As shown in Fig. 5,
S_DOUT is driven only when data are being read. Otherwise, it is tristated. Note: in this
implementation, chip select (CS) is tied to GND internall y on chip, and so should always
be LOW in real usage. Apart from the CS issue, and the 6-bit address format, this interface
is identical to that present on the existing DPS8000 and DPS8001 family of products.
4.2.1 Serial Port Timing
The timing diagram for the serial port is shown in Fig. 5.
Fig. 5 Timing diagram for the serial port
CS A5 A4 A3 A2 A1 A0 R/W D15 D14 D13 D12 D4 D3 D2 D1 D0
D15 D14 D13 D12 D4 D3 D2 D1 D0
S_EN
S_CLK
S_DIN
S_DOUT
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4.2.2 Serial Port
a. Conditions: load capacitance = 30 pF, VOH = 5.0 V
Parameter Symbol Min Typ Max Units
S_CLK clock period TCYC 100 125 ns
S_CLK high time TPWH 50 ns
S_CLK low time TPWL 50 ns
S_EN low to S_CLK high TSU1 30 ns
S_CLK high to S_EN high TH1 15 ns
S_EN inactive pulse width TPW 100 ns
S_DIN setup time TSU2 15 ns
S_DIN hold time TH2 15 ns
S_CLK low to S_DOUT delay TD3 30ans
S_EN inactive to S_DOUT HiZ TD4 30 ns
CS A5 A4 A3 A2 A1 A0 R/W D15 D14 D13 D12 D4 D3 D2 D1 D0
D15 D14 D13 D12 D4 D3 D2 D1 D0
S_EN
S_CLK
S_DIN
S_DOUT
TSU1 TPWL TPWH
TCYC
TSU2
TH2
TH1
TPW
TD3 TD4
