CMOS STATIC RAM IDT71256S 256K (32K x 8-BIT) IDT71256L Integrated Device Technology, Inc. FEATURES: High-speed address/chip select time DESCRIPTION: Military: 25/30/35/45/55/70/85/100/1 20/1 50ns (max.) Commercial: 20/25/35/45ns (max.) Low Power only. Low-power operation Battery Backup operation 2V data retention Produced with advanced high-perfdrmance CMOS technology Input and output directly TTL-compatible Available in standard 28-pin (300 or 600 mil) ceramic DIP, 28-pin (600 mil) plastic DIP, 28-pin (300 mil) SOJ and 32-pin LCC Military product compliant to MIL-STD-883, Class B The IDT71256 is a 262,144-bit high-speed static RAM organized as 32K x 8. It is fabricated using |DTs high- performance, high-reliability CMOS technology. Address access times as fast as 20ns are available with power consumption of only 350mW (typ.). The circuit also offers a reduced power standby mode. When CS goes HIGH, the circuit will automatically go to, and remain in, a low-power standby mode as long as CSremains HIGH. In the full standby mode, the low-power device consumes less than 15uW, typically. This capability provides significant system level power and cooling savings. The low-power (L) version also offers a battery backup data retention capability where the circuit typically consumes only 5uW when operating off a 2V battery. The IDT71256 is packaged in a 28-pin (300 or 600 mil) ceramic DIP, a 28-pin 300 mil J-bend SOIC, and a 28-pin (600 mil) plastic DIP, and 32-pin LCC providing high board-levei packing densities. The IDT71256 military RAM is manufactured in compliance with the latest revision of MiL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. FUNCTIONAL BLOCK DIAGRAM Ao ADDRESS DECODER At4 VOo INPUT DATA CIRCUIT VO7 CONTROL CIRCUIT The IDT loge is a registered trademark of Integrated Device Technology, Inc. Vcc GND 262,144 BIT MEMORY ARRAY YO CONTROL 2946 drw 01 MILITARY AND COMMERCIAL TEMPERATURE RANGES AUGUST 1996 1996 Integrated Device Technology, Inc. DSC-2946/7 7.2 11DT71256 S/L CMOS STATIC RAM 256K (32K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATIONS aad whee TRUTH TABLE ae 4 2 27 H WE WE cs OE vO Function 7 L}3 2 At Ae Cla oH As x H x | High-z| Standby (Isp) As C5 28-1 24 FD Ag x Vic x High-Z] Standby (ise1) M6 pog3 23 PAu H H | High-z] Oo: AsG7 pow, 2 FOE igh- utput Disabled Ag ; 8 S028-5 21 T) Ato H L Dout Read Data n 4 0 20 SO. L X Din_| Write Data 0 19 7 NOTE: 2946 tbl 02 vO. 4 2 \ at 1. H= Vin, L = Vit, X = Don't Care VOe2 (13 16 FVvO4 GND [14 15 [VO 3 2946 drw 02 DIP/SOJ ABSOLUTE MAXIMUM RATINGS) TOP VIEW Symbol Rating Com'l. Mil. Unit VieRM | Terminal Voltage |-0.5 to +7.0] -0.5to+7.0] V with Respect to GND TA Operatin Oto+70 | -55to+125 | C 8H 8 2 Pp 19 INDEX 229 gis < Temperature vA V3 piian x Teas =| Temperature = | -55 to +125 | -65 to +135 | C As As Under Bias AS Ag TsT Storage -55 to +125 | -65 to +150 | C No Temperature 3 Ao OE Pr Power Dissipation 1.0 1.0 Ww Al Ato louT DC Output 50 mA Ne lor Current Oo VO6 NOTE: 2946 tbi 03 16 17 18 19 20 1. Stresses greater than those listed under ABSOLUTE MAXIMUM mANnMOoMMN RATINGS may cause permanent damage to the device. This is a stress Tra OO +H rating only and functional operation of the device at these or any other 990 5 zoo Q 2946 dew 03 conditions above those indicated in the operational sections of this ~~ ~~ specification is not implied. Exposure to absolute maximum rating con- ditions for extended periods may affect reliability. 32-Pin LCC TOP VIEW PIN DESCRIPTIONS N Descriou CAPACITANCE (Ta = +25C, f = 1.0MHz) lame escription ADA Add P Symbol Parameter'") Conditions | Max.| Unit 0-A14 resses VOo_VOy Data InputOutut CIN Input Capacitance VIN = OV 8 pF 1o| ata utpul ts Chi ca ' P Cvo VO Capacitance VouT = 0V 8 pF ip Selec NOTE: 2046 tl 04 WE Write Enable 1. This parameter is determined by device characterization, but is not OE Output Enable production tested. GND Ground vec Power 2946 thi 01 7.2IDT71256S/L CMOS STATIC RAM 256K (32K x 8-BIT) RECOMMENDED OPERATING MILITARY AND COMMERCIAL TEMPERATURE RANGES RECOMMENDED DC OPERATING TEMPERATURE AND SUPPLY VOLTAGE CONDITIONS Grade Temperature GND Vee Symbol Parameter Min. | Typ. | Max. | Unit Military -55C to +125C ov 5.0V + 10% Vec Supply Voltage 45 [50] 55] V Commercial 0C to +70C ov 5.0V+10% GND Supply Voltage 0 0 0 Vv 2946 tbl 05 Vik Input High Voltage 2.2 _ 6.0 Vv VIL Input Low Voltage 0.5 | 0.8 v NOTE: 2946 tb! 06 1. Vit (min.) = 3.0V for pulse width less than 20ns, once per cycle. DC ELECTRICAL CHARACTERISTICS" ) (Vcc = 5.0V + 10%, Vic = 0.2V, VHC = Vcc - 0.2V) 71256S/L20 | 71256S/L25 | 71256S/L30 71256S/L35 Symboi Parameter Power |Coml. | Mil. |Coml.| Mil. |ComL| Mil. | Coml| Mil. | Unit Icc Dynamic Operating Current Ss _ _ 150 _- 145 _ 140 | mA CS < Vit, Outputs Open Vcc = Max., f = fmax!?) L 1385 | | 15 | 130 | | 125 | 105 | 120 Iss Standby Power Supply _ _ _ 20 _ 20 _ 20 mA Current (TTL Level) CS 2 Vin, Voc = Max., L 3 3 3 _ 3 3 3 Outputs Open, f = fMax?? IsB1 Full Standby Power Supply Ss = _ 20 _ 20 _ 20 mA Current (CMOS Level) CS 2 VHc, Vec = Max., f= 0 L 0.4 _ 0.4 1.5 _ 1.5 0.4 15 71256S/L45 | 71256S/L55 | 71256S/L70 | 71256S/L85|71256S/L100) Symbol Parameter Power | Com'l.| Mil. |Com!.| Mil. |Com'l.| Mil. | Coml.| Mil. [Com'l.! Mil. jUnit (cc Dynamic Operating Current $s 1135 _ 135 _ 135 _~ 135 _ 135 [mA CS < VIL, Outputs Open Vec = Max., f = fax) L oo fis] | 115 | | 115] | ais] | 115 \sB Standby Power Supply Ss | 20 _ 20 _ 20 _ 20 _ 20 mA Current (TTL Level) CS 2 Vir, Voc = Max., L 3 3 _ 3 _ 3 _ 3 _ 3 Outputs Open, f = fmax!) IsBi Full Standby Power Supply Ss _ 20 _ 20 _ 20 _ 20 20 mA Current (CMOS Level) CS 2 Vuc, Vcc = Max., f = 0 L 0.4 11.5 _ 1.5 _ 1.5 _ 1.5 _ 1.5 NOTES: 2948 tbl 07 1. All values are maximum guaranteed values. 2. fMax = 1/trc, all address inputs cycling at fmax; f = 0 means no address pins are cycling. 3. Also available: 120 and 150 ns military devices. 7.2IDT71256 S/L CMOS STATIC RAM 256K (32K x 8-BIT} AC TEST CONDITIONS Input Pulse Leveis GND to 3.0V Input Rise/Fall Times 5ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V AC Test Load See Figures 1 and 2 2946 tbl 08 5V 4802 DATAOUT 2550 30pF* 2946 drw 04 Figure 1. AC Test Load Includes scope and jig capacitances DC ELECTRICAL CHARACTERISTICS Voc = 5.0V + 10% MILITARY AND COMMERCIAL TEMPERATURE RANGES 5V 480Q DATAouT 255Q 5pF* 2946 drw 05 Figure 2. AC Test Load (for tciz, touz, tcnz, tonz, tow, twHz)} 1DT71256S IDT71256L Symbol Parameter Test Condition Min. | Typ. | Max. | Min. | Typ. | Max. | Unit tL Input Leakage Current Vcc = Max., MIL. _ _ 10 _ _ 5 pA VIN = GND to Vec COM'L.| _ 5 ~ _ 2 lILol Output Leakage Current] Vcc = Max., CS = Vin, MIL. ~ _ 10 _ _ 5 HA VouT = GND to Vcc COML.| _ 5 ~ _ 2 VoL Output Low Voltage loL = 8mA, Vcc = Min. _ 0.4 _~ _ 0.4 Vv lo. = 10mA, Vcc = Min. _ _ 0.5 _ _ 0.5 VoH Output High Voltage loH = 4mA, Vcc = Min. 2.4 _ _ 2.4 _ _ v 2946 tbl 09 DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES (L Version Only) Vic = 0.2V, VHC = Vcc 0.2V Typ. 7 Max. Vec @ Vcc @ Symbol Parameter Test Condition Min. 2.0v 3.0V 2.0V 3.0V Unit VoR Vcc for Data Retention 2.0 - _ _ _ Vv IccDR Data Retention Current MIL. _ _ _ 500 800 HA COML. _ _ _ 120 200 tCDR Chip Deselect to Data CS 2 Vic 0 _ - ns Retention Time tr) Operation Recovery Time tro) > _ _ _ ns NOTES: 2946 tol 10 1. Ta= +26C. 2. tac = Read Cycle Time. 3. This parameter is guaranteed, but not tested. 7.2 4IDT71256S/L CMOS STATIC RAM 256K (32K x 8-BIT)} LOW Vcc DATA RETENTION WAVEFORM DATA [*- RETENTION UN MODE Vcc 4.5V X 7 4.5V tcpR /*+> VDR22V <+ tr 2946 drw 06 AC ELECTRICAL CHARACTERISTICS (Vcc = 5.0V + 10%, All Temperature Ranges) MILITARY AND COMMERCIAL TEMPERATURE RANGES 71256825 | 7125630 | 71256935 71256845 71256L20 | 71256L25 | 71256L30@ | 71256L35 71256L45 Symbol Parameter Min. | Max. Min.| Max.| Min. | Max.| Min. | Max. } Min.| Max. | Unit Read Cycle tac Read Cycle Time 20 - 2]; 30 35 _ 45 | | ns tAA Address Access Time _ 20 25 _ 30 ~ 35 _ 45 | ns tacs Chip Select Access Time _ 20 25 _ 30 35 _ 45 | ns tc.z) | Chip Select to Output in Low-Z 5 _ 5] 5 _~ 5 _ 5 | | ns tcHz | Chip Deselect to Output in High-Z _ 10 / 1 pB) 15 |} 20 | ns tOE Output Enable to Output Valid _ 10 _ 11 _ 13 ~ 15 | 20 | ns toz?) | Output Enable to Output in Low-Z 2 2] 2 _~ 2 _ o} {ons tonz | Output Disable to Output in High-Z 2 8 2] 10 2 12 2 15 j} 20 | ns tOH Output Hold from Address Change 5 _ 5 _ 5 ~ 5 _ 5 | ns Write Cycle twe Write Cycle Time 20 _ 2a) 30 _ 35 45 | | ns tow Chip Select to End-of-Write 15 _ 20 _ 25 30 40 | ns taw Address Valid to End-of-Write 16 _ 20] 25 ~ 30 40] | ns TAS Address Set-up Time 0 _ 0 _ 0 _ 0 ~ 0 | ns twP Write Pulse Width 15 _ 20]; 25 ~ 30 _ 35 | | ns twa Write Recovery Time 0 _ 0 - 0 _ 0 ~ 0 -- | ons {pw Data to Write Time Overlap 1 _ 13 _ 14 _ 15 20 | ns twuz) | Write Enable to Output in High-Z | 10 | 4 | 156] ~ | 15 | 20 |] ns tDH Data Hold from Write Time 0 _ 0 _ 0 _ 0 _ | ns tow?) | Output Active from End-of-Write 5 _ 5| 5 _~ 5 | ns NOTES: 2946 tb! 11 1. 0 to +70C temperature range only. 2. This parameter guaranteed by device characterization, but is not production tested. 3. ~55 to +125C temperature range only. 7.2IDT71256 S/L CMOS STATIC RAM 256K (32K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS (Vcc = 5.0V + 10%, All Temperature Ranges) 71256865" | 71256870) 71256885" | 7125610007) 71256L55() 71256L70") 71256L85" | 712561000 Symbol Parameter Min. | Max. | Min. | Max. | Min. [Max. | Min. | Max. | Unit Read Cycle {RC Read Cycle Time 55 _ 70 _ 85 _ 100 _ ns tAA Address Access Time _ 55 _ 70 _ 85 100 ns tacs Chip Select Access Time _ 55 _ 70 _ 85 _ 100 ns tc.z) | Chip Deselect to Output in Low-Z 5 = 5 _ 5 5 _ ns tcHz) | Output Enable to Output in Low-Z _ 25 30 35 40 ns fOE Output Enable to Output Valid _ 25 ~ 30 _ 35 _ 40 ns to.z | Output Enable to Output in Low-Z 0 _ 0 = 0 _ 0 _ ns toHz) | Output Disable to Output in High-Z 0 25 0 30 = 35 40 ns tOH Output Hold from Address Change 5 _ 5 _ 5 _ 5 _ ns Write Cycle twe Write Cycle Time 55 _ 70 _ 85 _ 100 _ ns icw Chip Select to End-of-Write 50 _ 60 _ 70 _ 80 _ ns taw Address Valid to End-of-Write 50 _ 60 _ 70 _ 80 _ ns tas Address Set-up Time 0 _ 0 _ 0 _ 0 _ ns twp Write Pulse Width 40 _ 45 _ 50 _ 55 _ ns twR Write Recovery Time 0 > 0 _ 0 _ 0 _ ns tpw Data to Write Time Overlap 25 _ 30 _ 35 _ 40 _ ns tbH Data Hold from Write Time (WE) 0 _ 0 = 0 = 0 = ns twHz) | Write Enable to Output in High-Z 25 30 _ 35 _ 40 ns tow | Output Active from End-of-Write 5 _ 5 5 5 _ ns NOTES: 2946 tbl 11 1. -55C to +125C temperature range only. 2. This parameter guaranteed by device characterization, but is not production tested. 3. Also available: 120 and 150 ns military devices. 7.2 6IDT71256S/L CMOS STATIC RAM 256K (32K x 8-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF READ CYCLE NO. 1") | tre | ADDRESS DATA out 2946 drw 07 TIMING WAVEFORM OF READ CYCLE NO. 2": 2: 4) tac 1 ADDRESS y i TAA __ J toH >| tOH DATA out 2946 drw OB TIMING WAVEFORM OF READ CYCLE NO. 3 3 4) wc cs kK tcLz oO | tcnz (5) DATA ouT 2946 drw 09 NOTES: . WEis HIGH for Read cycle. . Device is continuously selected, CS is LOW. . Address valid prior to or coincident with CS transition LOW. . OEis Low. . Transition is measured +200mV from steady state. obon 7.2 710771256 S/L. CMOS STATIC RAM 256K (32K x 8-BIT} MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED TIMING)": 2 3-5: 7) Leg two > ADDRESS x tonz (Lp| OE + taw y_- cs 7 tas te twe > twr >| WE ri (6__ tWwHz a tow DATA out ~~ (4) (4) _ tow a tOH DATA IN 2946 dw 10 TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED TIMING)": 2: 3: 5) ~ two | ADDRESS W taw cs * H i tasrfae tow Phe tWR tow toH2 DATA IN p______ 2946 drw 11 NOTES: . WE or CS must be HIGH during all address transitions. . Awrite occurs during the overlap of a LOW CS and a LOW WE. . twr is measured from the earlier of CS or WE going HIGH to the end of the write cycle. . During this period, 1/O pins are in the output state so that the input signals must not be applied. . If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. . Transition is measured +200mV from steady state. . if OEis LOW during a WE controlled write cycle, the write pulse width must be the larger of twr or (twHz + tow) to allow the I/O drivers to turn off and data to be placed on the bus for the required tow. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the spectified twe. For a CS controlled write cycle, OE may be LOW with no degradation to tcw. NOOO h GM = 7.2 8IDT71256S/L. CMOS STATIC RAM 256K (32K x 8-BIT) ORDERING INFORMATION {DT 71256 Xx XXX XXX Xx Device Power Speed Package Process/ Type Temperature Range || MILITARY AND COMMERCIAL TEMPERATURE RANGES Blank B TO Commercial (0C to +70C) Military (-S5C to +125C) Compliant to MIL-STD-883, Class B 300 mil CERDIP (D28-3) 600 mil CERDIP (D28-1) 300 mil SOJ (SO28-5) 600 mil Plastic DIP (P28-1) Leadiess Chip Carrier (32-pin) (L32-1) Commercial Only Military Only Military Only Military Only Military Only Military Only Military Only Military Only Speed in nanoseconds Standard Power Low Power 2946 drw 12 7.2