PRELIMINARY
32K x 8 Static RAM
CY62256V
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05057 Rev. ** Revised August 31, 2001
56V
Features
• Low voltage range :
—2.7V − 3.6V (62256V)
—2.3V − 2.7V (62256V25)
—1.6V − 2.0V (62256V18)
•Low active power and standby power
•Easy memory expansion with CE and OE features
•TTL-compatible inputs and outputs
•Automatic power-down when deselected
•CMOS for optimum speed/power
Functional Description
The CY6 2256V family is composed of three high-perf ormance
CMOS static RAM’s organized as 32,768 words by 8 bits. Easy
memory ex pan si on i s pro vi ded by an ac tiv e L OW chi p en able
(CE) and ac tive LOW ou tput enabl e (OE) and three-state driv-
ers. These devices have an automatic power-down feature,
reducin g the po wer con sumpt ion b y over 99% w hen dese lect-
ed. The CY62256V family is available in the standard
450-mil-wide (300-mil body width) SOIC, TSOP, and reverse
TSOP packages.
An active LOW write enable signal (WE) controls the writ-
ing/reading operation of the memory . When CE and WE inputs
are both LOW, data on the eight data input/output pins (I/O0
through I/O 7) is writt en into the memory loc ation addressed b y
the address present on the address pins (A0 through A14).
Reading the device is accomplished by selecting the device
and enabling the outputs, CE and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the con-
tents of the location addressed by the information on address
pins are present on the eight data input/output pins.
The inpu t/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.
A9
A8
A7
A6
A5
A4
A3
A2
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUTBUFFER
POWER
DOWN
WE
OE
I/O0
CE
I/O1
I/O2
I/O3
1
2
3
4
5
6
7
8
9
10
11
14 15
16
20
19
18
17
21
24
23
22
Top View
SOIC
12
13
25
28
27
26
GND
A6
A7
A8
A9
A10
A11
A12
A13
WE
VCC
A4
A3
A2
A1
I/O7
I/O6
I/O5
I/O4
A14
A5
I/O0
I/O1
I/O2
CE
OE
A0
I/O3
512x512
ARRA
Y
I/O7
I/O6
I/O5
I/O4
A10
A
13
A
11
A
12
A
A
14
C62256V–1
C62256V–2
A
1
0
22
23
24
25
26
27
28
1
2
510
11
15
14
13
12
16
19
18
17
3
4
20
21
7
68
9
OE
A1
A2
A3
A4
WE
VCC
A5
A6
A7
A8
A9
A0
CE
I/O7
I/O6
I/O5
GND
I/O2
I/O1
I/O4
I/O0
A14
A10
A11 A13
A12
C62256V–3
I/O3
22
23
24
25
26
27
28
1
2
510
11
15
14
13
12
16
19
18
17
3
4
20
21
7
68
9
OE
A1
A2
A3
A4
WE
VCC
A5
A6
A7
A8
A9
A0
CE
I/O7
I/O6
I/O5
GND
I/O2
I/O1
I/O4
I/O0
A14
A10
A11 A13
A12
C62256V–4
I/O3
TSOP I
Top View
(not to scale)
TSOP I
Top View
(not to scale)
Reverse Pinout
LogicBlockDiagram Pin Configurations
CY62256V
PRELIMINARY
Document #: 38-05057 Rev. ** Page 2 of 13
Maximum Ratings
(Above w hi ch the usef ul l ife m ay be impai red. For user g uid e-
lines, not tes ted .)
Storage Temperature .....................................−65°C to +150°C
Ambient Temperature with
Power Applied...................................................0°C to +70°C
Supply Voltage to Ground Potential
(Pin 28 to Pin 14).................................................−0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z Stat e[1] .......................................−0.5V to VCC + 0.5V
DC Input Voltage[1]....................................−0.5V to VCC + 0.5V
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage.......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Operating Range
Range Ambient Temperature VCC
Commercial 0°C to +70°C 1.6V to 3.6V
Industrial −40°C to +85°C 1.6V to 3.6V
Note:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
Product Portfolio
Product VCC Range Speed
Power Dissipation (LL Devices)
Operating (ICC)Standby (ISB2)
Min. Typ. Max. Typical Maximum Typical Maximum
CY62256V 2.7V 3.0 3.6V 70 ns 11 mA 30 mA 0.1 µA5 µA
CY62256V25 2.3V 2.5V 2.7V 100 ns 9 mA 15 mA 0.1 µA4 µA
CY62256V18 1.6V 1.8V 2.0V 200 ns 5 mA 10 mA 0.1 µA3 µA
Electrical Characteristics Over the Op erat ing Ran ge
Test Conditions
CY62256V-70
Parameter Description Min. Typ.[2] Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = −1.0 mA 2.4 V
VOL Output LOW Voltage VCC = Min., IOL = 2.1 mA 0.4 V
VIH Input HIGH Voltage 2.2 VCC
+0.3V V
VIL Input LOW Voltage −0.5 0.8 V
IIX Input Load Current GND < VI < VCC −1+1 µA
IOZ Output Leakage Current GND < VO < VCC, Output Disabled −1+1 µA
ICC VCC Operating Supply
Current VCC = Max. , IOUT = 0 mA,
f = fMAX = 1/tRC Com’lStd/L
/LL 11 30 mA
ISB1 Automatic CE Power-Down
Current— TTL Inputs Max. VCC, CE > VIH, VIN > VIH
or V IN < VIL, f = fMAX Com’lStd/L
/LL 100 300 µA
ISB2 Automatic CE
Power-Down Current—
CMOS Inputs
Max. VCC, CE > VCC – 0.3V
VIN > VCC – 0.3V or VIN < 0.3V,
f = 0
Com’lStd/ L 0.1 50 µA
LL 5µA
Ind’lLL 10 µA
Electrical Characteristics Over the Op erat ing Ran ge
CY62256V25-100
Parameter Description Test Conditions Min. Typ.[2] Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = −0.1 mA 2 V
VOL Output LO W Voltage VCC = Min., IOL = 0.1 mA 0.4 V
VIH Input HIGH Voltage 1.7 Vcc +
0.3V V
VIL Input LOW Voltage −0.3 0.7 V
IIX Input Lo ad Current GND < VI < VCC −1+1 µA
CY62256V
PRELIMINARY
Document #: 38-05057 Rev. ** Page 3 of 13
IOZ Output Leakage Cur-
rent GND < VO < VCC, Output Disabled −1+1 µA
ICC VCC Operating Supply
Current VCC = Max. , IOUT = 0 mA,
f = fMAX = 1/tRC Com’lStnd/L
/LL 14 23 mA
ISB1 Automatic CE Pow-
er-Down Current—
TTL Inputs
Max. VCC, CE > VIH, VIN > VIH
or VIN < VIL, f = fMAX Com’lStnd/L
/LL 75 225 µA
ISB2 Automatic CE
Power-Down Current
— CMOS Inputs
Max. VCC, CE > V CC − 0.3V
VIN > VCC – 0.3V or VIN < 0.3V,
f = 0
Com’lStnd/L 0.1 40 µA
LL 4µA
Ind’lLL 8µA
Electrical Characteristics Over the Op erat ing Ran ge
CY62256V18-200
Parameter Description Test Conditions Min. Typ.[2] Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = −0.1 mA 0.8*Vcc V
VOL Output LO W Voltage VCC = Min., IOL = 0.1 mA 0.2 V
VIH Input HIGH Voltage 0.7*Vcc VCC
+0.3V V
VIL Input LOW Voltage −0.5 0.2*Vcc V
IIX Input Lo ad Current GND < VI < VCC −1+1 µA
IOZ Output Leakage
Current GND < VO < VCC, Output Disabled −1+1 µA
ICC VCC Operating Supply
Current VCC = Max., IOUT = 0 mA,
f = fMAX = 1/tRC Com’lStnd/L
/LL 10 17 mA
ISB1 Automatic CE Pow-
er-Down Current— TTL
Inputs
Max. VCC, CE > VIH,
VIN > VIH or VIN < VIL, f = fMAX Com’lStnd/L
/LL 56 165 µA
ISB2 Automatic CE
Power-Down Current—
CMOS Inputs
Max. VCC, CE > VCC – 0.3V
VIN > VCC – 0.3V or VIN < 0.3V ,
f = 0
Com’lStnd/L 0.1 30 µA
LL 3µA
Ind’lLL 6µA
Electrical Characteristics Over the Op erat ing Ran ge (con tin ued)
CY62256V25-100
Parameter Description Test Conditions Min. Typ.[2] Max. Unit
Capacitance[3]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VCC = 3.0 V 6pF
COUT Output Capacitance 8pF
Notes:
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = Vcc T yp., TA = 25°C, and tAA=70ns.
3. Tested initially and after any design or process changes that may affect these parameters.
CY62256V
PRELIMINARY
Document #: 38-05057 Rev. ** Page 4 of 13
AC Test Loads and W aveforms
Vcc
Vcc
OUTPUT
R2
50 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10% 90%
10%
<5ns <5ns
OUTPUT Vth
Equivalent to:THÉ VENIN EQUIVALENT
ALL INPUT PULSES
C62256V–5C62256V–6
R1
Rth
AC Test Load
Vcc 3.3 V 2.5V 1.8V
R1 1103 16.6K 13.6K
R2 1554 15.4K 11.4K
RTH 645 8K 6.2K
VTH 1.75V 1.2V 0.82V
Data Retention Characteristics (Over the Operating Range)
Parameter Description Conditions[4] Min. Typ.[2] Max. Unit
VDR VCC for Da ta Retentio n 1.4 V
ICCDR Data Retention Current Coml Stnd/L VCC = 1.6
CE > VCC – 0.3V ,
VIN > VCC – 0.3V or
VIN < 0.3V 0.1
30 uA
LL 3uA
Ind. LL 6uA
tCDR[3] Chip Deselect to Data
Retention Time 0ns
tR[3] Operation Recovery Time tRC ns
Data Retention Waveform
C62256V–7
1.8V1.8V
tCDR
VDR >1.4V
DATA RETENTION MODE
tR
CE
VCC
CY62256V
PRELIMINARY
Document #: 38-05057 Rev. ** Page 5 of 13
Switching Characteristics Over the Operating Range[5]
CY62256V-70 CY62256V25-100 CY62256V18-200
Parameter Description Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC Read Cycle Time 70 100 200 ns
tAA Address to Data Valid 70 100 200 ns
tOHA Dat a Hold from Addres s Cha nge 10 10 10 ns
tACE CE LOW to Data Valid 70 100 200 ns
tDOE OE LOW to Data Valid 35 75 125 ns
tLZOE OE LOW to Low Z[6] 5 5 10 ns
tHZOE OE HIGH to High Z[6, 7 ] 25 50 75 ns
tLZCE CE LOW to Low Z[6] 10 10 10 ns
tHZCE CE HIGH to High Z[6, 7] 25 50 75 ns
tPU CE LOW to Power-Up 000ns
tPD CE HIGH to Power-Down 70 100 200 ns
WRITE CYCLE[8,9]
tWC Write Cycle Time 70 100 200 ns
tSCE CE LOW to Write End 60 90 180 ns
tAW Address Set-Up to W rit e End 60 90 180 ns
tHA Address Hold from Write End 000ns
tSA Address Set-Up to W rit e Start 000ns
tPWE WE Pulse Width 50 80 160 ns
tSD Data Set-Up to Write End 30 60 100 ns
tHD Data Hold from Write End 000ns
tHZWE WE LOW to High Z[6, 7] 25 50 100 ns
tLZWE WE HIGH to Low Z[6] 10 10 10 ns
Switching Waveforms
Notes:
4. No input may exceed VCC+0.3V.
5. Test conditions assume signal transition time of 5 ns or less timing reference levels of Vcc/2, input pulse levels of 0 to Vcc, and output loading of the specified
IOL/IOH and 100-p F load capacit ance.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less t han tLZOE, and tHZWE is less than tLZWE for any given de vice .
7. tHZOE, tHZCE, a nd tHZWE are specif ied with CL = 5 pF as in part (b) of AC Test Loads. T ransi tion is measure d ±200 mV from steady-stat e voltage.
8. The internal write time of the memory is defined by the overlap of C E LO W and WE L OW . Both signals must be LOW to initiate a write and eit her signal can terminate
a write by going HIGH. The dat a inp ut se t-up an d hold t iming should be refe renced to th e risin g edge of th e signal that te rmina t es the write.
9. The minimum write cycle time for write cycle #3 (WE controlled , OE LOW) is t he su m of t HZWE and tSD.
10. Device is continuously selected. OE, CE = VIL.
11. WE is HIGH for read cyc le.
Read Cycle No. 1
ADDRESS
DATA OUT PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
C62256V–8
[10, 11]
[10, 11]
CY62256V
PRELIMINARY
Document #: 38-05057 Rev. ** Page 6 of 13
Notes:
12. Address valid prior to or coincident with CE transition L OW .
13. Data I/O is high impedance if O E = VIH.
14. If CE goe s HIGH simulta neously wi th WE HIGH, th e outpu t remai ns in a high -impeda nce stat e.
15. During this period, the I/Os are in output state and input signals should not be applied.
Switching Waveforms (continued)
Read Cycle No. 2
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
DATA OUT HIGH IMPEDANCE IMPEDANCE
ICC
ISB
tHZOE
tHZCE
tPD
OE
CE
HIGH
VCC
SUPPLY
CURRENT
C62256V–9
[11, 12]
Write Cycle No.1(WE Controlled)
tHD
tSD
tPWE
tSA
tHA
tAW
tWC
DATA I/O
ADDRESS
CE
WE
OE
tHZOE C62256V–10
DATAINVALID
[8, 13, 14]
NOTE 15
Write Cycle No. 2 (CEControlled)tWC
tAW
tSA tHA
tHD
tSD
tSCE
WE
DATA I/O
ADDRESS
CE
C62256V–11
DATAINVALID
[8, 13, 14]
CY62256V
PRELIMINARY
Document #: 38-05057 Rev. ** Page 7 of 13
Switching Waveforms (continued)
Write Cycle No. 3 (WEControlled,OELOW)
DATA I/O
ADDRESS
tHD
tSD
tLZWE
tSA
tHA
tAW
tWC
tHZWE C62256V–12
DATAINVALID
[ 9, 14]
NOTE 15
WE
CE
CY62256V
PRELIMINARY
Document #: 38-05057 Rev. ** Page 8 of 13
Typical DC and AC Characteristics
1.6
1.8
1.0
0.6
0.4
0.2
1.6
1.4
1.2
1.0
0.8
−55 25 125
−55 25 125
1.2
1.0
0.8
NORMALIZED t
AA
-14
-12
-10
-8
-6
-4
0.0 1.0 1.5 22.5
OUTPUT SOURCE CURRENT (mA)
SUPPLYVOLTAGE (V)
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
AMBI EN T TEMPERATURE (°C)
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
AMBI EN T TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
0.8
1.5
1.0
0.5
1.65 2.1 2.6 3.1 3.6
NORMALIZED t
SUPPL YVOLTAGE (V)
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
6
4
2
0.0 1.0 2.0 3.0
OUTPUT SINK CURRENT (mA)
0
OUTP UT VO LT AGE (V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
0.6
0.4
0.2
0.0
NORMALIZED I
CC
NORMALIZED I
CC
TA=25°C
0.6
0.0
0
AA
2.5
2.0
TA=25°C
1.4
−55 25 105
2.5
2.0
1.5
CURRENT
vs. AMBIENT TEMPERATURE
AMBIEN T TE MPERATU RE (°C)
1.0
0.5
0.0
-0.5
ISB
3.0
STANDBY
I
SB2
µ
A
Vcc=3.0V
Vcc=2.5V
Vcc=1.8V
V
cc
=2.5V
V
cc
=1.8V
V
cc
=3.3V
1.6
1.8
2.0
2.4
2.8
3.2
3.6
1.4
1.2
Vcc=1.8V
Vcc=3.0V
Vcc=2.5V
0.5
8
10
12
14
TA=25°C
TA=25°C
Vcc=2.5V
Vcc=2.5 V
CY62256V
PRELIMINARY
Document #: 38-05057 Rev. ** Page 9 of 13
Truth Table
CE WE OE Inputs/Outputs Mode Power
H X X High Z Deselect/Power-Down Standby (ISB)
L H L Data Out Read Active (ICC)
L L X Data In Write Active (ICC)
L H H High Z Deselect, Output Disa bled Active (ICC)
Typical DC and AC Characteristics (continued)
1.5
1.0
0.5
0.0 1.0 2.0 3.0
NORMALIZED I
PO
SUPPL YVOLTAGE (V)
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE 30.0
25.0
20.0
15.0
10.0
5.0
0 200 400 600 800
DELT A t (ns)
AA
CAPACITANCE (pF)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING 1.25
1.00
0.75
10 20 30
NORMALIZED I
CC
CYCLE FREQUENCY (MHz)
NORMALIZED ICC vs.CYCLETIME
0.0 4.0 0.0 1000 0.50
TA=25°C
VIN =0.5V
TA=25°C
Vcc =3V
1
Vcc=1.8V
Vcc=3.0V
CY62256V
PRELIMINARY
Document #: 38-05057 Rev. ** Page 10 of 13
Ordering Information
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
70 CY62256V -70SNC S22 28-Lead 450-Mil (300-Mil Body Width) SOIC Commercial
CY62256V L-70SNC
CY62256V LL-70SNC
CY62256V -70ZRC ZR28 28-Lead Reverse Th in Small Outline Package
CY62256V L-70ZRC
CY62256V LL-70ZRC
CY62256V -70ZC Z28 28-Lead Thin Small Outline Package
CY62256V L-70ZC
CY62256V LL-70ZC
CY62256V -70ZI Z28 28-Lead Thin Small Outline Package Industrial
CY62256V L-70ZI
CY62256V LL-70ZI
CY62256V -70SNI S22 28-Lead 450-Mil (300-Mil Body Width) SOIC
CY62256VL -70SNI
CY62256VLL -70SNI
CY62256V -70ZRI ZR28 28-Lead Reverse Thin Small Outline Package
CY62256V L-70ZRI
CY62256V LL-70ZRI
100 CY62256V25-100SNC S22 28-Lead 450-Mil (300-Mil Body Width) SOIC Commercial
CY62256V25L-100SNC
CY62256V25LL-100SNC
CY62256V25-100ZRC ZR28 28-Lead Reverse Thin Small Outline Package
CY62256V25L-100ZRC
CY62256V25LL-100ZRC
CY62256V25-100ZC Z28 28-Lead Thin Small Outline Package
100 CY62256V25L-100ZC Z28 28-Lead Thin Small Outline Package Commercial
CY62256V25LL-100ZC
200 CY62256V18-200SNC S22 28-Lead 450-Mil (300-Mil Body Width) SOIC Commercial
CY62256V18L-200SNC
CY62256V18LL-200SNC
CY62256V18-200ZRC ZR28 28-Lead Reverse Thin Small Outline Package
CY62256V18L-200ZRC
CY62256V18LL-200ZRC
CY62256V18-200ZC Z28 28-Lead Thin Small Outline Package
CY62256V18LL-200ZC
200 CY62256V18L-200ZC Z28 28-Lead Thin Small Outline Package Commercial
Shaded area contains advanced information.
CY62256V
PRELIMINARY
Document #: 38-05057 Rev. ** Page 11 of 13
Package Diagrams
28-Lead 450-Mil (300-Mil Body Width) SOIC S22
28-Lead ReverseThin Small Outline Package ZR28
CY62256V
PRELIMINARY
Document #: 38-05057 Rev. ** Page 12 of 13
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry emb odied in a Cypress Semiconductor product. Nor does it convey or imply any license under paten t or other rights. Cypress Se miconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconducto r products in life-support systems application implies that the manu factur er assume s all risk of such use and in doi
ng so indemnifies Cypress Semiconductor against all charges.
Package Diagrams (continued)
28-Lead Thin Small Outline Package Z28
CY62256V
PRELIMINARY
Document #: 38-05057 Rev. ** Page 13 of 13
Document Title: CY62256V 32K x 8 Static RAM
Document Number: 38-05057
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 107248 09/10/01 SZV Change from Spec number: 38-00519 to 38-05057
