HEF4027BPN - NXP Semiconductors / Philips Semiconductors

1. General description

The HEF4027B is a edge-trigg ered dua l JK flip-flop which fe atures indepen dent set-direct

(SD), clear-direct (CD), clock (CP) input s and outputs (Q, Q). Dat a is accepted when CP is

LOW, and transfer re d to the ou tp u t on th e po sitiv e- go in g ed ge of th e cl oc k. Th e active

HIGH asynchronous clear-direct (CD) and set-direct (SD) inputs ar e independent and

override the J, K, and CP inputs. The outputs are buffered for best system performance.

Schmitt trigger action makes the clock input highly tolerant of slower rise and fall times.

It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS

(usually ground). Unused inputs must be connected to VDD, VSS, or another inpu t. It is

also suitable for use over the full industrial (−40 °C to +85 °C) temperature range.

2. Features

Fully static operation

5 V, 10 V, and 15 V parametric ratings

Standardized symmetrical output characteristics

Operates across the full industrial temperature range −40 °C to +85 °C

Complies with JEDEC standard JESD 13-B

3. Applications

Registers

Counters

Control circuits

4. Ordering information

HEF4027B

Dual JK flip-flop

Rev. 07 — 25 November 2009 Product data sheet

Table 1. Ordering information

Tamb from

−

C to +85

Type number Package

Name Description Version

HEF4027BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4

HEF4027BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

Product data sheet Rev. 07 — 25 November 2009 2 of 13

NXP Semiconductors HEF4027B

Dual JK flip-f lo p

5. Functional diagram

Fig 1. Functional di agram

001aae593

1SD

1CD

1J 1Q

1CP

1K 1Q

2SD

2CD

2J 2Q

FF 2

FF 1

2CP

2K 2Q

Fig 2. Logic diagram of one flip-flop

001aae59

Product data sheet Rev. 07 — 25 November 2009 3 of 13

NXP Semiconductors HEF4027B

Dual JK flip-f lo p

6. Pinning information

6.1 Pinning

6.2 Pin description

7. Functional description

Fig 3. Pin configuratio n

HEF4027B

2Q V

2Q 1Q

2CP 1Q

2CD 1CP

2K 1CD

2J 1K

2SD 1J

1SD

001aae594

Table 2. Pin description

Symbol Pin Description

VSS 8 ground supply voltage

1SD, 2SD 9, 7 asynchronous set-direct input (active HIGH)

1J, 2J 10, 6 synchronous input

1K, 2K 11, 5 synchronous input

1CD, 2CD 12, 4 asynchronous clear-direct input (active HIGH)

1CP, 2CP 13, 3 clock input (LOW-to-HIGH edge-trigg ered)

1Q, 2Q 14, 2 complement output

1Q, 2Q 15, 1 true output

VDD 16 supply voltage

Table 3. Function table[1]

Inputs Outputs

nSD nCD nCP nJ nK nQ nQ

HLXXXHL

LHXXXLH

HHXXXHH

Product data sheet Rev. 07 — 25 November 2009 4 of 13

NXP Semiconductors HEF4027B

Dual JK flip-f lo p

[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.; ↑ = positive-going transition.

8. Limiting values

[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C.

[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C.

9. Recommended operating conditions

LL↑L L no change no change

LL↑HLHL

LL↑LHLH

LL↑HHnQ

Table 3. Function table[1] …continued

Inputs Outputs

nSD nCD nCP nJ nK nQ nQ

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage −0.5 +18 V

IIK input clamping current VI<−0.5 V or VI>V

DD + 0.5 V - ±10 mA

VIinput voltage −0.5 VDD + 0.5 V

IOK output clamping current VO<−0.5 V or VO>V

DD + 0.5 V - ±10 mA

II/O input/output current - ±10 mA

IDD supply current - 50 mA

Tstg storage temperature −65 +150 °C

Tamb ambient temperature in free air −40 +85 °C

Ptot total power dissipation Tamb −40 °C to +85 °C

DIP16 package [1] -750mW

SO16 package [2] -500mW

P power dissipation per output - 100 mW

Table 5. Recommended operating con ditions

Symbol Parameter Conditions Min Max Unit

VDD supply voltage 3 15 V

VIinput voltage 0 VDD V

Tamb ambient temperature in free air −40 +85 °C

Δt/ΔV input transition rise and fall rate VDD = 5 V - 3.7 5 μs/V

VDD = 10 V - 0.5 μs/V

VDD = 15 V - 0.08 μs/V

Product data sheet Rev. 07 — 25 November 2009 5 of 13

NXP Semiconductors HEF4027B

Dual JK flip-f lo p

10. Static characteristics

Table 6. Static characteristics

VSS = 0 V; VI = VSS or VDD; unless otherwise specified.

Symbol Parameter Conditions VDD Tamb = −40 °C Tamb = 25 °C Tamb = 85 °CUnit

Min Max Min Max Min Max

VIH HIGH-level input voltage |IO| < 1 μA 5 V 3.5 - 3.5 - 3.5 - V

10 V 7.0 - 7.0 - 7.0 - V

15 V 11.0 - 11.0 - 11.0 - V

VIL LOW-level input voltage |IO| < 1 μA5 V-1.5-1.5-1.5V

10 V - 3.0 - 3.0 - 3.0 V

15 V - 4.0 - 4.0 - 4.0 V

VOH HIGH-level output voltage |IO| < 1 μA 5 V 4.95 - 4.95 - 4.95 - V

10 V 9.95 - 9.95 - 9.95 - V

15 V 14.95 - 14.95 - 14.95 - V

VOL LOW-level output voltage |IO| < 1 μA 5 V - 0.05 - 0.05 - 0.05 V

10 V - 0.05 - 0.05 - 0.05 V

15 V - 0.05 - 0.05 - 0.05 V

IOH HIGH-level output current VO = 2.5 V 5 V −1.7 - −1.4 - −1.1 - mA

VO = 4.6 V 5 V −0.52 - −0.44 - −0.36 - mA

VO = 9.5 V 10 V −1.3 - −1.1 - −0.9 - mA

VO = 13.5 V 15 V −3.6 - −3.0 - −2.4 - mA

IOL LOW-level output current VO = 0.4 V 5 V 0.52 - 0.44 - 0.36 - mA

VO = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA

VO = 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA

IIinput leakage current 15 V - ±0.3 - ±0.3 - ±1.0 μA

IDD supply current IO = 0 A 5 V - 4.0 - 4.0 - 30 μA

10 V - 8.0 - 8.0 - 60 μA

15 V - 16.0 - 16.0 - 120 μA

CIinput capacitance - - - - 7.5 - - pF

Product data sheet Rev. 07 — 25 November 2009 6 of 13

NXP Semiconductors HEF4027B

Dual JK flip-f lo p

11. Dynamic characteristics

Table 7. Dynamic characteristics

VSS = 0 V; Tamb = 25

C; for test circuit see Figure 7; unless otherwise speci fied.

Symbol Parameter Conditions VDD Extrapolation formula[1] Min Typ Max Unit

tPHL HIGH to LOW

propagation delay CP → Q, Q;

see Figure 4 5 V 78 ns + (0.55 ns/pF)CL- 105 210 ns

10 V 29 ns + (0.23 ns/pF)CL-4080ns

15 V 22 ns + (0.16 ns/pF)CL-3060ns

CD → Q;

see Figure 4 5 V 93 ns + (0.55 ns/pF)CL- 120 240 ns

10 V 33 ns + (0.23 ns/pF)CL-4590ns

15 V 27 ns + (0.16 ns/pF)CL-3570ns

SD → Q;

see Figure 4 5 V 113 ns + (0.55 ns/pF ) C L- 140 280 ns

10 V 44 ns + (0.23 ns/pF)CL-55110ns

15 V 32 ns + (0.16 ns/pF)CL-4080ns

tPLH LOW to HIGH

propagation delay CP → Q, Q;

see Figure 4 5 V 58 ns + (0.55 ns/pF)CL- 85 170 ns

10 V 27 ns + (0.23 ns/pF)CL-3570ns

15 V 22 ns + (0.16 ns/pF)CL-3060ns

CD → Q;

see Figure 4 5 V 48 ns + (0.55 ns/pF)CL- 75 150 ns

10 V 24 ns + (0.23 ns/pF)CL-3570ns

15 V 17 ns + (0.16 ns/pF)CL-2550ns

SD → Q;

see Figure 4 5 V 43 ns + (0.55 ns/pF)CL- 70 140 ns

10 V 19 ns + (0.23 ns/pF)CL-3060ns

15 V 17 ns + (0.16 ns/pF)CL-2550ns

tttransition time see Figure 4 5 V [2] 10 ns + (1.00 ns/pF)CL- 60 120 ns

10 V 9 ns + (0.42 ns/pF)CL-3060ns

15 V 6 ns + (0.28 ns/pF)CL-2040ns

tsu set-up time J, K → CP;

see Figure 5 5 V 50 25 - ns

10 V 30 1 0 - ns

15 V 20 5 - ns

thhold time J, K → CP;

see Figure 5 5 V 25 0 - ns

10 V 20 0 - ns

15 V 15 5 - ns

tWpulse width CP LOW;

minimum width

see Figure 5

5 V 80 40 - ns

10 V 30 1 5 - ns

15 V 24 1 2 - ns

SD, CD HIGH;

minimum width

see Figure 6

5 V 90 45 - ns

10 V 40 2 0 - ns

15 V 30 1 5 - ns

trec recovery time SD, CD inputs;

see Figure 6 5 V +20 −15 - ns

10 V +15 −10 - ns

15 V +10 −5- ns

Product data sheet Rev. 07 — 25 November 2009 7 of 13

NXP Semiconductors HEF4027B

Dual JK flip-f lo p

[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).

[2] tt is the same as tTLH and tTHL.

12. Waveforms

fmax maximum

frequency CP input;

J = K = HIGH;

see Figure 5

5 V 4 8 - MHz

10 V 12 25 - MHz

15 V 15 30 - MHz

Table 7. Dynamic characteristics …continued

VSS = 0 V; Tamb = 25

C; for test circuit see Figure 7; unless otherwise speci fied.

Symbol Parameter Conditions VDD Extrapolation formula[1] Min Typ Max Unit

Table 8. Dynamic power dissipation PD

PD can be calculated from the formulas shown. VSS = 0 V; tr = tf

≤

20 ns; Tamb = 25

Symbol Parameter VDD Typical formula for PD (μW) Where:

PDdynamic power

dissipation 5 V PD = 900 × fi + Σ(fo × CL) × VDD2fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VDD = supply voltage in V;

Σ(fo × CL) = sum of the outputs.

10 V PD = 4500 × fi + Σ(fo × CL) × VDD2

15 V PD = 13200 × fi + Σ(fo × CL) × VDD2

VOH and VOL are typical output voltages levels that occur with the output load.

Measurement points are given in Table 9.

Fig 4. Waveforms showing rise, fall and transition times an d propagation delays

Measurement points are given in Table 9.

Fig 5. Waveforms showing set-up and hold times and minimum clock pulse width

001aah86

SD, CD or CP

INPUT

0 V

Q or Q

OUTPUT V

PLH

PHL

90 %

10 %

TLH

THL

001aae59

CP INPUT

J,K INPUT

1/fmax

tsu

Product data sheet Rev. 07 — 25 November 2009 8 of 13

NXP Semiconductors HEF4027B

Dual JK flip-f lo p

VOH and VOL are typical output voltages levels that occur with the output load.

Measurement points are given in Table 9.

Fig 6. Waveforms showing pulse widths and recovery times

001aae59

INPUT

0 V

CD INPUT

CP INPUT

Q OUTPUT

rec

Table 9. Measurement points

Supply voltage Input Output

VDD VMVM

5 V to 15 V 0.5VDD 0.5VDD

Test data is given in Table 10.

Definitions for test circuit:

DUT = Device Under Test.

CL= load capacitance including jig and probe capacitance.

RT= termination resistance should be equal to the output impedance Zo of the pulse generator.

Fig 7. Tes t circui t

VDD

VIVO

001aag18

DUT

Table 10. Test data

Supply voltage Input Load

VDD VItr, tfCL

5 V to 15 V VSS or VDD ≤20 ns 50 pF

Product data sheet Rev. 07 — 25 November 2009 9 of 13

NXP Semiconductors HEF4027B

Dual JK flip-f lo p

13. Package outline

Fig 8. Package outline SOT38-4 (DIP16)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT38-4 95-01-14

03-02-13

(e )

seating plane

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

UNIT A

max. 12 b1(1) (1) (1)

b2cD E e M Z

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

min. A

max. bmax.

1.73

1.30

0.53

0.38

0.36

0.23

19.50

18.55

6.48

6.20

3.60

3.05 0.2542.54 7.62 8.25

7.80

10.0

8.3 0.764.2 0.51 3.2

inches 0.068

0.051

0.021

0.015

0.014

0.009

1.25

0.85

0.049

0.033

0.77

0.73

0.26

0.24

0.14

0.12 0.010.1 0.3 0.32

0.31

0.39

0.33 0.030.17 0.02 0.13

IP16: plastic dual in-line package; 16 leads (300 mil) SOT38

-4

Product data sheet Rev. 07 — 25 November 2009 10 of 13

NXP Semiconductors HEF4027B

Dual JK flip-f lo p

Fig 9. Package outline SOT109-1 (SO16)

detail X

vMA

(A )

pin 1 index

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10

1.45

1.25 0.25 0.49

0.36

0.25

0.19

10.0

9.8

4.0

3.8 1.27 6.2

5.8

0.7

0.6

0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT109-1 99-12-27

03-02-19

076E07 MS-012

0.069 0.010

0.004

0.057

0.049 0.01 0.019

0.014

0.0100

0.0075

0.39

0.38

0.16

0.15 0.05

1.05

0.041

0.244

0.228

0.028

0.020

0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

0 2.5 5 mm

scale

O16: plastic small outline package; 16 leads; body width 3.9 mm SOT109

-1

Product data sheet Rev. 07 — 25 November 2009 11 of 13

NXP Semiconductors HEF4027B

Dual JK flip-f lo p

14. Revision history

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

HEF4027B_7 20091125 Product data sheet - HEF4027B_6

Modifications: •Section 9 “Recommended operating conditions”, Δt/ΔV values updated.

HEF4027B_6 20090624 Product data sheet - HEF4027B_5

HEF4027B_5 20081110 Product data sheet - HEF4027B_4

HEF4027B_4 20080703 Product specification - HEF4027B_CNV_3

HEF4027B_CNV_3 19950101 Product specification - HEF4027B_CNV_2

HEF4027B_CNV_2 19950101 Produ ct specification - -

Product data sheet Rev. 07 — 25 November 2009 12 of 13

NXP Semiconductors HEF4027B

Dual JK flip-f lo p

15. Legal information

15.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

15.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warrant ies as to t he accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short dat a sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not b e relied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre va il.

15.3 Disclaimers

General — In formation in this document is believed to be accurate and

reliable. However, NXP Semiconductors d oes not give an y represent ations or

warranties, expressed or impli ed, as to the accuracy or completeness of such

information and shall have no liability for th e co nsequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are no t designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liab ility for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for il lustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ra tings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other co nditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may af fect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/profile/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conflict between inf ormation in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Not hing in this document may be interpret ed or

construed as an of fer t o sell product s that is open for accept ance or the gr ant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulatio ns. Export might require a prior

authorization from national authorities.

15.4 Trademarks

Notice: All refe renced brands, produc t names, service names and trademarks

are the property of their respective ow ners.

16. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contain s data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] data sheet Production This document contains the product specification.

NXP Semiconductors HEF4027B

Dual JK flip-f lo p

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of rele ase: 25 November 2009

Document identifier: HEF4027B_7

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

17. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 1

5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

7 Functional description . . . . . . . . . . . . . . . . . . . 3

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4

9 Recommended operating conditions. . . . . . . . 4

10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5

11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6

12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9

14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 11

15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12

15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12

15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 12

15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 12

16 Contact information. . . . . . . . . . . . . . . . . . . . . 12

17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13