Features * High-performance, Low-power AVR(R) 8-bit Microcontroller * Advanced RISC Architecture * * * * * * * * - 131 Powerful Instructions - Most Single-clock Cycle Execution - 32 x 8 General Purpose Working Registers - Fully Static Operation - Up to 16 MIPS Throughput at 16 MHz - On-chip 2-cycle Multiplier Nonvolatile Program and Data Memories - 32K Bytes of In-System Self-Programmable Flash Endurance: 10,000 Write/Erase Cycles - Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation - 1024 Bytes EEPROM Endurance: 100,000 Write/Erase Cycles - 2K Byte Internal SRAM - Programming Lock for Software Security JTAG (IEEE std. 1149.1 Compliant) Interface - Boundary-scan Capabilities According to the JTAG Standard - Extensive On-chip Debug Support - Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface Peripheral Features - Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes - One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode - Real Time Counter with Separate Oscillator - Four PWM Channels - 8-channel, 10-bit ADC 8 Single-ended Channels 7 Differential Channels in TQFP Package Only 2 Differential Channels with Programmable Gain at 1x, 10x, or 200x - Byte-oriented Two-wire Serial Interface - Programmable Serial USART - Master/Slave SPI Serial Interface - Programmable Watchdog Timer with Separate On-chip Oscillator - On-chip Analog Comparator Special Microcontroller Features - Power-on Reset and Programmable Brown-out Detection - Internal Calibrated RC Oscillator - External and Internal Interrupt Sources - Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended Standby I/O and Packages - 32 Programmable I/O Lines - 40-pin PDIP, 44-lead TQFP, and 44-pad MLF Operating Voltages - 2.7 - 5.5V for ATmega32L - 4.5 - 5.5V for ATmega32 Speed Grades - 0 - 8 MHz for ATmega32L - 0 - 16 MHz for ATmega32 Power Consumption at 1 MHz, 3V, 25C for ATmega32L - Active: 1.1 mA - Idle Mode: 0.35 mA - Power-down Mode: < 1 A 8-bit Microcontroller with 32K Bytes In-System Programmable Flash ATmega32 ATmega32L Summary 2503GS-AVR-11/04 Note: This is a summary document. A complete document is available on our Web site at www.atmel.com. Pin Configurations Figure 1. Pinout ATmega32 PDIP (XCK/T0) PB0 (T1) PB1 (INT2/AIN0) PB2 (OC0/AIN1) PB3 (SS) PB4 (MOSI) PB5 (MISO) PB6 (SCK) PB7 RESET VCC GND XTAL2 XTAL1 (RXD) PD0 (TXD) PD1 (INT0) PD2 (INT1) PD3 (OC1B) PD4 (OC1A) PD5 (ICP1) PD6 PA0 (ADC0) PA1 (ADC1) PA2 (ADC2) PA3 (ADC3) PA4 (ADC4) PA5 (ADC5) PA6 (ADC6) PA7 (ADC7) AREF GND AVCC PC7 (TOSC2) PC6 (TOSC1) PC5 (TDI) PC4 (TDO) PC3 (TMS) PC2 (TCK) PC1 (SDA) PC0 (SCL) PD7 (OC2) PB4 (SS) PB3 (AIN1/OC0) PB2 (AIN0/INT2) PB1 (T1) PB0 (XCK/T0) GND VCC PA0 (ADC0) PA1 (ADC1) PA2 (ADC2) PA3 (ADC3) TQFP/MLF (MOSI) PB5 (MISO) PB6 (SCK) PB7 RESET VCC GND XTAL2 XTAL1 (RXD) PD0 (TXD) PD1 (INT0) PD2 (INT1) (OC1B) (OC1A) (ICP1) (OC2) PD3 PD4 PD5 PD6 PD7 VCC GND (SCL) PC0 (SDA) PC1 (TCK) PC2 (TMS) PC3 PA4 (ADC4) PA5 (ADC5) PA6 (ADC6) PA7 (ADC7) AREF GND AVCC PC7 (TOSC2) PC6 (TOSC1) PC5 (TDI) PC4 (TDO) 2 ATmega32(L) 2503GS-AVR-11/04 ATmega32(L) Overview The ATmega32 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega32 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Block Diagram Figure 2. Block Diagram PA0 - PA7 PC0 - PC7 PORTA DRIVERS/BUFFERS PORTC DRIVERS/BUFFERS PORTA DIGITAL INTERFACE PORTC DIGITAL INTERFACE VCC GND AVCC MUX & ADC ADC INTERFACE TWI AREF PROGRAM COUNTER STACK POINTER PROGRAM FLASH SRAM TIMERS/ COUNTERS OSCILLATOR INTERNAL OSCILLATOR XTAL1 INSTRUCTION REGISTER GENERAL PURPOSE REGISTERS WATCHDOG TIMER OSCILLATOR XTAL2 X INSTRUCTION DECODER Y MCU CTRL. & TIMING RESET Z CONTROL LINES ALU INTERRUPT UNIT AVR CPU STATUS REGISTER EEPROM PROGRAMMING LOGIC SPI USART + - INTERNAL CALIBRATED OSCILLATOR COMP. INTERFACE PORTB DIGITAL INTERFACE PORTD DIGITAL INTERFACE PORTB DRIVERS/BUFFERS PORTD DRIVERS/BUFFERS PB0 - PB7 PD0 - PD7 3 2503GS-AVR-11/04 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega32 provides the following features: 32K bytes of In-System Programmable Flash Program memory with Read-While-Write capabilities, 1024 bytes EEPROM, 2K byte SRAM, 32 general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip Debugging support and programming, three flexible Timer/Counters with compare modes, Internal and External Interrupts, a serial programmable USART, a byte oriented Two-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with programmable gain (TQFP package only), a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, and six software selectable power saving modes. The Idle mode stops the CPU while allowing the USART, Two-wire interface, A/D Converter, SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next External Interrupt or Hardware Reset. In Power-save mode, the Asynchronous Timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. The device is manufactured using Atmel's high density nonvolatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega32 is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many embedded control applications. The ATmega32 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. Pin Descriptions VCC Digital supply voltage. GND Ground. Port A (PA7..PA0) Port A serves as the analog inputs to the A/D Converter. Port A also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. 4 ATmega32(L) 2503GS-AVR-11/04 ATmega32(L) Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega32 as listed on page 55. Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PC5(TDI), PC3(TMS) and PC2(TCK) will be activated even if a reset occurs. The TD0 pin is tri-stated unless TAP states that shift out data are entered. Port C also serves the functions of the JTAG interface and other special features of the ATmega32 as listed on page 58. Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega32 as listed on page 60. RESET Reset Input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 15 on page 35. Shorter pulses are not guaranteed to generate a reset. XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting Oscillator amplifier. AVCC AVCC is the supply voltage pin for Port A and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. AREF AREF is the analog reference pin for the A/D Converter. 5 2503GS-AVR-11/04 Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 $3F ($5F) SREG I T H S V N Z C 8 $3E ($5E) SPH - - - - SP11 SP10 SP9 SP8 10 SP4 SP3 SP2 SP1 SP0 10 - - - IVSEL IVCE 45, 65 $3D ($5D) SPL $3C ($5C) OCR0 $3B ($5B) GICR INT1 INT0 80 INT2 $3A ($5A) GIFR INTF1 INTF0 INTF2 - - - - - 66 $39 ($59) TIMSK OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 OCIE0 TOIE0 80, 110, 128 81, 111, 128 $38 ($58) TIFR OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 OCF0 TOV0 $37 ($57) SPMCR SPMIE RWWSB - RWWSRE BLBSET PGWRT PGERS SPMEN 246 $36 ($56) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN - TWIE 175 $35 ($55) MCUCR SE SM2 SM1 SM0 ISC11 ISC10 ISC01 ISC00 30, 64 $34 ($54) MCUCSR JTD ISC2 - JTRF WDRF BORF EXTRF PORF 38, 65, 226 $33 ($53) TCCR0 FOC0 WGM00 COM01 COM00 WGM01 CS02 CS01 CS00 78 $32 ($52) TCNT0 $31(1) ($51)(1) OSCCAL OCDR Timer/Counter0 (8 Bits) 80 Oscillator Calibration Register 28 On-Chip Debug Register 222 $30 ($50) SFIOR ADTS2 ADTS1 ADTS0 - ACME PUD PSR2 PSR10 54,83,129,196,216 $2F ($4F) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B WGM11 WGM10 105 $2E ($4E) TCCR1B ICNC1 ICES1 - WGM13 WGM12 CS12 CS11 CS10 108 $2D ($4D) TCNT1H Timer/Counter1 - Counter Register High Byte 109 $2C ($4C) TCNT1L 109 $2B ($4B) OCR1AH Timer/Counter1 - Counter Register Low Byte Timer/Counter1 - Output Compare Register A High Byte $2A ($4A) OCR1AL Timer/Counter1 - Output Compare Register A Low Byte 109 $29 ($49) OCR1BH Timer/Counter1 - Output Compare Register B High Byte 109 109 $28 ($48) OCR1BL Timer/Counter1 - Output Compare Register B Low Byte 109 $27 ($47) ICR1H Timer/Counter1 - Input Capture Register High Byte 110 $26 ($46) ICR1L Timer/Counter1 - Input Capture Register Low Byte $25 ($45) TCCR2 $24 ($44) TCNT2 Timer/Counter2 (8 Bits) $23 ($43) OCR2 Timer/Counter2 Output Compare Register $22 ($42) ASSR $21 ($41) $20(2) ($40)(2) 6 SP7 SP6 SP5 Timer/Counter0 Output Compare Register Page FOC2 WGM20 COM21 110 COM20 WGM21 CS22 CS21 CS20 123 125 125 - - - - AS2 TCN2UB OCR2UB TCR2UB WDTCR - - - WDTOE WDE WDP2 WDP1 WDP0 UBRRH URSEL - - - UBRR[11:8] 126 40 162 UCSRC URSEL UMSEL UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPOL 160 $1F ($3F) EEARH - - - - - - EEAR9 EEAR8 17 $1E ($3E) EEARL EEPROM Address Register Low Byte $1D ($3D) EEDR EEPROM Data Register $1C ($3C) EECR - - - - EERIE EEMWE EEWE EERE $1B ($3B) PORTA PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 62 $1A ($3A) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 62 62 17 17 17 $19 ($39) PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 $18 ($38) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 62 $17 ($37) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 62 $16 ($36) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 63 $15 ($35) PORTC PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 63 $14 ($34) DDRC DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 63 $13 ($33) PINC PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 63 $12 ($32) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 63 $11 ($31) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 63 PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 $10 ($30) PIND $0F ($2F) SPDR SPI Data Register 63 136 $0E ($2E) SPSR SPIF WCOL - - - - - SPI2X 136 $0D ($2D) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 134 $0C ($2C) UDR $0B ($2B) UCSRA USART I/O Data Register 157 $0A ($2A) UCSRB $09 ($29) UBRRL $08 ($28) ACSR ACD ACBG $07 ($27) ADMUX REFS1 $06 ($26) ADCSRA ADEN $05 ($25) ADCH ADC Data Register High Byte 215 $04 ($24) ADCL ADC Data Register Low Byte 215 $03 ($23) TWDR Two-wire Serial Interface Data Register $02 ($22) TWAR RXC TXC UDRE FE DOR PE U2X MPCM 158 RXCIE TXCIE UDRIE RXEN TXEN UCSZ2 RXB8 TXB8 159 ACO ACI ACIE ACIC ACIS1 ACIS0 197 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 212 ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 214 USART Baud Rate Register Low Byte TWA6 TWA5 TWA4 162 177 TWA3 TWA2 TWA1 TWA0 TWGCE 177 ATmega32(L) 2503GS-AVR-11/04 ATmega32(L) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page $01 ($21) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 - TWPS1 TWPS0 176 $00 ($20) TWBR Notes: Two-wire Serial Interface Bit Rate Register 175 1. When the OCDEN Fuse is unprogrammed, the OSCCAL Register is always accessed on this address. Refer to the debugger specific documentation for details on how to use the OCDR Register. 2. Refer to the USART description for details on how to access UBRRH and UCSRC. 3. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 4. Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only. 7 2503GS-AVR-11/04 Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd Rd + Rr Z,C,N,V,H ADC Rd, Rr Add with Carry two Registers Rd Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two Registers Rd Rd - Rr - C Z,C,N,V,H 1 1 SBCI Rd, K Subtract with Carry Constant from Reg. Rd Rd - K - C Z,C,N,V,H 1 SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl Rdh:Rdl - K Z,C,N,V,S 2 1 AND Rd, Rr Logical AND Registers Rd Rd * Rr Z,N,V ANDI Rd, K Logical AND Register and Constant Rd Rd * K Z,N,V 1 OR Rd, Rr Logical OR Registers Rd Rd v Rr Z,N,V 1 ORI Rd, K Logical OR Register and Constant Rd Rd v K Z,N,V 1 EOR Rd, Rr Exclusive OR Registers Rd Rd Rr Z,N,V 1 COM Rd One's Complement Rd $FF - Rd Z,C,N,V 1 NEG Rd Two's Complement Rd $00 - Rd Z,C,N,V,H 1 SBR Rd,K Set Bit(s) in Register Rd Rd v K Z,N,V 1 CBR Rd,K Clear Bit(s) in Register Rd Rd * ($FF - K) Z,N,V 1 INC Rd Increment Rd Rd + 1 Z,N,V 1 DEC Rd Decrement Rd Rd - 1 Z,N,V 1 TST Rd Test for Zero or Minus Rd Rd * Rd Z,N,V 1 CLR Rd Clear Register Rd Rd Rd Z,N,V 1 SER Rd Set Register Rd $FF None 1 MUL Rd, Rr Multiply Unsigned R1:R0 Rd x Rr Z,C 2 MULS Rd, Rr Multiply Signed R1:R0 Rd x Rr Z,C 2 MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 Rd x Rr Z,C 2 FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 (Rd x Rr) << Z,C 2 FMULS Rd, Rr Fractional Multiply Signed Z,C 2 FMULSU Rd, Rr Fractional Multiply Signed with Unsigned 1 R1:R0 (Rd x Rr) << 1 R1:R0 (Rd x Rr) << 1 Z,C 2 Relative Jump PC PC + k + 1 None 2 Indirect Jump to (Z) PC Z None 2 3 BRANCH INSTRUCTIONS RJMP k IJMP JMP k Direct Jump PC k None RCALL k Relative Subroutine Call PC PC + k + 1 None 3 Indirect Call to (Z) PC Z None 3 ICALL Direct Subroutine Call PC k None 4 RET Subroutine Return PC Stack None 4 RETI Interrupt Return PC Stack I if (Rd = Rr) PC PC + 2 or 3 None CALL k 4 CPSE Rd,Rr Compare, Skip if Equal 1/2/3 CP Rd,Rr Compare Rd - Rr Z, N,V,C,H 1 CPC Rd,Rr Compare with Carry Rd - Rr - C Z, N,V,C,H 1 CPI Rd,K Compare Register with Immediate Rd - K Z, N,V,C,H SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC PC + 2 or 3 None 1 1/2/3 SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC PC + 2 or 3 None 1/2/3 SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC PC + 2 or 3 None 1/2/3 SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC PC + 2 or 3 None 1/2/3 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PCPC+k + 1 None 1/2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PCPC+k + 1 None 1/2 BREQ k Branch if Equal if (Z = 1) then PC PC + k + 1 None 1/2 BRNE k Branch if Not Equal if (Z = 0) then PC PC + k + 1 None 1/2 BRCS k Branch if Carry Set if (C = 1) then PC PC + k + 1 None 1/2 BRCC k Branch if Carry Cleared if (C = 0) then PC PC + k + 1 None 1/2 BRSH k Branch if Same or Higher if (C = 0) then PC PC + k + 1 None 1/2 BRLO k Branch if Lower if (C = 1) then PC PC + k + 1 None 1/2 BRMI k Branch if Minus if (N = 1) then PC PC + k + 1 None 1/2 BRPL k Branch if Plus if (N = 0) then PC PC + k + 1 None 1/2 BRGE k Branch if Greater or Equal, Signed if (N V= 0) then PC PC + k + 1 None 1/2 BRLT k Branch if Less Than Zero, Signed if (N V= 1) then PC PC + k + 1 None 1/2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC PC + k + 1 None 1/2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC PC + k + 1 None 1/2 BRTS k Branch if T Flag Set if (T = 1) then PC PC + k + 1 None 1/2 BRTC k Branch if T Flag Cleared if (T = 0) then PC PC + k + 1 None 1/2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC PC + k + 1 None 1/2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC PC + k + 1 None 1/2 8 ATmega32(L) 2503GS-AVR-11/04 ATmega32(L) Mnemonics Operands Description Operation Flags BRIE k Branch if Interrupt Enabled if ( I = 1) then PC PC + k + 1 None #Clocks 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC PC + k + 1 None 1/2 None 1 None 1 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers MOVW Rd, Rr Copy Register Word Rd Rr Rd+1:Rd Rr+1:Rr LDI Rd, K Load Immediate Rd K None 1 LD Rd, X Load Indirect Rd (X) None 2 LD Rd, X+ Load Indirect and Post-Inc. Rd (X), X X + 1 None 2 LD Rd, - X Load Indirect and Pre-Dec. X X - 1, Rd (X) None 2 2 LD Rd, Y Load Indirect Rd (Y) None LD Rd, Y+ Load Indirect and Post-Inc. Rd (Y), Y Y + 1 None 2 LD Rd, - Y Load Indirect and Pre-Dec. Y Y - 1, Rd (Y) None 2 LDD Rd,Y+q Load Indirect with Displacement Rd (Y + q) None 2 LD Rd, Z Load Indirect Rd (Z) None 2 LD Rd, Z+ Load Indirect and Post-Inc. Rd (Z), Z Z+1 None 2 LD Rd, -Z Load Indirect and Pre-Dec. Z Z - 1, Rd (Z) None 2 LDD Rd, Z+q Load Indirect with Displacement Rd (Z + q) None 2 2 LDS Rd, k Load Direct from SRAM Rd (k) None ST X, Rr Store Indirect (X) Rr None 2 ST X+, Rr Store Indirect and Post-Inc. (X) Rr, X X + 1 None 2 ST - X, Rr Store Indirect and Pre-Dec. X X - 1, (X) Rr None 2 ST Y, Rr Store Indirect (Y) Rr None 2 ST Y+, Rr Store Indirect and Post-Inc. (Y) Rr, Y Y + 1 None 2 ST - Y, Rr Store Indirect and Pre-Dec. Y Y - 1, (Y) Rr None 2 STD Y+q,Rr Store Indirect with Displacement (Y + q) Rr None 2 ST Z, Rr Store Indirect (Z) Rr None 2 ST Z+, Rr Store Indirect and Post-Inc. (Z) Rr, Z Z + 1 None 2 ST -Z, Rr Store Indirect and Pre-Dec. Z Z - 1, (Z) Rr None 2 STD Z+q,Rr Store Indirect with Displacement (Z + q) Rr None 2 STS k, Rr Store Direct to SRAM (k) Rr None 2 Load Program Memory R0 (Z) None 3 LPM LPM Rd, Z Load Program Memory Rd (Z) None 3 LPM Rd, Z+ Load Program Memory and Post-Inc Rd (Z), Z Z+1 None 3 Store Program Memory (Z) R1:R0 None - In Port Rd P None 1 1 SPM IN Rd, P OUT P, Rr Out Port P Rr None PUSH Rr Push Register on Stack Stack Rr None 2 POP Rd Pop Register from Stack Rd Stack None 2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) 0 None 2 LSL Rd Logical Shift Left Rd(n+1) Rd(n), Rd(0) 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) Rd(n+1), Rd(7) 0 Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0)C,Rd(n+1) Rd(n),CRd(7) Z,C,N,V 1 ROR Rd Rotate Right Through Carry Rd(7)C,Rd(n) Rd(n+1),CRd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) None 1 BSET s Flag Set SREG(s) 1 SREG(s) 1 BCLR s Flag Clear SREG(s) 0 SREG(s) 1 BST Rr, b Bit Store from Register to T T Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b) T None 1 1 SEC Set Carry C1 C CLC Clear Carry C0 C 1 SEN Set Negative Flag N1 N 1 CLN Clear Negative Flag N0 N 1 SEZ Set Zero Flag Z1 Z 1 CLZ Clear Zero Flag Z0 Z 1 SEI Global Interrupt Enable I1 I 1 CLI Global Interrupt Disable I0 I 1 1 SES Set Signed Test Flag S1 S CLS Clear Signed Test Flag S0 S 1 SEV Set Twos Complement Overflow. V1 V 1 CLV SET CLT SEH Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG V0 T1 T0 H1 V T T H 1 1 1 1 9 2503GS-AVR-11/04 Mnemonics Operands CLH MCU CONTROL INSTRUCTIONS NOP SLEEP WDR BREAK 10 Description Operation Flags Clear Half Carry Flag in SREG H0 H No Operation Sleep Watchdog Reset Break (see specific descr. for Sleep function) (see specific descr. for WDR/timer) For On-Chip Debug Only None None None None #Clocks 1 1 1 1 N/A ATmega32(L) 2503GS-AVR-11/04 ATmega32(L) Ordering Information Speed (MHz) 8 16 Notes: Power Supply 2.7 - 5.5V 4.5 - 5.5V Ordering Code Package(1) ATmega32L-8AC ATmega32L-8PC ATmega32L-8MC 44A 40P6 44M1 Commercial (0oC to 70oC) ATmega32L-8AI ATmega32L-8AU(2) ATmega32L-8PI ATmega32L-8MI ATmega32L-8MU(2) 44A 44A 40P6 44M1 44M1 Industrial (-40oC to 85oC) ATmega32-16AC ATmega32-16PC ATmega32-16MI 44A 40P6 44M1 Commercial (0oC to 70oC) ATmega32-16AI ATmega32-16AU(2) ATmega32-16PI ATmega32-16MC ATmega32-16MU(2) 44A 44A 40P6 44M1 44M1 Industrial (-40oC to 85oC) Operational Range 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging alternative. Complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. Package Type 44A 44-lead, 10 x 10 x 1.0 mm, Thin Profile Plastic Quad Flat Package (TQFP) 40P6 40-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP) 44M1 44-pad, 7 x 7 x 1.0 mm, Micro Lead Frame Package (MLF) 11 2503GS-AVR-11/04 Packaging Information 44A PIN 1 B PIN 1 IDENTIFIER E1 e E D1 D C 0~7 A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. SYMBOL MIN NOM MAX A - - 1.20 A1 0.05 - 0.15 A2 0.95 1.00 1.05 D 11.75 12.00 12.25 D1 9.90 10.00 10.10 E 11.75 12.00 12.25 E1 9.90 10.00 10.10 B 0.30 - 0.45 C 0.09 - 0.20 L 0.45 - 0.75 e NOTE Note 2 Note 2 0.80 TYP 10/5/2001 R 12 2325 Orchard Parkway San Jose, CA 95131 TITLE 44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. REV. 44A B ATmega32(L) 2503GS-AVR-11/04 ATmega32(L) 40P6 D PIN 1 E1 A SEATING PLANE A1 L B B1 e E 0 ~ 15 C eB Notes: COMMON DIMENSIONS (Unit of Measure = mm) REF 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). SYMBOL MIN NOM MAX A - - 4.826 A1 0.381 - - D 52.070 - 52.578 E 15.240 - 15.875 E1 13.462 - 13.970 B 0.356 - 0.559 B1 1.041 - 1.651 L 3.048 - 3.556 C 0.203 - 0.381 eB 15.494 - 17.526 e NOTE Note 2 Note 2 2.540 TYP 09/28/01 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 40P6 REV. B 13 2503GS-AVR-11/04 44M1 D Marked Pin# 1 ID E SEATING PLANE A1 TOP VIEW A3 A K L Pin #1 Corner D2 1 2 3 Option A SIDE VIEW Pin #1 Triangle COMMON DIMENSIONS (Unit of Measure = mm) E2 Option B Pin #1 Chamfer (C 0.30) SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 - 0.02 0.05 A3 b K Option C e b 0.25 REF 0.18 D Pin #1 Notch (0.20 R) BOTTOM VIEW D2 0.32 5.20 5.40 7.00 BSC 5.00 e Note: JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-1. 0.23 7.00 BSC 5.00 E E2 NOTE 5.20 5.40 0.50 BSC L 0.35 0.55 0.75 K 0.20 - - 8/19/04 R 14 2325 Orchard Parkway San Jose, CA 95131 TITLE 44M1, 44-pad, 7 x 7 x 1.0 mm Body, Lead Pitch 0.50 mm, 5.20 mm Exposed Pad, Micro Lead Frame Package (MLF) DRAWING NO. 44M1 REV. E ATmega32(L) 2503GS-AVR-11/04 ATmega32(L) Errata ATmega32, rev. A to E There are no errata for this revision of ATmega32.However, a proposal for solving problems regarding the JTAG instruction IDCODE is presented below. IDCODE masks data from TDI input The public but optional JTAG instruction IDCODE is not implemented correctly according to IEEE1149.1; a logic one is scanned into the shift register instead of the TDI input while shifting the Device ID Register. Hence, captured data from the preceding devices in the boundary scan chain are lost and replaced by all-ones, and data to succeeding devices are replaced by all-ones during Update-DR. If ATmega32 is the only device in the scan chain, the problem is not visible. Problem Fix / Workaround Select the Device ID Register of the ATmega32 (Either by issuing the IDCODE instruction or by entering the Test-Logic-Reset state of the TAP controller) to read out the contents of its Device ID Register and possibly data from succeeding devices of the scan chain. Note that data to succeeding devices cannot be entered during this scan, but data to preceding devices can. Issue the BYPASS instruction to the ATmega32 to select its Bypass Register while reading the Device ID Registers of preceding devices of the boundary scan chain. Never read data from succeeding devices in the boundary scan chain or upload data to the succeeding devices while the Device ID Register is selected for the ATmega32. Note that the IDCODE instruction is the default instruction selected by the Test-Logic-Reset state of the TAP-controller. Alternative Problem Fix / Workaround If the Device IDs of all devices in the boundary scan chain must be captured simultaneously (for instance if blind interrogation is used), the boundary scan chain can be connected in such way that the ATmega32 is the fist device in the chain. UpdateDR will still not work for the succeeding devices in the boundary scan chain as long as IDCODE is present in the JTAG Instruction Register, but the Device ID registered cannot be uploaded in any case. 15 2503GS-AVR-11/04 Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. Changes from Rev. 2503F-12/03 to Rev. 2503G-11/04 1. "Channel" renamed "Compare unit" in Timer/Counter sections, ICP renamed ICP1. 2. Updated Table 7 on page 27, Table 15 on page 35, Table 81 on page 205, Table 114 on page 270, Table 115 on page 271, and Table 118 on page 287. 3. Updated Figure 1 on page 2, Figure 46 on page 98. 4. Updated "Version" on page 224. 5. Updated "Calibration Byte" on page 256. 6. Added section "Page Size" on page 256. 7. Updated "ATmega32 Typical Characteristics" on page 294. 8. Updated "Ordering Information" on page 11. Changes from Rev. 2503E-09/03 to Rev. 2503F-12/03 1. Updated "Calibrated Internal RC Oscillator" on page 27. Changes from Rev. 2503D-02/03 to Rev. 2503E-09/03 1. Updated and changed "On-chip Debug System" to "JTAG Interface and Onchip Debug System" on page 33. 2. Updated Table 15 on page 35. 3. Updated "Test Access Port - TAP" on page 217 regarding the JTAGEN fuse. 4. Updated description for Bit 7 - JTD: JTAG Interface Disable on page 226. 5. Added a note regarding JTAGEN fuse to Table 104 on page 255. 6. Updated Absolute Maximum Ratings* , DC Characteristics and ADC Characteristics in "Electrical Characteristics" on page 285. 7. Added a proposal for solving problems regarding the JTAG instruction IDCODE in "Errata" on page 15. Changes from Rev. 2503C-10/02 to Rev. 2503D-02/03 1. Added EEAR9 in EEARH in "Register Summary" on page 6. 2. Added Chip Erase as a first step in"Programming the Flash" on page 282 and "Programming the EEPROM" on page 283. 3. Removed reference to "Multi-purpose Oscillator" application note and "32 kHz Crystal Oscillator" application note, which do not exist. 4. Added information about PWM symmetry for Timer0 and Timer2. 16 ATmega32(L) 2503GS-AVR-11/04 ATmega32(L) 5. Added note in "Filling the Temporary Buffer (Page Loading)" on page 249 about writing to the EEPROM during an SPM Page Load. 6. Added "Power Consumption" data in "Features" on page 1. 7. Added section "EEPROM Write During Power-down Sleep Mode" on page 20. 8. Added note about Differential Mode with Auto Triggering in "Prescaling and Conversion Timing" on page 202. 9. Updated Table 89 on page 230. 10.Added updated "Packaging Information" on page 12. Changes from Rev. 2503B-10/02 to Rev. 2503C-10/02 1. Updated the "DC Characteristics" on page 285. Changes from Rev. 2503A-03/02 to Rev. 2503B-10/02 1. Canged the endurance on the Flash to 10,000 Write/Erase Cycles. 2. Bit nr.4 - ADHSM - in SFIOR Register removed. 3. Added the section "Default Clock Source" on page 23. 4. When using External Clock there are some limitations regards to change of frequency. This is described in "External Clock" on page 29 and Table 117 on page 287. 5. Added a sub section regarding OCD-system and power consumption in the section "Minimizing Power Consumption" on page 32. 6. Corrected typo (WGM-bit setting) for: - - - - "Fast PWM Mode" on page 73 (Timer/Counter0) "Phase Correct PWM Mode" on page 74 (Timer/Counter0) "Fast PWM Mode" on page 118 (Timer/Counter2) "Phase Correct PWM Mode" on page 119 (Timer/Counter2) 7. Corrected Table 67 on page 162 (USART). 8. Updated VIL, IIL, and IIH parameter in "DC Characteristics" on page 285. 9. Updated Description of OSCCAL Calibration Byte. In the datasheet, it was not explained how to take advantage of the calibration bytes for 2, 4, and 8 MHz Oscillator selections. This is now added in the following sections: Improved description of "Oscillator Calibration Register - OSCCAL" on page 28 and "Calibration Byte" on page 256. 10. Corrected typo in Table 42. 11. Corrected description in Table 45 and Table 46. 12. Updated Table 118, Table 120, and Table 121. 17 2503GS-AVR-11/04 13. Added "Errata" on page 15. 18 ATmega32(L) 2503GS-AVR-11/04 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80 Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743 Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. (c) Atmel Corporation 2004. All rights reserved. Atmel (R), logo and combinations thereof, AVR (R), and AVR Studio (R) are registered trademarks, and Everywhere You Are SM are the trademarks of Atmel Corporation or its subsidiaries. Microsoft (R), Windows (R), Windows NT(R), and Windows XP (R) are the registered trademarks of Microsoft Corporation. Other terms and product names may be trademarks of others. Printed on recycled paper. 2503GS-AVR-11/04