ADS8343
ADS8343
16-Bit, 4-Channel Serial Output Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
●BIPOLAR INPUT RANGE
●PIN-FOR-PIN COMPATIBLE WITH THE
ADS7841 AND ADS8341
●SINGLE SUPPLY: 2.7V to 5V
●4-CHANNEL SINGLE-ENDED OR
2-CHANNEL DIFFERENTIAL INPUT
●UP TO 100kHz CONVERSION RATE
●86dB SINAD
●SERIAL INTERFACE
●SSOP-16 PACKAGE
DESCRIPTION
The ADS8343 is a 4-channel, 16-bit sampling Analog-to-
Digital (A/D) converter with a synchronous serial interface.
Typical power dissipation is 8mW at a 100kHz throughput
rate and a +5V supply. The reference voltage (VREF) can be
varied between 500mV and VCC/2, providing a corresponding
input voltage range of ±VREF. The device includes a shut-
down mode which reduces power dissipation to under 15µW.
The ADS8343 is ensured down to 2.7V operation.
Low power, high speed, and an onboard multiplexer make
the ADS8343 ideal for battery-operated systems such as
personal digital assistants, portable multi-channel data log-
gers, and measurement equipment. The serial interface also
provides low-cost isolation for remote data acquisition. The
ADS8343 is available in an SSOP-16 package and is en-
sured over the –40°C to +85°C temperature range.
APPLICATIONS
●DATA ACQUISITION
●TEST AND MEASUREMENT
●INDUSTRIAL PROCESS CONTROL
●PERSONAL DIGITAL ASSISTANTS
●BATTERY-POWERED SYSTEMS
CDAC
SAR
Comparator
Four
Channel
Multiplexer
Serial
Interface
and
Control
CH0
CH1
CH2
CH3
COM
V
REF
CS
SHDN
DIN
DOUT
BUSY
DCLK
www.ti.com
Copyright © 2001-2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SBAS183C – JANUARY 2001 – REVISED APRIL 2003
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
ADS8343
2SBAS183C
www.ti.com
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
PIN CONFIGURATIONS
Top View SSOP
PIN DESCRIPTIONS
PIN NAME DESCRIPTION
1+V
CC Power Supply, 2.7V to 5V
2 CH0 Analog Input Channel 0
3 CH1 Analog Input Channel 1
4 CH2 Analog Input Channel 2
5 CH3 Analog Input Channel 3
6 COM Common reference for analog inputs. This pin is typically connected to VREF.
7SHDN Shutdown. When LOW, the device enters a very low power shutdown mode.
8V
REF Voltage Reference Input. See Electrical Characteristic Table for ranges.
9+V
CC Power Supply, 2.7V to 5V
10 GND Ground
11 GND Ground
12 DOUT Serial Data Output. Data is shifted on the falling edge of DCLK. This output is high impedance when
CS
is HIGH.
13 BUSY Busy Output. This output is high impedance when
CS
is HIGH.
14 DIN Serial Data Input. If
CS
is LOW, data is latched on rising edge of DCLK.
15
CS
Chip Select Input. Controls conversion timing and enables the serial input/output register.
16 DCLK External Clock Input. This clock runs the SAR conversion process and synchronizes serial data I/O. Maximum input clock frequency
equals 2.4MHz to achieve 100kHz sampling rate.
ABSOLUTE MAXIMUM RATINGS(1)
+VCC to GND ........................................................................ –0.3V to +6V
Analog Inputs to GND ............................................ –0.3V to +VCC + 0.3V
Digital Inputs to GND ........................................................... –0.3V to +6V
Power Dissipation .......................................................................... 250mW
Maximum Junction Temperature................................................... +150°C
Operating Temperature Range ........................................–40°C to +85°C
Storage Temperature Range .........................................–65°C to +150°C
Lead Temperature (soldering, 10s)............................................... +300°C
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
1
2
3
4
5
6
7
8
+VCC
CH0
CH1
CH2
CH3
COM
SHDN
VREF
DCLK
CS
DIN
BUSY
DOUT
GND
GND
+VCC
16
15
14
13
12
11
10
9
ADS8343
PACKAGE/ORDERING INFORMATION
MAXIMUM NO
INTEGRAL MISSING SPECIFIED
LINEARITY CODES PACKAGE TEMPERATURE ORDERING TRANSPORT
PRODUCT ERROR (LSB) ERROR (LSB) PACKAGE-LEAD DESIGNATOR(1) RANGE NUMBER MEDIA, QUANTITY
ADS8343E 8 14 SSOP-16 DBQ –40°C to +85°C ADS8343E Rails, 100
""""""ADS8343E/2K5 Tape and Reel, 2500
ADS8343EB 6 15 SSOP-16 DBQ –40°C to +85°C ADS8343EB Rails, 100
""""""ADS8343EB/2K5 Tape and Reel, 2500
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
ADS8343 3
SBAS183C www.ti.com
ELECTRICAL CHARACTERISTICS: +5V
At TA = –40°C to +85°C, +VCC = +5V, VREF = +2.5V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.
ADS8343E ADS8343EB
✻ Same specifications as ADS8343E.
NOTES: (1) LSB means Least Significant Bit. With VREF equal to +2.5V, one LSB is 76µV. (2) First nine harmonics of the test frequency. (3) Auto power-down mode
(PD1 = PD0 = 0) active or SHDN = GND. (4) Power-down after conversion mode with external clock gated ‘HIGH’.
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
RESOLUTION 16 ✻Bits
ANALOG INPUT
Full-Scale Input Span Positive Input-Negative Input –VREF +VREF ✻✻V
Absolute Input Range Positive Input –0.2 +VCC + 0.2 ✻✻V
Negative Input –0.2 +VCC + 0.2 ✻✻V
Capacitance 25 ✻pF
Leakage Current ±1✻µA
SYSTEM PERFORMANCE
No Missing Codes 14 15 Bits
Integral Linearity Error ±8±6LSB
Bipolar Error ±2±1mV
Bipolar Error Match 2.3 8.0 ✻✻LSB(1)
Gain Error ±0.05 ±0.024 %
Gain Error Match 1.0 4.0 ✻✻ LSB
Noise 20 ✻µVrms
Power-Supply Rejection +4.75V < VCC < 5.25V 3 ✻LSB(1)
SAMPLING DYNAMICS
Conversion Time 16 ✻Clk Cycles
Acquisition Time 4.5 ✻Clk Cycles
Throughput Rate 100 ✻kHz
Multiplexer Settling Time 500 ✻ns
Aperture Delay 30 ✻ns
Aperture Jitter 100 ✻ps
Internal Clock Frequency SHDN = VDD 2.4 ✻MHz
External Clock Frequency 0.024 2.4 ✻✻MHz
Data Transfer Only 0 2.4 ✻✻MHz
DYNAMIC CHARACTERISTICS
Total Harmonic Distortion(2) VIN = 5Vp-p at 10kHz –95 ✻dB
Signal-to-(Noise + Distortion) VIN = 5Vp-p at 10kHz 86 ✻dB
Spurious-Free Dynamic Range VIN = 5Vp-p at 10kHz 97 ✻dB
Channel-to-Channel Isolation VIN = 5Vp-p at 50kHz 100 ✻dB
REFERENCE INPUT
Range 0.5 +VCC/2 ✻✻V
Resistance DCLK Static 5 ✻GΩ
Input Current 40 100 ✻✻ µA
fSAMPLE = 12.5kHz 2.5 ✻µA
DCLK Static 0.001 3 ✻✻ µA
DIGITAL INPUT/OUTPUT
Logic Family CMOS ✻
Logic Levels
VIH | IIH | ≤ +5µA 3.0 5.5 ✻✻V
VIL | IIL | ≤ +5µA–0.3 +0.8 ✻✻V
VOH IOH = –250µA 3.5 ✻V
VOL IOL = 250µA 0.4 ✻V
Data Format Binary Two’s Complement ✻
POWER-SUPPLY REQUIREMENTS
+VCC Specified Performance 4.75 5.25 ✻✻V
Quiescent Current 1.5 2.0 ✻mA
fSAMPLE = 10kHz 150 ✻µA
Power-Down Mode
(3, 4)
,
CS
= +V
CC
3✻µA
Power Dissipation 7.5 10 ✻mW
TEMPERATURE RANGE
Specified Performance –40 +85 ✻✻°C
ADS8343
4SBAS183C
www.ti.com
ELECTRICAL CHARACTERISTICS: +2.7V
At TA = –40°C to +85°C, +VCC = +2.7V, VREF = +1.25V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.
ADS8343E ADS8343EB
✻ Same specifications as ADS8343E.
NOTES: (1) LSB means Least Significant Bit. With VREF equal to +1.25V, one LSB is 38µV. (2) First nine harmonics of the test frequency. (3) Auto power-down mode
(PD1 = PD0 = 0) active or SHDN = GND. (4) Power-down after conversion mode with external clock gated ‘HIGH’.
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
RESOLUTION 16 ✻BITS
ANALOG INPUT
Full-Scale Input Span Positive Input-Negative Input –VREF +VREF ✻✻V
Absolute Input Range Positive Input –0.2 +VCC + 0.2 ✻✻V
Negative Input –0.2 +VCC + 0.2 ✻✻V
Capacitance 25 ✻pF
Leakage Current ±1✻µA
SYSTEM PERFORMANCE
No Missing Codes 14 15 Bits
Integral Linearity Error ±12 ±8LSB
Bipolar Error ±1±0.5 mV
Bipolar Error Match 1.2 4.0 ✻✻ LSB
Gain Error ±0.05 ±0.0024 % of FSR
Gain Error Match 1.0 4.0 ✻✻ LSB
Noise 20 ✻µVrms
Power-Supply Rejection +2.7 < VCC < +3.3V 3 ✻LSB(1)
SAMPLING DYNAMICS
Conversion Time 16 ✻Clk Cycles
Acquisition Time 4.5 ✻Clk Cycles
Throughput Rate 100 ✻kHz
Multiplexer Settling Time 500 ✻ns
Aperture Delay 30 ✻ns
Aperture Jitter 100 ✻ps
Internal Clock Frequency SHDN = VDD 2.4 ✻MHz
External Clock Frequency 0.024 2.4 ✻✻MHz
When Used with Internal Clock 0.024 2.0 ✻✻MHz
Data Transfer Only 0 2.4 ✻✻MHz
DYNAMIC CHARACTERISTICS
Total Harmonic Distortion(2) VIN = 2.5Vp-p at 1kHz –94 ✻dB
Signal-to-(Noise + Distortion) VIN = 2.5Vp-p at 1kHz 81 ✻dB
Spurious-Free Dynamic Range VIN = 2.5Vp-p at 1kHz 98 ✻dB
Channel-to-Channel Isolation VIN = 2.5Vp-p at 10kHz 100 ✻dB
REFERENCE INPUT
Range 0.5 +VCC/2 ✻✻V
Resistance DCLK Static 5 ✻GΩ
Input Current 13 40 ✻✻ µA
fSAMPLE = 12.5kHz 2.5 ✻µA
DCLK Static 0.001 3 ✻✻ µA
DIGITAL INPUT/OUTPUT
Logic Family CMOS ✻
Logic Levels
VIH | IIH | ≤ +5µA+V
CC • 0.7 5.5 ✻✻V
VIL | IIL | ≤ +5µA–0.3 +0.8 ✻✻V
VOH IOH = –250µA+V
CC • 0.8 ✻V
VOL IOL = 250µA 0.4 ✻V
Data Format Binary Two’s Complement ✻
POWER-SUPPLY REQUIREMENTS
+VCC Specified Performance 2.7 3.6 ✻✻V
Quiescent Current 1.2 1.85 ✻✻ mA
fSAMPLE = 10kHz 105 µA
Power-Down Mode
(3, 4)
,
CS
= +V
CC
3✻µA
Power Dissipation 3.2 5 ✻mW
TEMPERATURE RANGE
Specified Performance –40 +85 ✻✻°C
ADS8343 5
SBAS183C www.ti.com
TYPICAL CHARACTERISTICS: +5V
At TA = +25°C, +VCC = +5V, VREF = +2.5V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.
0
–20
–40
–60
–80
–100
–120
–140
FREQUENCY SPECTRUM
(4096 Point FFT; f
IN
= 1.001kHz, –0.2dB)
0502010 4030
Frequency (kHz)
Amplitude (dB)
0
–20
–40
–60
–80
–100
–120
–140
FREQUENCY SPECTRUM
(4096 Point FFT; f
IN
= 9.985kHz, –0.2dB)
0502010 4030
Frequency (kHz)
Amplitude (dB)
SIGNAL-TO-NOISE RATIO AND
SIGNAL-TO-(NOISE + DISTORTION)
vs INPUT FREQUENCY
101 100
Frequency (kHz)
SNR and SINAD (dB)
100
90
80
70
60
SNR
SINAD
SPURIOUS-FREE DYNAMIC RANGE AND
TOTAL HARMONIC DISTORTION
vs INPUT FREQUENCY
101 100
Frequency (kHz)
SFDR (dB)
110
100
90
80
70
60
THD (dB)
–110
–100
–90
–80
–70
–60
SFDR
THD(1)
NOTE: (1) First nine harmonics of the input frequency.
EFFECTIVE NUMBER OF BITS
vs INPUT FREQUENCY
101 100
Frequency (kHz)
Effective Number of Bits
15.0
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
Temperature (°C)
0.1
0
–0.1
–0.2
–0.3
CHANGE IN SIGNAL-TO-(NOISE + DISTORTION)
vs TEMPERATURE
25 100–50 –25 0 50 75
Delta from 25°C (dB)
f
IN
= 4.956kHz, –0.2dB
ADS8343
6SBAS183C
www.ti.com
TYPICAL CHARACTERISTICS: +5V (Cont.)
At TA = +25°C, +VCC = +5V, VREF = +2.5V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.
Output Code
3
2
1
0
–1
–2
–3
–4
INTEGRAL LINEARITY ERROR vs CODE
0000
H
7FFF
H
8000
H
C000
H
4000
H
ILE (LSBs)
Output Code
4
3
2
1
0
–1
–2
–3
DIFFERENTIAL LINEARITY ERROR vs CODE
0000
H
7FFF
H
8000
H
C000
H
4000
H
DLE (LSBs)
SUPPLY CURRENT vs TEMPERATURE
–50 –25 0 25 50 75 100
Temperature (°C)
Supply Current (mA)
1.6
1.5
1.4
1.3
1.2
CHANGE IN BPZ vs TEMPERATURE
–50 –25 0 25 50 75 100
Temperature (°C)
Delta from 25°C (LSBs)
1
0
–1
–2
–3
–4
CHANGE IN GAIN vs TEMPERATURE
–50 –25 0 25 50 75 100
Temperature (°C)
Delta from 25°C (LSBs)
1.0
0.5
0
–0.5
WORST-CASE CHANNEL-TO-CHANNEL
BPZ MATCH vs TEMPERATURE
–50 –25 0 25 50 75 100
Temperature (°C)
BPZ Match (LSBs)
4.5
4.0
3.5
3.0
ADS8343 7
SBAS183C www.ti.com
TYPICAL CHARACTERISTICS: +5V (Cont.)
At TA = +25°C, +VCC = +5V, VREF = +2.5V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.
WORST CASE CHANNEL-TO-CHANNEL
GAIN MATCH vs TEMPERATURE
–50 –25 0 25 50 75 100
Temperature (°C)
Gain Match (LSBs)
0.4
0.3
0.2
0.1
0
–0.1
COMMON-MODE REJECTION vs FREQUENCY
1 10 1000.1 Frequency (kHz)
CMRR (dB)
100
90
80
70
60
50
VCM = 2Vp-p Sinewave
Centered Around VREF
TYPICAL CHARACTERISTICS: +2.7V
At TA = +25°C, +VCC = +2.7V, VREF = +1.25V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.
0
–20
–40
–60
–80
–100
–120
–140
FREQUENCY SPECTRUM
(4096 Point FFT; f
IN
= 1.001kHz, –0.2dB)
0502010 4030
Frequency (kHz)
Amplitude (dB)
0
–20
–40
–60
–80
–100
–120
–140
FREQUENCY SPECTRUM
(4096 Point FFT; f
IN
= 9.985kHz, –0.2dB)
0502010 4030
Frequency (kHz)
Amplitude (dB)
SIGNAL-TO-NOISE RATIO AND
SIGNAL-TO-(NOISE + DISTORTION)
vs INPUT FREQUENCY
101 100
Frequency (kHz)
SNR and SINAD (dB)
95
85
75
65
55
SNR
SINAD
SPURIOUS-FREE DYNAMIC RANGE AND
TOTAL HARMONIC DISTORTION
vs INPUT FREQUENCY
101 100
Frequency (kHz)
SFDR (dB)
100
90
80
70
60
500
THD (dB)
–100
–90
–80
–70
–60
–50
SFDR
THD(1)
NOTE: (1) First nine harmonics of the input frequency.
ADS8343
8SBAS183C
www.ti.com
CHANGE IN BPZ vs TEMPERATURE
–50 –25 0 25 50 75 100
Temperature (°C)
Delta from 25°C (LSBs)
1.0
0.5
0
–0.5
–1.0
SUPPLY CURRENT vs TEMPERATURE
–50 –25 0 25 50 75 100
Temperature (°C)
Supply Current (mA)
1.2
1.1
1.0
0.9
Output Code
4
3
2
1
0
–1
–2
–3
DIFFERENTIAL LINEARITY ERROR vs CODE
0000
H
7FFF
H
8000
H
C000
H
4000
H
DLE (LSBs)
Output Code
3
2
1
0
–1
–2
–3
INTEGRAL LINEARITY ERROR vs CODE
0000
H
7FFF
H
8000
H
C000
H
4000
H
ILE (LSBs)
TYPICAL CHARACTERISTICS: +2.7V (Cont.)
At TA = +25°C, +VCC = +2.7V, VREF = +1.25V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.
EFFECTIVE NUMBER OF BITS
vs INPUT FREQUENCY
101 100
Frequency (kHz)
Effective Number of Bits
14.0
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
9.5
9.0
Temperature (°C)
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
CHANGE IN SIGNAL-TO-(NOISE + DISTORTION)
vs TEMPERATURE
25 100–50 –25 0 50 75
Delta from 25°C (dB)
f
IN
= 4.956kHz, –0.2dB
ADS8343 9
SBAS183C www.ti.com
TYPICAL CHARACTERISTICS: +2.7V (Cont.)
At TA = +25°C, +VCC = +2.7V, VREF = +1.25V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.
WORST-CASE CHANNEL-TO-CHANNEL
BPZ MATCH vs TEMPERATURE
–50 –25 0 25 50 75 100
Temperature (°C)
BPZ Match (LSBs)
1.5
1.0
0.5
0
CHANGE IN GAIN vs TEMPERATURE
–50 –25 0 25 50 75 100
Temperature (°C)
Delta from 25°C (LSBs)
0.5
0
–0.5
–1.0
+VSS (V)
1.4
1.3
1.2
1.1
1.0
SUPPLY CURRENT vs +VSS
3.5 5.02.5 3.0 4.0 4.5
Supply Current (mA)
fSAMPLE = 100kHz
Temperature (°C)
140
120
100
80
60
40
20
0
POWER-DOWN SUPPLY CURRENT
vs TEMPERATURE
–50 –25 0 25 50 75 100
Supply Current (mA)
External Clock Disabled
COMMON-MODE REJECTION vs FREQUENCY
1 10 1000.1 Frequency (kHz)
CMRR (dB)
80
70
60
50
40
VCM = 1Vp-p Sinewave
Centered Around VREF
WORST-CASE CHANNEL-TO-CHANNEL
GAIN MATCH vs TEMPERATURE
–50 –25 0 25 50 75 100
Temperature (°C)
Gain Match (LSBs)
0.16
0.15
0.14
0.13
0.12
ADS8343
10 SBAS183C
www.ti.com
THEORY OF OPERATION
The ADS8343 is a classic Successive Approximation Register
(SAR) A/D converter. The architecture is based on capacitive
redistribution which inherently includes a sample-and-hold func-
tion. The converter is fabricated on a 0.6µm CMOS process.
The basic operation of the ADS8343 is shown in Figure 1.
The device requires an external reference and an external
clock. It operates from a single supply of 2.7V to 5.25V. The
external reference can be any voltage between 500mV and
+VCC/2. The value of the reference voltage directly sets the
input range of the converter. The average reference input
current depends on the conversion rate of the ADS8343.
The analog input to the converter is differential and is
provided via a 4-channel multiplexer. The input can be
provided in reference to a voltage on the COM pin (which is
generally VREF) or differentially by using two of the four input
channels (CH0-CH3). The particular configuration is select-
able via the digital interface.
ANALOG INPUT
The analog input is bipolar and fully differential. There are
two general methods of driving the analog input of the
ADS8343: single-ended or differential, as shown in Figure 2.
FIGURE 2. Methods of Driving the ADS8343—Single-Ended
or Differential.
FIGURE 1. Basic Operation of the ADS8343.
TYPICAL CHARACTERISTICS: +2.7V (Cont.)
At TA = +25°C, +VCC = +2.7V, VREF = +1.25V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE = 2.4MHz, unless otherwise noted.
Sampling Frequency (kHz)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
SUPPLY CURRENT vs SAMPLING FREQUENCY
10 20 30 40 50 60 70 80 90 100
Supply Current (mA)
f
CLK
= 2.4MHz
V
SS
= 5.0V
V
SS
= 2.7V
Power-Down After Conversion Mode.
External Clock Gated HIGH After Conversion.
+V
CC
CH0
CH1
CH2
CH3
COM
SHDN
V
REF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DCLK
CS
DIN
BUSY
DOUT
GND
GND
+V
CC
Chip Select
Serial Data In
Serial Data Out
Serial/Conversion
Clock
1µF
0.1µF
+2.7V to +5V ADS8343
Single-ended
or differential
analog inputs.
V
REF
+1µF
to
10µF
ADS8343
ADS8343
Single-Ended Input
CHX
COM
CHX+
CHX–
±V
REF(1)
Differential Input
NOTE: (1) Relative to common-mode voltage.
Common-Mode
Voltage
Common-Mode
Voltage
(typically V
REF
)
±V
REF(1)
2
±
V
REF(1)
2
ADS8343 11
SBAS183C www.ti.com
When the input is single-ended, the COM input is held at a
fixed voltage. The CHX input swings around the same
voltage and the peak-to-peak amplitude is 2 • V
REF. The
value of VREF determines the range over which the common
voltage may vary, as shown in Figure 3.
FIGURE 4. Differential Input—Common Voltage Range vs V
REF.
0.0 1.0 1.5 2.0 2.5
VREF (V)
4.2
VCC = 5V
0.8
5.2
Common Voltage Range (V)
0
1
2
3
4
5
Differential Input
0.2
FIGURE 3. Single-Ended Input—Common Voltage Range vs V
REF
.
0.5 1.0 1.5 2.0 2.5
V
REF
(V)
Common Voltage Range (V)
–1
0
1
2
3
4
5
2.8
2.1
V
CC
= 5V
Single-Ended Input
0.1
4.9
When the input is differential, the amplitude of the input is the
difference between the CHX and COM input. A voltage or
signal is common to both of these inputs. The peak-to-peak
amplitude of each input is VREF about this common voltage.
However, since the inputs are 180° out-of-phase, the peak-
to-peak amplitude of the difference voltage is 2 • VREF. The
value of VREF also determines the range of the voltage that
may be common to both inputs, as shown in Figure 4.
In each case, care should be taken to ensure that the output
impedance of the sources driving the CHX and COM inputs
are matched. If this is not observed, the two inputs could
have different settling times. This may result in offset error,
gain error, and linearity error which change with both tem-
perature and input voltage. If the impedance cannot be
matched, the errors can be lessened by giving the ADS8343
additional acquisition time.
The input current on the analog inputs depends on a number
of factors: sample rate, input voltage, and source impedance.
Essentially, the current into the ADS8343 charges the inter-
nal capacitor array during the sample period. After this
capacitance has been fully charged, there is no further input
current.
Care must be taken regarding the absolute analog input
voltage. Outside of these ranges, the converter’s linearity
may not meet specifications. Please refer to the electrical
characteristics table for min/max ratings.
REFERENCE INPUT
The external reference sets the analog input range. The
ADS8343 will operate with a reference in the range of 500mV
to +VCC/2. Keep in mind that the analog input is the differ-
ence between the CHX input and the COM input, as shown
in Figure 5. For example, in the single-ended mode, with
VREF and COM pin set to 1.25V, the selected input channel
(CH0-CH3) will properly digitize a signal in the range of 0V to
2.50V relative to GND. If the COM pin is connected to 2.0V,
the input range on the selected channel is 0.75V to 3.25V.
FIGURE 5. Simplified Diagram of the Analog Input.
Converter
+IN
–IN
CH0
CH1
CH2
CH3
COM
A2-A0
(Shown 001B)
SGL/DIF
(Shown HIGH)
There are several critical items concerning the reference
input and its wide voltage range. As the reference voltage is
reduced, the analog voltage weight of each digital output
code is also reduced. This is often referred to as the LSB
(Least Significant Bit) size and is equal to the reference
voltage divided by 65,536. Any offset or gain error inherent
in the A/D converter will appear to increase, in terms of LSB
ADS8343
12 SBAS183C
www.ti.com
A2 A1 A0 CH0 CH1 CH2 CH3 COM
001+IN–IN
101–IN +IN
010 +IN–IN
110 –IN +IN
TABLE IV. Differential Channel Control (SGL/DIF LOW).
Bit 7 Bit 0
(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB)
S A2A1A0—
SGL/DIF
PD1 PD0
TABLE I. Order of the Control Bits in the Control Byte.
TABLE II. Descriptions of the Control Bits within the Control Byte.
BIT NAME DESCRIPTION
7 S Start Bit. Control byte starts with first HIGH bit on
DIN.
6-4 A2-A0 Channel Select Bits. Along with the
SGL/DIF
bit,
these bits control the setting of the multiplexer input.
2
SGL/DIF
Single-Ended/Differential Select Bit. Along with bits
A2-A0, this bit controls the setting of the multiplexer
input.
1-0 PD1-PD0 Power-Down Mode Select Bits. See Table V for
details.
A2 A1 A0 CH0 CH1 CH2 CH3 COM
001+IN –IN
101 +IN –IN
010 +IN –IN
110 +IN–IN
TABLE III. Single-Ended Channel Selection (SGL/DIF HIGH).
size, as the reference voltage is reduced. For example, if the
offset of a given converter is 2LSBs with a 2.5V reference,
then it will typically be 10LSBs with a 0.5V reference. In each
case, the actual offset of the device is the same, 76µV.
The noise or uncertainty of the digitized output will increase
with lower LSB size. With a reference voltage of 500mV, the
LSB size is 7.6µV. This level is below the internal noise of the
device. As a result, the digital output code will not be stable
and vary around a mean value by a number of LSBs. The
distribution of output codes will be gaussian and the noise
can be reduced by simply averaging consecutive conversion
results or applying a digital filter.
With a lower reference voltage, care should be taken to
provide a clean layout including adequate bypassing, a clean
(low-noise, low-ripple) power supply, a low-noise reference,
and a low-noise input signal. Because the LSB size is lower,
the converter will also be more sensitive to nearby digital
signals and electromagnetic interference.
The voltage into the VREF input is not buffered and directly
drives the Capacitor Digital-to-Analog Converter (CDAC)
portion of the ADS8343. Typically, the input current is 13µA
with a 2.5V reference. This value will vary by microamps
depending on the result of the conversion. The reference
current diminishes directly with both conversion rate and
reference voltage. As the current from the reference is drawn
on each bit decision, clocking the converter more quickly
during a given conversion period will not reduce overall
current drain from the reference.
DIGITAL INTERFACE
Figure 6 shows the typical operation of the ADS8343’s digital
interface. This diagram assumes that the source of the digital
signals is a microcontroller or digital signal processor with a
basic serial interface (note that the digital inputs are over-
voltage tolerant up to 5.5V, regardless of +VCC). Each com-
munication between the processor and the converter con-
sists of eight clock cycles. One complete conversion can be
accomplished with three serial communications, for a total of
24 clock cycles on the DCLK input.
The first eight cycles are used to provide the control byte via
the DIN pin. When the converter has enough information
about the following conversion to set the input multiplexer
appropriately, it enters the acquisition (sample) mode. After
three more clock cycles, the control byte is complete and the
converter enters the conversion mode. At this point, the input
sample-and-hold goes into the hold mode. The next 16 clock
cycles accomplish the actual A/D conversion.
Control Byte
Also shown in Figure 6 is the placement and order of the
control bits within the control byte. Tables I and II give
detailed information about these bits. The first bit, the ‘S’ bit,
must always be HIGH and indicates the start of the control
byte. The ADS8343 will ignore inputs on the DIN pin until the
start bit is detected. The next three bits (A2-A0) select the
active input channel or channels of the input multiplexer, as
shown in Tables III and IV and Figure 5.
FIGURE 6. Conversion Timing, 24-Clocks per Conversion, 8-Bit Bus Interface. No DCLK delay required with dedicated serial port.
t
ACQ
AcquireIdle Conversion
1DCLK
CS
81
15
DOUT
BUSY
(MSB)
(START)
(LSB)
A2S
DIN A1 A0
SGL/
DIF
PD1 PD0
14131211109 8 7654321 0 Zero Filled...
81 8
AcquireIdle Conversion
181
15
(MSB)
(START)
A2SA1A0
SGL/
DIF
PD1 PD0
14
ADS8343 13
SBAS183C www.ti.com
Clock Modes
The ADS8343 can be used with an external serial clock or an
internal clock to perform the successive-approximation con-
version. In both clock modes, the external clock shifts data
in and out of the device. Internal clock mode is selected
when PD1 is HIGH and PD0 is LOW.
If the user decides to switch from one clock mode to the
other, an extra conversion cycle will be required before the
The SGL/DIF bit controls the multiplexer input mode: either
single-ended (HIGH) or differential (LOW). In single-ended
mode, the selected input channel is referenced to the COM
pin. In differential mode, the two selected inputs provide a
differential input. See Tables III and IV and Figure 5 for more
information. The last two bits (PD1-PD0) select the power-
down mode as shown in Table V. If both inputs are HIGH, the
device is always powered up. If both inputs are LOW, the
device enters a power-down mode between conversions.
When a new conversion is initiated, the device will resume
normal operation instantly—no delay is needed to allow the
device to power up and the very first conversion will be valid.
PD1 PD0 DESCRIPTION
0 0 Power-down between conversions. When each
conversion is finished, the converter enters a low-
power mode. At the start of the next conversion,
the device instantly powers up to full power. There
is no need for additional delays to assure full
operation and the very first conversion is valid.
1 0 Selects internal clock mode.
0 1 Reserved for future use.
1 1 No power-down between conversions, device al-
ways powered. Selects external clock mode.
TABLE V. Power-Down Selection.
ADS8343 can switch to the new mode. The extra cycle is
required because the PD0 and PD1 control bits need to be
written to the ADS8343 prior to the change in clock modes.
When power is first applied to the ADS8343, the user must
set the desired clock mode. It can be set by writing PD1 = 1
and PD0 = 0 for internal clock mode or PD1 = 1 and PD0
= 1 for external clock mode. After enabling the required clock
mode, only then should the ADS8343 be set to power-down
between conversions (i.e., PD1 = PD0 = 0). The ADS8343
maintains the clock mode it was in prior to entering the
power-down modes.
External Clock Mode
In external clock mode, the external clock not only shifts data
in and out of the ADS8343, it also controls the A/D conver-
sion steps. BUSY will go HIGH for one clock period after the
last bit of the control byte is shifted in. Successive-approxi-
mation bit decisions are made and appear at DOUT on each
of the next 16 DCLK falling edges, see Figure 6. Figure 7
shows the BUSY timing in external clock mode.
Since one clock cycle of the serial clock is consumed with
BUSY going HIGH (while the MSB decision is being made),
16 additional clocks must be given to clock out all 16 bits of
data; thus, one conversion takes a minimum of 25 clock
cycles to fully read the data. Since most microprocessors
communicate in 8-bit transfers, this means that an additional
transfer must be made to capture the LSB.
There are two ways of handling this requirement. One is
presented in Figure 6, where the beginning of the next
control byte appears at the same time the LSB is being
clocked out of the ADS8343. This method allows for maxi-
mum throughput and 24 clock cycles per conversion.
FIGURE 7. Detailed Timing Diagram.
PD0
t
BDV
t
DH
t
CH
t
CL
t
DS
t
CSS
t
DV
t
BD
t
BD
t
TR
t
BTR
t
D0
t
CSH
DCLK
CS
15DOUT
BUSY
DIN
14
ADS8343
14 SBAS183C
www.ti.com
SYMBOL DESCRIPTION MIN TYP MAX UNITS
tACQ Acquisition Time 1.5 µs
tDS DIN Valid Prior to DCLK Rising 100 ns
tDH DIN Hold After DCLK HIGH 10 ns
tDO DCLK Falling to DOUT Valid 200 ns
tDV
CS
Falling to DOUT Enabled 200 ns
tTR
CS
Rising to DOUT Disabled 200 ns
tCSS
CS
Falling to First DCLK Rising 100 ns
tCSH
CS
Rising to DCLK Ignored 0 ns
tCH DCLK HIGH 200 ns
tCL DCLK LOW 200 ns
tBD DCLK Falling to BUSY Rising 200 ns
tBDV
CS
Falling to BUSY Enabled 200 ns
tBTR
CS
Rising to BUSY Disabled 200 ns
TABLE VI. Timing Specifications (+VCC = +2.7V to 3.6V,
TA = –40°C to +85°C, CLOAD = 50pF).
SYMBOL DESCRIPTION MIN TYP MAX UNITS
tACQ Acquisition Time 1.7 µs
tDS DIN Valid Prior to DCLK Rising 50 ns
tDH DIN Hold After DCLK HIGH 10 ns
tDO DCLK Falling to DOUT Valid 100 ns
tDV
CS
Falling to DOUT Enabled 70 ns
tTR
CS
Rising to DOUT Disabled 70 ns
tCSS
CS
Falling to First DCLK Rising 50 ns
tCSH
CS
Rising to DCLK Ignored 0 ns
tCH DCLK HIGH 150 ns
tCL DCLK LOW 150 ns
tBD DCLK Falling to BUSY Rising 100 ns
tBDV
CS
Falling to BUSY Enabled 70 ns
tBTR
CS
Rising to BUSY Disabled 70 ns
TABLE VII. Timing Specifications (+VCC = +4.75V to +5.25V,
TA = –40°C to +85°C, CLOAD = 50pF).
The other method is shown in Figure 8, which uses 32 clock
cycles per conversion; the last seven clock cycles simply
shift out zeros on the DOUT line. BUSY and DOUT go into
a high-impedance state when
CS
goes HIGH; after the next
CS
falling edge, BUSY will go LOW.
Internal Clock Mode
In internal clock mode, the ADS8343 generates its own
conversion clock internally. This relieves the microprocessor
from having to generate the SAR conversion clock and
allows the conversion result to be read back at the processor’s
convenience, at any clock rate from 0MHz to 2.0MHz. BUSY
goes LOW at the start of conversion and then returns HIGH
when the conversion is complete. During the conversion,
BUSY will remain LOW for a maximum of 8µs. Also, during
the conversion, DCLK should remain LOW to achieve the
best noise performance. The conversion result is stored in an
internal register; the data may be clocked out of this register
any time after the conversion is complete.
If
CS
is LOW when BUSY goes LOW following a conversion,
the next falling edge of the external serial clock will write out
the MSB on the DOUT line. The remaining bits (D14-D0) will
be clocked out on each successive clock cycle following the
MSB. If
CS
is HIGH when BUSY goes LOW then the DOUT
line will remain in tri-state until
CS
goes LOW, as shown in
Figure 9.
CS
does not need to remain LOW once a conver-
sion has started. Note that BUSY is not tri-stated when
CS
goes HIGH in internal clock mode.
Data can be shifted in and out of the ADS8343 at clock rates
exceeding 2.4MHz, provided that the minimum acquisition time
tACQ, is kept above 1.7µs.
Digital Timing
Figure 4 and Tables VI and VII provide detailed timing for the
digital interface of the ADS8343.
FIGURE 9. Internal Clock Mode Timing.
t
ACQ
AcquireIdle Conversion
1
DCLK
CS
8
9 1011121314151617181920212223242526272829303132
15
DOUT
BUSY
(MSB)
(START)
(LSB)
A2S
DIN
A1 A0
SGL/
DIF
PD1 PD0
14131211109 8 7654321 0 Zero Filled...
FIGURE 8. External Clock Mode 32 Clocks Per Conversion.
t
ACQ
AcquireIdle Conversion
1
DCLK
CS
81
15
DOUT
BUSY
(MSB)
(START)
(LSB)
A2S
DIN
A1 A0
SGL/
DIF
PD1 PD0
14131211109 8 7654321 0
81 8
Idle
18
Zero Filled...
ADS8343 15
SBAS183C www.ti.com
DATA FORMAT
The output data from the ADS8343 is in Binary Two’s
Complement format, as shown in Table VIII. This table
represents the ideal output code for the given input voltage
and does not include the effects of offset, gain, or noise.
POWER DISSIPATION
There are three power modes for the ADS8343: full-power
(PD1 = PD0 = 1B), auto power-down (PD1 = PD0 = 0B), and
shutdown (
SHDN
LOW). The affects of these modes varies
depending on how the ADS8343 is being operated. For
example, at full conversion rate and 24-clocks per conver-
sion, there is very little difference between full-power mode
and auto power-down, a shutdown (
SHDN
LOW) will not
lower power dissipation.
When operating at full-speed and 24 clocks per conversion
(see Figure 6), the ADS8343 spends most of its time acquir-
ing or converting. There is little time for auto power-down,
assuming that this mode is active. Thus, the difference
between full-power mode and auto power-down is negligible.
If the conversion rate is decreased by simply slowing the
frequency of the DCLK input, the two modes remain approxi-
mately equal. However, if the DCLK frequency is kept at the
maximum rate during a conversion, but conversion are sim-
ply done less often, then the difference between the two
modes is dramatic. Figure 10 shows the difference between
reducing the DCLK frequency (“scaling” DCLK to match the
conversion rate) or maintaining DCLK at the highest fre-
quency and reducing the number of conversion per second.
In the later case, the converter spends an increasing per-
centage of its time in power-down mode (assuming the auto
power-down mode is active).
DESCRIPTION ANALOG VALUE
Full-Scale Range 2 • VREF
Least Significant 2 • VREF/65536
Bit (LSB) BINARY CODE HEX CODE
+Full-Scale +VREF – 1LSB 0111 1111 1111 1111 7FFF
Midscale 0V 0000 0000 0000 0000 0000
Midscale – 1LSB 0V – 1LSB 1111 1111 1111 1111 FFFF
–Full-Scale –VREF 1000 0000 0000 0000 8000
DIGITAL OUTPUT
BINARY TWO’S COMPLEMENT
TABLE VIII. Ideal Input Voltages and Output Codes.
FIGURE 10. Supply Current versus Directly Scaling the Fre-
quency of DCLK with Sample Rate or Keeping
DCLK at the Maximum Possible Frequency.
10k 100k1k 1M
fSAMPLE (Hz)
Supply Current (µA)
100
10
1
1000
fCLK = 2.4MHz
fCLK = 24 • fSAMPLE
TA = 25°C
+VCC = +2.7V
VREF = +2.5V
PD1 = PD0 = 0
FIGURE 11. Supply Current vs State of
CS
.
10k 100k1k 1M
fSAMPLE (Hz)
Supply Current (µA)
0.00
0.09
14
0
2
4
6
8
10
12
CS LOW
(GND)
CS HIGH (+VCC)
TA = 25°C
+VCC = +2.7V
VREF = +2.5V
fCLK = 24 • fSAMPLE
PD1 = PD0 = 0
If DCLK is active and
CS
is LOW while the ADS8343 is in
auto power-down mode, the device will continue to dissipate
some power in the digital logic. The power can be reduced
to a minimum by keeping
CS
HIGH. The differences in
supply current for these two cases are shown in Figure 11.
Operating the ADS8343 in auto power-down mode will result
in the lowest power dissipation, and there is no conversion
time “penalty” on power-up. The very first conversion will be
valid.
SHDN
can be used to force an immediate power-down.
ADS8343
16 SBAS183C
www.ti.com
NOISE
The noise floor of the ADS8343 itself is extremely low, as can
be seen from Figures 12 and 13, and is much lower than
competing A/D converters. The ADS8343 was tested at both
5V and 2.7V and in both the internal and external clock
modes. A low-level DC input was applied to the analog input
pins and the converter was put through 5000 conversions.
The digital output of the A/D converter will vary in output code
due to the internal noise of the ADS8343. This is true for all
16-bit, SAR-type, A/D converters. Using a histogram to plot
the output codes, the distribution should appear bell-shaped
with the peak of the bell curve representing the nominal code
for the input value. The ±1σ, ±2σ, and ±3σ distributions will
represent the 68.3%, 95.5%, and 99.7%, respectively, of all
codes. The transition noise can be calculated by dividing the
number of codes measured by 6 and this will yield the ±3σ
distribution or 99.7% of all codes. Statistically, up to 3 codes
could fall outside the distribution when executing 1000 con-
versions. The ADS8343, with < 3 output codes for the ±3σ
distribution, will yield a < ±0.5LSB transition noise at 5V
operation. Remember, to achieve this low noise perfor-
mance, the peak-to-peak noise of the input signal and
reference must be < 50µV.
FIGURE 12. Histogram of 5000 Conversions of a DC Input at the
Code Transition, 5V Operation External Clock Mode.
FIGURE 13. Histogram of 5000 Conversions of a DC Input at the
Code Center, 2.7V Operation Internal Clock Mode.
3295
774
95 131
705
FFFE
H
FFFF
H
0000
H
0001
H
0002
H
Code
2387
694 905
512
411
38 38
87
FFFEH
FFFDH
FFFCHFFFFH0000H0001H0002H0003H0004H
Code
AVERAGING
The noise of the A/D converter can be compensated by
averaging the digital codes. By averaging conversion results,
transition noise will be reduced by a factor of 1/
√n
, where n
is the number of averages. For example, averaging 4 conver-
sion results will reduce the transition noise by 1/2 to
±0.25LSBs. Averaging should only be used for input signals
with frequencies near DC.
For AC signals, a digital filter can be used to low-pass filter
and decimate the output codes. This works in a similar
manner to averaging; for every decimation by 2, the signal-
to-noise ratio will improve 3dB.
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS8343 circuitry. This is particularly true
if the reference voltage is low and/or the conversion rate is high.
The basic SAR architecture is sensitive to glitches or sudden
changes on the power supply, reference, ground connections,
and digital inputs that occur just prior to latching the output of the
analog comparator. Thus, during any single conversion for an n-
bit SAR converter, there are n “windows” in which large external
transient voltages can easily affect the conversion result. Such
glitches might originate from switching power supplies, nearby
digital logic, and high-power devices. The degree of error in the
digital output depends on the reference voltage, layout, and the
exact timing of the external event. The error can change if the
external event changes in time with respect to the DCLK input.
With this in mind, power to the ADS8343 should be clean and
well bypassed. A 0.1µF ceramic bypass capacitor should be
placed as close to the device as possible. In addition, a 1µF
to 10µF capacitor and a 5Ω or 10Ω series resistor may be
used to low-pass filter a noisy supply.
The reference should be similarly bypassed with a 1µF
capacitor. Again, a series resistor and large capacitor can be
used to low-pass filter the reference voltage. If the reference
voltage originates from an op amp, make sure that it can
drive the bypass capacitor without oscillation (the series
resistor can help in this case). The ADS8343 draws very little
current from the reference on average, but it does place
larger demands on the reference circuitry over short periods
of time (on each rising edge of DCLK during a conversion).
The ADS8343 architecture offers no inherent rejection of
noise or voltage variation in regards to the reference input.
This is of particular concern when the reference input is tied
to the power supply. Any noise and ripple from the supply will
appear directly in the digital results. While high-frequency
noise can be filtered out as discussed in the previous
paragraph, voltage variation due to line frequency (50Hz or
60Hz) can be difficult to remove.
The GND pin should be connected to a clean ground point. In
many cases, this will be the “analog” ground. Avoid connec-
tions which are too near the grounding point of a microcontroller
or digital signal processor. If needed, run a ground trace
directly from the converter to the power-supply entry point. The
ideal layout will include an analog ground plane dedicated to
the converter and associated analog circuitry.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
ADS8343E ACTIVE SSOP DBQ 16 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8343E/2K5 ACTIVE SSOP DBQ 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8343E/2K5G4 ACTIVE SSOP DBQ 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8343EB ACTIVE SSOP DBQ 16 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8343EBG4 ACTIVE SSOP DBQ 16 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS8343EG4 ACTIVE SSOP DBQ 16 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADS8343E/2K5 SSOP DBQ 16 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS8343E/2K5 SSOP DBQ 16 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time
of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
Products Applications
Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive
Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications
Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers
DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps
DSP dsp.ti.com Energy and Lighting www.ti.com/energy
Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Security www.ti.com/security
Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Mobile Processors www.ti.com/omap TI E2E Community e2e.ti.com
Wireless Connectivity www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated
