B
DIR 5
4
A3
VCCA VCCB
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intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC1T45-Q1
SCES677D –SEPTEMBER 2006–REVISED JULY 2017
SN74LVC1T45-Q1 1.65-V to 5.5-V Single-Bit Dual-Supply Level Shifter
1
1 Features
1• Qualified for Automotive Applications
• AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
Range
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C3B
• Fully Configurable Dual-Rail Design Allows Each
Port to Operate Over the Full 1.65-V to 5.5-V
Power-Supply Range
• VCC Isolation Feature – If Either VCC Input Is at
GND, Both Ports Are in the High-Impedance State
• DIR Input Circuit Referenced to VCCA
• ±24-mA Output Drive at 3.3 V
• Ioff Supports Partial-Power-Down Mode Operation
• Maximum Data Rates
– 420 Mbps (3.3-V to 5-V Translation)
– 210 Mbps (Translate to 3.3 V)
– 140 Mbps (Translate to 2.5 V)
– 75 Mbps (Translate to 1.8 V)
2 Applications
• Head Units
• ADAS – Cameras
• Telematics
3 Description
The SN74LVC1T45-Q1 device is a single-bit,
noninverting bus transceiver that uses two separate
configurable power supply rails. The A-port is
designed to track VCCA. VCCA accepts any supply
voltage from 1.65 V to 5.5 V. The B-port is designed
to track VCCB. VCCB accepts any supply voltage from
1.65 V to 5.5 V. This allows for universal low-voltage
bidirectional translation between any of the 1.8-V,
2.5-V, 3.3-V, and 5-V voltage nodes.
The SN74LVC1T45-Q1 device is a single-bit, non-
inverting level translator. The fully configurable dual-
rail design allows each port to overate over the full
1.65-V to 5.5-V power supply range. It is ideal for
applications that need a wide bidirectional translation
range.
The SN74LVC1T45-Q1 is designed so that the DIR
input is powered by VCCA.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
The VCC isolation feature assures that if either VCC
input is at GND, then both ports are in the high-
impedance state.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
SN74LVC1T45-Q1 SC70 (6) 1.25 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
2
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Switching Characteristics: VCCA = 1.8 V ±0.15 V...... 7
6.7 Switching Characteristics: VCCA = 2.5 V ±0.2 V........ 8
6.8 Switching Characteristics: VCCA = 3.3 V ±0.3 V........ 9
6.9 Switching Characteristics: VCCA = 5 V ±0.5 V......... 11
6.10 Typical Characteristics.......................................... 13
7 Parameter Measurement Information ................ 16
8 Detailed Description............................................ 17
8.1 Overview................................................................. 17
8.2 Functional Block Diagram....................................... 17
8.3 Feature Description................................................. 17
8.4 Device Functional Modes........................................ 17
9 Application and Implementation ........................ 18
9.1 Application Information............................................ 18
9.2 Typical Applications ................................................ 18
10 Power Supply Recommendations ..................... 20
11 Layout................................................................... 21
11.1 Layout Guidelines ................................................. 21
11.2 Layout Example .................................................... 21
12 Device and Documentation Support................. 22
12.1 Documentation Support ........................................ 22
12.2 Receiving Notification of Documentation Updates 22
12.3 Community Resources.......................................... 22
12.4 Trademarks........................................................... 22
12.5 Electrostatic Discharge Caution............................ 22
12.6 Glossary................................................................ 22
13 Mechanical, Packaging, and Orderable
Information........................................................... 22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (September 2016) to Revision D Page
• Added Junction temperature, TJin Absolute Maximum Ratings............................................................................................ 4
• Added revised steps for power-up sequence in Power Supply Recommendations ............................................................ 20
Changes from Revision B (September 2012) to Revision C Page
• Changed data sheet title From: SN74LVC1T45-Q1 Single-Bit Dual-Supply Bus Transceiver With Configurable
Voltage Translation and 3-State Outputs To: SN74LVC1T45-Q1 1.65-V to 5.5-V Single-Bit Dual-Supply Level Shifter...... 1
• Added Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes section,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section....................................... 1
• Deleted Ordering Information table; see POA the end of the data sheet............................................................................... 1
1VCCA 6 VCCB
2GND 5 DIR
3A 4 B
Not to scale
3
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(1) G = Ground, I = Input, O = Output, P = Power
5 Pin Configuration and Functions
DCK Package
6-Pin SC70
Top View
See mechanical drawings for dimensions.
Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
A 3 I/O Output level depends on VCC1 voltage
B 4 I/O Input threshold value depends on VCC2 voltage
DIR 5 I GND (low level) determines B-port to A-port direction
GND 2 G Device GND
VCCA 1 P SYSTEM-1 supply voltage (1.65 V to 5.5 V)
VCCB 6 P SYSTEM-2 supply voltage (1.65 V to 5.5 V)
4
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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) The value of VCC is provided in Recommended Operating Conditions.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage, VCCA, VCCB –0.5 6.5 V
Input voltage, VI(2) –0.5 6.5 V
Voltage applied to any output in the high-impedance or power-off state, VO(2) –0.5 6.5 V
Voltage applied to any output in the high or low state, VO(2)(3) A port –0.5 VCCA + 0.5 V
B port –0.5 VCCB + 0.5
Input clamp current, IIK (VI< 0) –50 mA
Output clamp current, IOK (VO< 0) –50 mA
Continuous output current, IO±50 mA
Continuous current through VCC or GND ±100 mA
Junction temperature, TJ150 °C
Storage temperature, Tstg –65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±750
(1) VCCI is the VCC associated with the input port.
(2) VCCO is the VCC associated with the output port.
(3) All unused data inputs of the device must be held at VCCI or GND to assure proper device operation. See Implications of Slow or
Floating CMOS Inputs (SCBA004).
(4) For VCCI values not specified in the data sheet, VIH min = VCCI × 0.7 V, VIL max = VCCI × 0.3 V.
(5) For VCCI values not specified in the data sheet, VIH min = VCCA × 0.7 V, VIL max = VCCA × 0.3 V.
6.3 Recommended Operating Conditions
See(1)(2)(3)
MIN MAX UNIT
VCCA Supply voltage 1.65 5.5 V
VCCB Supply voltage 1.65 5.5 V
VIH High-level input voltage,
data inputs(4)
VCCI = 1.65 V to 1.95 V VCCI × 0.65
V
VCCI = 2.3 V to 2.7 V 1.7
VCCI = 3 V to 3.6 V 2
VCCI = 4.5 V to 5.5 V VCCI × 0.7
VIL Low-level input voltage,
data inputs(4)
VCCI = 1.65 V to 1.95 V VCCI × 0.35
V
VCCI = 2.3 V to 2.7 V 0.7
VCCI = 3 V to 3.6 V 0.8
VCCI = 4.5 V to 5.5 V VCCI × 0.3
VIH High-level input voltage,
DIR (referenced to VCCA)(5)
VCCI = 1.65 V to 1.95 V VCCA × 0.65
V
VCCI = 2.3 V to 2.7 V 1.7
VCCI = 3 V to 3.6 V 2
VCCI = 4.5 V to 5.5 V VCCA × 0.7
5
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Recommended Operating Conditions (continued)
See(1)(2)(3)
MIN MAX UNIT
VIL Low-level input voltage,
DIR (referenced to VCCA)(5)
VCCI = 1.65 V to 1.95 V VCCA × 0.35
V
VCCI = 2.3 V to 2.7 V 0.7
VCCI = 3 V to 3.6 V 0.8
VCCI = 4.5 V to 5.5 V VCCA × 0.3
VIInput voltage 0 5.5 V
VOOutput voltage 0 VCCO V
IOH High-level output current
VCCO = 1.65 V to 1.95 V –4
mA
VCCO = 2.3 V to 2.7 V –8
VCCO = 3 V to 3.6 V –24
VCCO = 4.5 V to 5.5 V –32
IOL Low-level output current
VCCO = 1.65 V to 1.95 V 4
mA
VCCO = 2.3 V to 2.7 V 8
VCCO = 3 V to 3.6 V 24
VCCO = 4.5 V to 5.5 V 32
Δt/ΔvInput transition
rise or fall rate Data inputs
VCCI = 1.65 V to 1.95 V 20
ns/V
VCCI = 2.3 V to 2.7 V 20
VCCI = 3 V to 3.6 V 10
VCCI = 4.5 V to 5.5 V 5
Control inputs, VCCI = 1.65 V to 5.5 V 5
TAOperating free-air temperature –40 125 °C
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.4 Thermal Information
THERMAL METRIC(1) SN74LVC1T45-Q1
UNITDCK (SC70)
6 PINS
RθJA Junction-to-ambient thermal resistance 286.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 93.9 °C/W
RθJB Junction-to-board thermal resistance 95.5 °C/W
ψJT Junction-to-top characterization parameter 1.9 °C/W
ψJB Junction-to-board characterization parameter 94.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — °C/W
6
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(1) VCCO is the VCC associated with the output port.
(2) VCCI is the VCC associated with the input port.
(3) Power dissipation capacitance per transceiver
6.5 Electrical Characteristics
over operating free-air temperature range with all limits at TA= –40°C to 125°C (unless otherwise noted)(1)(2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH VI= VIH
IOH = –100 µA, VCCA = 1.65 V to 4.5 V,
VCCB = 1.65 V to 4.5 V VCCO – 0.1
V
IOH = –4 mA, VCCA = 1.65 V, VCCB = 1.65 V 1.2
IOH = –8 mA, VCCA = 2.3 V, VCCB = 2.3 V 1.9
IOH = –24 mA, VCCA = 3 V, VCCB = 3 V 2.3
IOH = –32 mA, VCCA = 4.5 V, VCCB = 4.5 V 3.8
VOL VI= VIL
IOL = 100 µA, VCCA = 1.65 V to 4.5 V,
VCCB = 1.65 V to 4.5 V 0.1
V
IOL = 4 mA, VCCA = 1.65 V, VCCB = 1.65 V 0.45
IOL = 8 mA, VCCA = 2.3 V, VCCB = 2.3 V 0.4
IOL = 24 mA, VCCA = 3 V, VCCB = 3 V 0.65
IOL = 32 mA, VCCA = 4.5 V, VCCB = 4.5 V 0.65
IIDIR at VI= VCCA or GND, VCCA = 1.65 V to 5.5 V,
VCCB = 1.65 V to 5.5 V TA= 25°C ±1 µA
TA= –40°C to 125°C ±4
Ioff VIor VO= 0 to 5.5 V
A port at VCCA = 0 V,
VCCB = 0 to 5.5 V TA= 25°C ±1
µA
TA= –40°C to 125°C ±10
B port at VCCA = 0
to 5.5 V, VCCB = 0 V TA= 25°C ±1
TA= –40°C to 125°C ±10
IOZ A or B port at VO= VCCO or GND,
VCCA = 1.65 V to 5.5 V, VCCB = 1.65 V to 5.5 V TA= 25°C ±1 µA
TA= –40°C to 125°C ±10
ICCA VI= VCCI or GND, IO= 0 VCCA = 1.65 V to 5.5 V, VCCB = 1.65 V to 5.5 V 10 µAVCCA = 5.5 V, VCCB = 0 V 4
VCCA = 0 V, VCCB = 5.5 V –10
ICCB VI= VCCI or GND, IO= 0 VCCA = 1.65 V to 5.5 V, VCCB = 1.65 V to 5.5 V 10 µAVCCA = 5.5 V, VCCB = 0 V –10
VCCA = 0 V, VCCB = 5.5 V 4
ICCA + ICCB VI= VCCI or GND, IO= 0, VCCA = 1.65 V to 5.5 V,
VCCB = 1.65 V to 5.5 V 20 µA
ΔICCA VCCA = 3 V to 5.5 V,
VCCB = 3 V to 5.5 V
A port at VCCA – 0.6 V, DIR at VCCA,
B port = open 50 µA
DIR at VCCA – 0.6 V, B port = open,
A port at VCCA or GND 50
ΔICCB B port at VCCB – 0.6 V, DIR at GND, A port = open, VCCA = 3 V to 5.5 V,
VCCB = 3 V to 5.5 V 50 µA
CiDIR at VI= VCCA or GND, TA= 25°C, VCCA = 3.3 V, VCCB = 3.3 V 2.5 pF
Cio A or B port at VO= VCCA/B or GND, TA= 25°C, VCCA = 3.3 V,
VCCB = 3.3 V 6 pF
CpdA(3) CL= 0 pF,
f = 10 MHz,
tr= tf= 1 ns
A-port input,
B-port output
VCCA = VCCB = 1.8 V 3
pF
VCCA = VCCB = 2.5 V 4
VCCA = VCCB = 3.3 V 4
VCCA = VCCB = 5 V 4
B-port input,
A-port output
VCCA = VCCB = 1.8 V 18
VCCA = VCCB = 2.5 V 19
VCCA = VCCB = 3.3 V 20
VCCA = VCCB = 5 V 21
7
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Electrical Characteristics (continued)
over operating free-air temperature range with all limits at TA= –40°C to 125°C (unless otherwise noted)(1)(2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CpdB(3) CL= 0 pF,
f = 10 MHz,
tr= tf= 1 ns
A-port input,
B-port output
VCCA = VCCB = 1.8 V 18
pF
VCCA = VCCB = 2.5 V 19
VCCA = VCCB = 3.3 V 20
VCCA = VCCB = 5 V 21
B-port input,
A-port output
VCCA = VCCB = 1.8 V 3
VCCA = VCCB = 2.5 V 4
VCCA = VCCB = 3.3 V 4
VCCA = VCCB = 5 V 4
6.6 Switching Characteristics: VCCA = 1.8 V ±0.15 V
over operating free-air temperature range (unless otherwise noted; see Figure 17)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH From A (input) to B (output)
VCCB = 1.8 V ±0.15 V 3 20.7
ns
VCCB = 2.5 V ±0.2 V 2.2 13.3
VCCB = 3.3 V ±0.3 V 1.7 11.3
VCCB = 5 V ±0.5 V 1.4 10.2
tPHL From A (input) to B (output)
VCCB = 1.8 V ±0.15 V 2.8 17.3
ns
VCCB = 2.5 V ±0.2 V 2.2 11.5
VCCB = 3.3 V ±0.3 V 1.8 10.1
VCCB = 5 V ±0.5 V 1.7 10
tPLH From B (input) to A (output)
VCCB = 1.8 V ±0.15 V 3 20.7
ns
VCCB = 2.5 V ±0.2 V 2.3 19
VCCB = 3.3 V ±0.3 V 2.1 18.5
VCCB = 5 V ±0.5 V 1.9 18.1
tPHL From B (input) to A (output)
VCCB = 1.8 V ±0.15 V 2.8 17.3
ns
VCCB = 2.5 V ±0.2 V 2.1 15.9
VCCB = 3.3 V ±0.3 V 2 15.6
VCCB = 5 V ±0.5 V 1.8 15.2
tPHZ From DIR (input) to A (output)
VCCB = 1.8 V ±0.15 V 5.2 22.7
ns
VCCB = 2.5 V ±0.2 V 4.8 21.5
VCCB = 3.3 V ±0.3 V 4.7 21.4
VCCB = 5 V ±0.5 V 5.1 20.1
tPLZ From DIR (input) to A (output)
VCCB = 1.8 V ±0.15 V 2.3 13.5
ns
VCCB = 2.5 V ±0.2 V 2.1 13.5
VCCB = 3.3 V ±0.3 V 2.4 13.7
VCCB = 5 V ±0.5 V 3.1 13.9
tPHZ From DIR (input) to B (output)
VCCB = 1.8 V ±0.15 V 7.4 27.9
ns
VCCB = 2.5 V ±0.2 V 4.9 14.5
VCCB = 3.3 V ±0.3 V 3.6 13.3
VCCB = 5 V ±0.5 V 2.3 11.2
tPLZ From DIR (input) to B (output)
VCCB = 1.8 V ±0.15 V 4.2 19
ns
VCCB = 2.5 V ±0.2 V 2.2 12.2
VCCB = 3.3 V ±0.3 V 2.3 11.4
VCCB = 5 V ±0.5 V 2 9.4
8
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Switching Characteristics: VCCA = 1.8 V ±0.15 V (continued)
over operating free-air temperature range (unless otherwise noted; see Figure 17)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(1) The enable time is a calculated value, derived using the formula shown in Enable Times.
tPZH(1) From DIR (input) to A (output)
VCCB = 1.8 V ±0.15 V 39.7
ns
VCCB = 2.5 V ±0.2 V 31.2
VCCB = 3.3 V ±0.3 V 29.9
VCCB = 5 V ±0.5 V 27.5
tPZL(1) From DIR (input) to A (output)
VCCB = 1.8 V ±0.15 V 45.2
ns
VCCB = 2.5 V ±0.2 V 30.4
VCCB = 3.3 V ±0.3 V 28.9
VCCB = 5 V ±0.5 V 26.4
tPZH(1) From DIR (input) to B (output)
VCCB = 1.8 V ±0.15 V 34.2
ns
VCCB = 2.5 V ±0.2 V 26.8
VCCB = 3.3 V ±0.3 V 25
VCCB = 5 V ±0.5 V 24.1
tPZL(1) From DIR (input) to B (output)
VCCB = 1.8 V ±0.15 V 40.7
ns
VCCB = 2.5 V ±0.2 V 33
VCCB = 3.3 V ±0.3 V 31.5
VCCB = 5 V ±0.5 V 30.1
6.7 Switching Characteristics: VCCA = 2.5 V ±0.2 V
over operating free-air temperature range (unless otherwise noted; see Figure 17)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH From A (input) to B (output)
VCCB = 1.8 V ±0.15 V 2.3 19
ns
VCCB = 2.5 V ±0.2 V 1.5 11.5
VCCB = 3.3 V ±0.3 V 1.3 9.4
VCCB = 5 V ±0.5 V 1.1 8.1
tPHL From A (input) to B (output)
VCCB = 1.8 V ±0.15 V 2.1 15.9
ns
VCCB = 2.5 V ±0.2 V 1.4 10.5
VCCB = 3.3 V ±0.3 V 1.3 8.4
VCCB = 5 V ±0.5 V 0.9 7.6
tPLH From B (input) to A (output)
VCCB = 1.8 V ±0.15 V 2.2 13.3
ns
VCCB = 2.5 V ±0.2 V 1.5 11.5
VCCB = 3.3 V ±0.3 V 1.4 11
VCCB = 5 V ±0.5 V 1 10.5
tPHL From B (input) to A (output)
VCCB = 1.8 V ±0.15 V 2.2 11.5
ns
VCCB = 2.5 V ±0.2 V 1.4 10.7
VCCB = 3.3 V ±0.3 V 1.3 10
VCCB = 5 V ±0.5 V 0.9 9.2
tPHZ From DIR (input) to A (output)
VCCB = 1.8 V ±0.15 V 3 11.1
ns
VCCB = 2.5 V ±0.2 V 2.1 11.1
VCCB = 3.3 V ±0.3 V 2.3 11.1
VCCB = 5 V ±0.5 V 3.2 11.1
tPLZ From DIR (input) to A (output)
VCCB = 1.8 V ±0.15 V 1.3 8.9
ns
VCCB = 2.5 V ±0.2 V 1.3 8.9
VCCB = 3.3 V ±0.3 V 1.3 8.9
VCCB = 5 V ±0.5 V 1 8.8
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Switching Characteristics: VCCA = 2.5 V ±0.2 V (continued)
over operating free-air temperature range (unless otherwise noted; see Figure 17)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(1) The enable time is a calculated value, derived using the formula shown in Enable Times.
tPHZ From DIR (input) to B (output)
VCCB = 1.8 V ±0.15 V 6.5 26.7
ns
VCCB = 2.5 V ±0.2 V 4.1 14.4
VCCB = 3.3 V ±0.3 V 3 13.2
VCCB = 5 V ±0.5 V 1.9 10.1
tPLZ From DIR (input) to B (output)
VCCB = 1.8 V ±0.15 V 3.5 21.9
ns
VCCB = 2.5 V ±0.2 V 2.2 12.6
VCCB = 3.3 V ±0.3 V 2.5 11.4
VCCB = 5 V ±0.5 V 1.6 8.3
tPZH(1) From DIR (input) to A (output)
VCCB = 1.8 V ±0.15 V 35.2
ns
VCCB = 2.5 V ±0.2 V 24.1
VCCB = 3.3 V ±0.3 V 22.4
VCCB = 5 V ±0.5 V 18.8
tPZL(1) From DIR (input) to A (output)
VCCB = 1.8 V ±0.15 V 38.2
ns
VCCB = 2.5 V ±0.2 V 24.9
VCCB = 3.3 V ±0.3 V 23.2
VCCB = 5 V ±0.5 V 19.3
tPZH(1) From DIR (input) to B (output)
VCCB = 1.8 V ±0.15 V 27.9
ns
VCCB = 2.5 V ±0.2 V 20.4
VCCB = 3.3 V ±0.3 V 18.3
VCCB = 5 V ±0.5 V 16.9
tPZL(1) From DIR (input) to B (output)
VCCB = 1.8 V ±0.15 V 27
ns
VCCB = 2.5 V ±0.2 V 21.6
VCCB = 3.3 V ±0.3 V 19.5
VCCB = 5 V ±0.5 V 18.7
6.8 Switching Characteristics: VCCA = 3.3 V ±0.3 V
over operating free-air temperature range (unless otherwise noted; see Figure 17)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH From A (input) to B (output)
VCCB = 1.8 V ±0.15 V 2.1 18.5
ns
VCCB = 2.5 V ±0.2 V 1.4 11
VCCB = 3.3 V ±0.3 V 0.7 8.8
VCCB = 5 V ±0.5 V 0.7 7.4
tPHL From A (input) to B (output)
VCCB = 1.8 V ±0.15 V 2 15.6
ns
VCCB = 2.5 V ±0.2 V 1.3 10
VCCB = 3.3 V ±0.3 V 0.8 8
VCCB = 5 V ±0.5 V 0.7 7
tPLH From B (input) to A (output)
VCCB = 1.8 V ±0.15 V 1.7 11.3
ns
VCCB = 2.5 V ±0.2 V 1.3 9.4
VCCB = 3.3 V ±0.3 V 0.7 8.8
VCCB = 5 V ±0.5 V 0.6 8.4
tPHL From B (input) to A (output)
VCCB = 1.8 V ±0.15 V 1.8 10.1
ns
VCCB = 2.5 V ±0.2 V 1.3 8.4
VCCB = 3.3 V ±0.3 V 0.8 8
VCCB = 5 V ±0.5 V 0.7 7.5
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Switching Characteristics: VCCA = 3.3 V ±0.3 V (continued)
over operating free-air temperature range (unless otherwise noted; see Figure 17)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(1) The enable time is a calculated value, derived using the formula shown in Enable Times.
tPHZ From DIR (input) to A (output)
VCCB = 1.8 V ±0.15 V 2.3 10.3
ns
VCCB = 2.5 V ±0.2 V 2.4 10.3
VCCB = 3.3 V ±0.3 V 1.5 10.3
VCCB = 5 V ±0.5 V 2.4 10.3
tPLZ From DIR (input) to A (output)
VCCB = 1.8 V ±0.15 V 1.8 8.6
ns
VCCB = 2.5 V ±0.2 V 1.6 8.6
VCCB = 3.3 V ±0.3 V 1.9 8.7
VCCB = 5 V ±0.5 V 2 8.7
tPHZ From DIR (input) to B (output)
VCCB = 1.8 V ±0.15 V 5.4 27.5
ns
VCCB = 2.5 V ±0.2 V 3.9 13.1
VCCB = 3.3 V ±0.3 V 2.9 11.8
VCCB = 5 V ±0.5 V 1.7 9.8
tPLZ From DIR (input) to B (output)
VCCB = 1.8 V ±0.15 V 2.3 17.5
ns
VCCB = 2.5 V ±0.2 V 2.1 10.8
VCCB = 3.3 V ±0.3 V 2.4 10.1
VCCB = 5 V ±0.5 V 1.5 7.9
tPZH(1) From DIR (input) to A (output)
VCCB = 1.8 V ±0.15 V 28.8
ns
VCCB = 2.5 V ±0.2 V 20.2
VCCB = 3.3 V ±0.3 V 18.9
VCCB = 5 V ±0.5 V 16.3
tPZL(1) From DIR (input) to A (output)
VCCB = 1.8 V ±0.15 V 37.6
ns
VCCB = 2.5 V ±0.2 V 21.5
VCCB = 3.3 V ±0.3 V 19.8
VCCB = 5 V ±0.5 V 17.3
tPZH(1) From DIR (input) to B (output)
VCCB = 1.8 V ±0.15 V 27.1
ns
VCCB = 2.5 V ±0.2 V 19.6
VCCB = 3.3 V ±0.3 V 17.5
VCCB = 5 V ±0.5 V 16.1
tPZL(1) From DIR (input) to B (output)
VCCB = 1.8 V ±0.15 V 25.9
ns
VCCB = 2.5 V ±0.2 V 20.3
VCCB = 3.3 V ±0.3 V 18.3
VCCB = 5 V ±0.5 V 17.3
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(1) The enable time is a calculated value, derived using the formula shown in Enable Times.
6.9 Switching Characteristics: VCCA = 5 V ±0.5 V
over operating free-air temperature range (unless otherwise noted; see Figure 17)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH From A (input) to B (output)
VCCB = 1.8 V ±0.15 V 1.9 18.1
ns
VCCB = 2.5 V ±0.2 V 1 10.5
VCCB = 3.3 V ±0.3 V 0.6 8.4
VCCB = 5 V ±0.5 V 0.5 6.9
tPHL From A (input) to B (output)
VCCB = 1.8 V ±0.15 V 1.8 15.2
ns
VCCB = 2.5 V ±0.2 V 0.9 9.2
VCCB = 3.3 V ±0.3 V 0.7 7.5
VCCB = 5 V ±0.5 V 0.5 6.5
tPLH From B (input) to A (output)
VCCB = 1.8 V ±0.15 V 1.4 10.2
ns
VCCB = 2.5 V ±0.2 V 1 8.1
VCCB = 3.3 V ±0.3 V 0.7 7.4
VCCB = 5 V ±0.5 V 0.5 6.9
tPHL From B (input) to A (output)
VCCB = 1.8 V ±0.15 V 1.7 10
ns
VCCB = 2.5 V ±0.2 V 0.9 7.6
VCCB = 3.3 V ±0.3 V 0.7 7
VCCB = 5 V ±0.5 V 0.5 6.5
tPHZ From DIR (input) to A (output)
VCCB = 1.8 V ±0.15 V 2.1 8.4
ns
VCCB = 2.5 V ±0.2 V 2 8.4
VCCB = 3.3 V ±0.3 V 2.2 8.5
VCCB = 5 V ±0.5 V 2 8.4
tPLZ From DIR (input) to A (output)
VCCB = 1.8 V ±0.15 V 0.9 6.8
ns
VCCB = 2.5 V ±0.2 V 1 6.8
VCCB = 3.3 V ±0.3 V 1 6.7
VCCB = 5 V ±0.5 V 0.9 6.7
tPHZ From DIR (input) to B (output)
VCCB = 1.8 V ±0.15 V 4.8 26.2
ns
VCCB = 2.5 V ±0.2 V 2.5 14.8
VCCB = 3.3 V ±0.3 V 1 11.5
VCCB = 5 V ±0.5 V 1.7 9.5
tPLZ From DIR (input) to B (output)
VCCB = 1.8 V ±0.15 V 2.6 17.8
ns
VCCB = 2.5 V ±0.2 V 2 10.4
VCCB = 3.3 V ±0.3 V 2.5 10
VCCB = 5 V ±0.5 V 1.6 7.5
tPZH(1) From DIR (input) to A (output)
VCCB = 1.8 V ±0.15 V 28
ns
VCCB = 2.5 V ±0.2 V 18.5
VCCB = 3.3 V ±0.3 V 17.4
VCCB = 5 V ±0.5 V 14.4
tPZL(1) From DIR (input) to A (output)
VCCB = 1.8 V ±0.15 V 36.2
ns
VCCB = 2.5 V ±0.2 V 22.4
VCCB = 3.3 V ±0.3 V 18.5
VCCB = 5 V ±0.5 V 16
tPZH(1) From DIR (input) to B (output)
VCCB = 1.8 V ±0.15 V 24.9
ns
VCCB = 2.5 V ±0.2 V 17.3
VCCB = 3.3 V ±0.3 V 15.1
VCCB = 5 V ±0.5 V 13.6
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Switching Characteristics: VCCA = 5 V ±0.5 V (continued)
over operating free-air temperature range (unless otherwise noted; see Figure 17)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPZL(1) From DIR (input) to B (output)
VCCB = 1.8 V ±0.15 V 23.6
ns
VCCB = 2.5 V ±0.2 V 17.6
VCCB = 3.3 V ±0.3 V 16
VCCB = 5 V ±0.5 V 14.9
0 5 10 15 20 25 30 35
tPHL − ns
CL− pF
0
1
2
3
4
5
6
7
8
9
10
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 5 V
0
1
2
3
4
5
6
7
8
9
10
0 5 10 15 20 25 30 35
tPLH − ns
CL− pF
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 5 V
0 5 10 15 20 25 30 35
tPHL − ns
CL− pF
0
1
2
3
4
5
6
7
8
9
10
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 5 V
0
1
2
3
4
5
6
7
8
9
10
0 5 10 15 20 25 30 35
tPLH − ns
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 5 V
CL− pF
0
1
2
3
4
5
6
7
8
9
0 5 10 15 20 25 30 35
tPHL − ns
CL− pF
10
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 5 V
0
1
2
3
4
5
6
7
8
9
10
0 5 10 15 20 25 30 35
tPLH− ns
CL− pF
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 5 V
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6.10 Typical Characteristics
TA= 25°C, VCCA = 1.8 V
Figure 1. Typical Propagation Delay (A to B)
vs Load Capacitance
TA= 25°C, VCCA = 1.8 V
Figure 2. Typical Propagation Delay (A to B)
vs Load Capacitance
TA= 25°C, VCCA = 1.8 V
Figure 3. Typical Propagation Delay (B to A)
vs Load Capacitance
TA= 25°C, VCCA = 1.8 V
Figure 4. Typical Propagation Delay (B to A)
vs Load Capacitance
TA= 25°C, VCCA = 2.5 V
Figure 5. Typical Propagation Delay (A to B)
vs Load Capacitance
TA= 25°C, VCCA = 2.5 V
Figure 6. Typical Propagation Delay (A to B)
vs Load Capacitance
tPHL − ns
CL− pF
0 5 10 15 20 25 30 35
0
1
2
3
4
5
6
7
8
9
10
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 5 V
0 5 10 15 20 25 30 35
tPLH − ns
CL− pF
0
1
2
3
4
5
6
7
8
9
10
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 5 V
0 5 10 15 20 25 30 35
tPHL− ns
CL− pF
0
1
2
3
4
5
6
7
8
9
10
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 5 V
0 5 10 15 20 25 30 35
tPLH − ns
CL− pF
0
1
2
3
4
5
6
7
8
9
10
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 5 V
0 5 10 15 20 25 30 35
tPLH − ns
CL− pF
0
1
2
3
4
5
6
7
8
9
10
VCCB = 1.8 V
VCCB = 3.3 V
VCCB = 5 V
VCCB = 2.5 V
0 5 10 15 20 25 30 35
tPHL − ns
CL− pF
0
1
2
3
4
5
6
7
8
9
10
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 5 V
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Typical Characteristics (continued)
TA= 25°C, VCCA = 2.5 V
Figure 7. Typical Propagation Delay (B to A)
vs Load Capacitance
TA= 25°C, VCCA = 2.5 V
Figure 8. Typical Propagation Delay (B to A)
vs Load Capacitance
TA= 25°C, VCCA = 3.3 V
Figure 9. Typical Propagation Delay (A to B)
vs Load Capacitance
TA= 25°C, VCCA = 3.3 V
Figure 10. Typical Propagation Delay (A to B)
vs Load Capacitance
TA= 25°C, VCCA = 3.3 V
Figure 11. Typical Propagation Delay (B to A)
vs Load Capacitance
TA= 25°C, VCCA = 3.3 V
Figure 12. Typical Propagation Delay (B to A)
vs Load Capacitance
tPLH − ns
0 5 10 15 20 25 30 35
CL− pF
0
1
2
3
4
5
6
7
8
9
10
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 5 V
VCCB = 1.8 V
0510 15 20 25 30 35
tPHL− ns
CL− pF
0
1
2
3
4
5
6
7
8
9
10
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 5 V
VCCB = 1.8 V
0 5 10 15 20 25 30 35
tPHL − ns
CL− pF
0
1
2
3
4
5
6
7
8
9
10
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 5 V
0 5 10 15 20 25 30 35
tPLH − ns
CL− pF
0
1
2
3
4
5
6
7
8
9
10
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 5 V
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Typical Characteristics (continued)
TA= 25°C, VCCA = 5 V
Figure 13. Typical Propagation Delay (A to B)
vs Load Capacitance
TA= 25°C, VCCA = 5 V
Figure 14. Typical Propagation Delay (A to B)
vs Load Capacitance
TA= 25°C, VCCA = 5 V
Figure 15. Typical Propagation Delay (B to A)
vs Load Capacitance
TA= 25°C, VCCA = 5 V
Figure 16. Typical Propagation Delay (B to A)
vs Load Capacitance
VOH
VOL
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1
2×VCCO
Open
GND
RL
RL
tPLH tPHL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 ×VCCO
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
VCCA/2VCCA/2
VCCI/2 VCCI/2
VCCI
0 V
VCCO/2 VCCO/2
VOH
VOL
0 V
VCCO/2 VOL + VTP
VCCO/2 VOH − VTP
0 V
VCCI
0 V
VCCI/2 VCCI/2
tw
Input
VCCA
VCCO
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Output
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2×VCCO
GND
TEST S1
NOTES: A. CLincludes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £10 MHz, ZO= 50 W, dv/dt ≥1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. VCCI is the VCC associated with the input port.
I. VCCO is the VCC associated with the output port.
J. All parameters and waveforms are not applicable to all devices.
1.8 V ±0.15 V
2.5 V ±0.2 V
3.3 V ±0.3 V
5 V ±0.5 V
2 kW
2 kW
2 kW
2 kW
VCCO RL
0.15 V
0.15 V
0.3 V
0.3 V
VTP
CL
15 pF
15 pF
15 pF
15 pF
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7 Parameter Measurement Information
Figure 17. Load Circuit and Voltage Waveforms
B
DIR 5
4
A3
VCCA VCCB
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8 Detailed Description
8.1 Overview
The SN74LVC1T45-Q1 is single-bit, dual-supply, non-inverting voltage level translation. Pin A and that direction
control pin (DIR) are supported by VCCA and pin B is supported by VCCB. The A port is able to accept I/O voltages
ranging from 1.65 V to 5.5 V, while the B port can accept I/O voltages from 1.65 V to 5.5 V. The high on the DIR
allows data transmissions from A to B and a low on the DIR allows data transmissions from B to A.
8.2 Functional Block Diagram
Figure 18. Logic Diagram (Positive Logic)
8.3 Feature Description
The SN74LVC1T45-Q1 has a fully configurable dual-rail design that allows each port to operate over the full
1.65-V to 5.5-V power-supply range. Both VCCA and VCCB can be supplied at any voltage between 1.65 V and 5.5
V, making the device suitable for translating between any of the voltage nodes (1.8-V, 2.5-V, 3.3-V and 5-V).
SN74LVC1T45-Q1 can support high data rate applications. The translated signal data rate can be up to 420
Mbps when the signal is translated from 3.3 V to 5 V.
Ioff prevents backflow current by disabling I/O output circuits when device is in partial-power-down mode.
8.4 Device Functional Modes
Table 1 lists the operational modes of SN74LVC1T45-Q1.
(1) Input circuits of the data I/Os always are active.
Table 1. Function Table(1)
INPUT
DIR OPERATION
L B data to A bus
H A data to B bus
1
2
3
6
5
4
VCC1 VCC1 VCC2 VCC2
SYSTEM-1 SYSTEM-2
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74LVC1T45 device can be used in level-translation applications for interfacing devices or systems
operating at different interface voltages with one another. The max data rate can be up to 420 Mbps when device
translates signals from 3.3 V to 5 V.
9.1.1 Enable Times
Calculate the enable times for the SN74LVC1T45-Q1 using the following formulas:
• tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A)
• tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A)
• tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B)
• tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B)
In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is
switched until an output is expected. For example, if the SN74LVC1T45-Q1 initially is transmitting from A to B,
then the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the
B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified
propagation delay.
9.2 Typical Applications
9.2.1 Unidirectional Logic Level-Shifting Application
Figure 19 shows an example of the SN74LVC1T45-Q1 being used in a unidirectional logic level-shifting
application.
Figure 19. Unidirectional Logic Level-Shifting Application
9.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 2.
Table 2. Design Parameters
PARAMETER VALUE
Input voltage 1.65 V to 5.5 V
Output voltage 1.65 V to 5.5 V
1
2
3
6
5
4
VCC1 VCC1 VCC2
SYSTEM-1 SYSTEM-2
DIR CTRL
I/O-1
VCC2
I/O-2
Pullup/Down
or Bus Hold(1)
Pullup/Down
or Bus Hold(1)
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9.2.1.2 Detailed Design Procedure
To begin the design process, determine the following:
• Input voltage range
– Use the supply voltage of the device that is driving the SN74LVC1T45 device to determine the input
voltage range. For a valid logic high the value must exceed the VIH of the input port. For a valid logic low
the value must be less than the VIL of the input port.
• Output voltage range
– Use the supply voltage of the device that the SN74LVC1T45 device is driving to determine the output
voltage range.
9.2.1.3 Application Curve
Figure 20. Translation Up (1.8 V to 5 V) at 2.5 MHz
9.2.2 Bidirectional Logic Level-Shifting Application
Figure 21 shows the SN74LVC1T45-Q1 being used in a bidirectional logic level-shifting application. Because the
SN74LVC1T45-Q1 does not have an output-enable (OE) pin, the system designer should take precautions to
avoid bus contention between SYSTEM-1 and SYSTEM-2 when changing directions.
Figure 21. Bidirectional Logic Level-Shifting Application
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(1) SYSTEM-1 and SYSTEM-2 must use the same conditions, that is, both pullup or both pulldown.
9.2.2.1 Detailed Design Procedure
Table 3 shows data transmission from SYSTEM-1 to SYSTEM-2 and then from SYSTEM-2 to SYSTEM-1.
Table 3. Data Transmission
STATE DIR CTRL I/O-1 I/O-2 DESCRIPTION
1 H Out In SYSTEM-1 data to SYSTEM-2
2 H Hi-Z Hi-Z SYSTEM-2 is getting ready to send data to SYSTEM-1. I/O-1 and I/O-2 are disabled. The bus-
line state depends on pullup or pulldown.(1)
3 L Hi-Z Hi-Z DIR bit is flipped. I/O-1 and I/O-2 still are disabled. The bus-line state depends on pullup or
pulldown.(1)
4 L Out In SYSTEM-2 data to SYSTEM-1
9.2.2.2 Application Curve
Figure 22. Translation Down (5 V to 1.8 V) at 2.5 MHz
10 Power Supply Recommendations
The SN74LVC1T45-Q1 device uses two separate configurable power-supply rails, VCCA and VCCB. VCCA accepts
any supply voltage from 1.65 V to 5.5 V, and VCCB accepts any supply voltage from 1.65 V to 5.5 V. The A port
and B port are designed to track VCCA and VCCB, respectively allowing for low-voltage bidirectional translation
between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For multiple VCC pins then
0.01-µF or 0.022-µF capacitor is recommended for each power pin. It is ok to parallel multiple bypass capacitors
to reject different frequencies of noise. 0.1-µF and 1-µF capacitors are commonly used in parallel. The bypass
capacitor should be installed as close to the power pin as possible for best results.
A proper power-up sequence is advisable as listed in the following:
1. Connect ground before any supply voltage is applied.
2. Power up VCCB.
3. VCCA can be ramped up along with VCCB.
TI recommends that the inputs are grounded during power up. Take care to assure that any state changes do not
affect system level operation.
21
SN74LVC1T45-Q1
www.ti.com
SCES677D –SEPTEMBER 2006–REVISED JULY 2017
Product Folder Links: SN74LVC1T45-Q1
Submit Documentation FeedbackCopyright © 2006–2017, Texas Instruments Incorporated
11 Layout
11.1 Layout Guidelines
To assure reliability of the device, the following common printed-circuit board layout guidelines are
recommended:
• Bypass capacitors must be used on power supplies.
• Short trace lengths must be used to avoid excessive loading.
• Placing pads on the signal paths for loading capacitors or pullup resistors to help adjust rise and fall times of
signals depends on the system requirements.
11.2 Layout Example
Figure 23. Layout Schematic
22
SN74LVC1T45-Q1
SCES677D –SEPTEMBER 2006–REVISED JULY 2017
www.ti.com
Product Folder Links: SN74LVC1T45-Q1
Submit Documentation Feedback Copyright © 2006–2017, Texas Instruments Incorporated
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
Implications of Slow or Floating CMOS Inputs, (SCBA004)
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
PACKAGE OPTION ADDENDUM
www.ti.com 6-Apr-2017
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN74LVC1T45QDCKRQ1 ACTIVE SC70 DCK 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 5TR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 6-Apr-2017
Addendum-Page 2
OTHER QUALIFIED VERSIONS OF SN74LVC1T45-Q1 :
•Catalog: SN74LVC1T45
•Enhanced Product: SN74LVC1T45-EP
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LVC1T45QDCKRQ1 SC70 DCK 6 3000 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Aug-2017
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVC1T45QDCKRQ1 SC70 DCK 6 3000 202.0 201.0 28.0
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Aug-2017
Pack Materials-Page 2
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