24LC16BT-E/MCG - Microchip Technology, Inc.

24AA16/24LC16B

Device Selection Table

Features:

• Single supply with operation down to 1.8V

• Low-power CMOS technology:

- 1 mA active current, ty pical

-1μA standby current (max.) (I-temp)

• Organized as 8 blocks of 256 bytes (8 x 256 x 8)

• 2-wire serial interface bus, I2C™ compatible

• Schmitt Trigger inputs for noise suppression

• Output slope control to eliminate ground bounce

• 100 kHz (2.5V) and 400 kHz (≥2.5V) compatibility

• Self-timed write cycle (including auto-erase)

• Page write buffer for up to 16 bytes

• Hardware write-protect for entire memory

• Can be operated as a serial ROM

• Factory programming (QTP) available

• ESD protection > 4,000V

• 1,000,000 erase/write cycles

• Data retention > 200 years

• 8-lead PDIP, SOIC, TSSOP, DFN and MSOP

packages

• 5-lead SOT-23 package

• Pb-free finish available

• Available temperature ranges:

- Industrial (I): -40°C to +85°C

- Automotive (E): -40°C to +125°C

Description:

The Microchip Technology Inc. 24AA16/24LC16B

(24XX16*) is a 16 Kbit Electrically Erasable PROM.

The device is organized as eight blocks of 256 x 8-bit

memory with a 2-wire serial interface. Low-voltage

design permits operation down to 1.8V with standby

and active currents of only 1 μA and 1 mA,

respectively. The 24XX16 also has a page write

capability for up to 16 bytes of data. The 24XX16 is

available in the standard 8-pin PDIP, surface mount

SOIC, TSSOP, 2x3 DFN and MSOP packages, and is

also avai lab le in t he 5-le ad SOT-23 pac k age .

Package Types

Block Diagram

Part

Number Vcc

Range Max. Clock

Frequency Temp.

Ranges

24AA16 1.8-5.5 400 kHz(1) I

24LC16B 2.5-5.5 400 kHz I, E

Note 1: 100 kHz for VCC <2.5V

VSS

VCC

SCL

SDA

PDIP, MSOP SOIC, TSSOP

VSS

VCC

SCL

SDA

DFN

VSS

SCL

SDA

VCC

SOT-23-5

SCL

Vss

SDA

Vcc

Note: Pins A0, A1 and A2 are not used by the 24XX16 (no

intern al connect ions).

EEPROM

Array

Page

YDEC

XDEC

Sense Amp.

Memory

Control

Logic

I/O

Control

Logic

I/O

SDA

SCL

VCC

VSS R/W Control

Latches

Generator

16K I2C™ Serial EEPROM

*24XX16 is used in this document as a generic part

numbe r for the 24AA16/2 4LC 1 6B devi ce s.

24AA16/24LC16B

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings (†)

VCC.............................................................................................................................................................................6.5V

All inputs and outputs w.r.t. VSS ......................................................................................................... -0.3V to VCC +1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied................................................................................................-65°C to +125°C

ESD protection on all pins......................................................................................................................................................≥ 4kV

TABLE 1-1: DC CHARACTERISTICS

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional operation of the device at those or any other conditions

above th ose indi cated in the opera tional li stings of this sp ecificati on is no t implie d. Exposu re to maxim um rating

conditions for extended periods may affect device reliability.

DC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C, VCC = +1.8V to +5.5V

Automotive (E): TA = -40°C to +125°C, VCC = +2.5V to +5.5V

Param.

No. Symbol Characteristic Min. Typ. Max. Units Conditions

D1 VIH WP, SCL and SDA pins —————

D2 — High-level input voltage 0.7 VCC ——V—

D3 VIL Low-level input voltage — — 0.3 VCC V—

D4 VHYS Hysteresis of Schmitt

Trigger inputs .05 VCC ——V(Note 1)

D5 VOL Low-level output voltage — — 0.40 V IOL = 3.0 m A, VCC = 2.5V

D6 ILI Input leakage current ——±1μAVIN = VSS or VCC

D7 ILO Output leakage current ——±1μAVOUT = VSS or VCC

D8 CIN,

COUT Pin capacitance

(all inputs/ou tpu t s) ——10pFVCC = 5.0V (Note 1)

TA = 25°C, FCLK = 1 MHz

D9 ICC write Operating current ——3mAVCC = 5.5V, SCL = 400 kHz

D10 ICC read — 0.01 1 mA —

D11 ICCS Standby current —

—0.3

.01 1

5μA

μAIndustrial

Automotive

SDA = SCL = VCC

WP = VSS

Note 1: This parameter is periodically sampled and not 100% tested.

2: Typical measurements taken at room temperature.

© 2005 Microchip Technology Inc. DS21703F-page 3
24AA16/24LC16B
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS Industrial (I):  TA = -40°C to +85°C, VCC = +1.8V to +5.5V
Automotive (E):  TA = -40°C to +125°C, VCC = +2.5V to +5.5V
Param.
No. Symbol Characteristic Min. Max. Units Conditions
1F
CLK Clock frequency —
—400
100 kHz 2.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC < 2.5V (24AA16)
2THIGH Clock high time 600
4000 —
—ns 2.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC < 2.5V (24AA16)
3T
LOW Clock low time 1300
4700 —
—ns 2.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC < 2.5V (24AA16)
4TRSDA and SCL rise time 
(Note 1) —
—300
1000 ns 2.5V ≤ VCC ≤ 5.5V (Note 1)
1.8V ≤ VCC < 2.5V (24AA16) 
(Note 1)
5T
FSDA and SCL fall time — 300 ns (Note 1)
6T
HD:STA Start condition hold time 600
4000 —
—ns 2.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC < 2.5V (24AA16)
7TSU:STA Start condition setup time 600
4700 —
—ns 2.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC < 2.5V (24AA16)
8THD:DAT Data input hold time 0 — ns (Note 2)
9TSU:DAT Data input setup time 100
250 —
—ns 2.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC < 2.5V (24AA16)
10 TSU:STO Stop condition setup time 600
4000 —
—ns 2.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC < 2.5V (24AA16)
11 TAA Output valid from clock 
(Note 2) —
—900
3500 ns 2.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC < 2.5V (24AA16)
12 TBUF Bus free time: Time the bus 
must be free before a new 
transmission can  start
1300
4700 —
—ns 2.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC < 2.5V (24AA16)
13 TOF Output fall time from VIH 
minimum to VIL max imum 20+0.1CB
—250
250 ns 2.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC <2.5V (24AA16)
14 TSP Input filter spike suppression
(SDA and SCL pins) —50ns(Notes 1 and 3)
15 TWC Write cycl e time 
(byte or page) —5ms—
16 — Endurance 1M — cycles 25°C, (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region 
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The com bi ned  TSP and V HYS s pec ifi ca tio ns  are due to  new   Schm it t Trigger inputs whi ch  pro vi de  im prov ed  
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensur ed by c haracterization. For endurance estimates in a specific 
applic ation, ple ase  co ns ult the Tot al  Endu ranc e™ Model  whic h c an  be obta ined f r om Mi cro chi p’s we b s ite 
at www.microchip.com.

24AA16/24LC16B

FIGURE 1-1: BUS TIMING DATA

FIGURE 1-2: BUS T IMING START/STOP

524

8910

14 6

SCL

SDA

OUT

Start Stop

SCL

SDA

24AA16/24LC16B

2.0 FUNCTIONAL DESCRIPTION

The 24XX16 supports a bidirectional, 2-wire bus and

data transmission protocol. A device that sends data

onto the bus is defined as a transmitter, while a device

receiving data is defined as a receiver. The bus has to

be controlled by a master device which generates the

Serial Clock (SCL), controls the bus access and

generates the Start and Stop conditions, while the

24XX16 works as slave. Both master and slave can

operate as transmitter or receiver, but the master

device determines which mode is activated.

3.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus

is not busy.

• During data transfer, the data line must remain

stab le when ever th e clock lin e is high. C hanges i n

the data line while the clock line is high will be

interpreted as a Start or Stop condition.

Accordingly, the following bus conditions have been

defined (Figure 3-1).

3.1 Bus Not Busy (A)

Both data and clock lines remain high.

3.2 Start Data Transfer (B)

A high-to-low transition of the SDA line while the clock

(SCL) is high determines a Start condition. All

commands must be preceded by a Start condition.

3.3 S top Data Transfer (C)

A low -t o- h i gh t ran si t io n of t h e SD A l in e whi l e t h e c lo ck

(SCL) is high determines a Stop condition. All

operations must be ended with a Stop condition.

3.4 Data Valid (D)

The state of the data line represents valid data when,

after a Start condition, the data line is stable for the

duration of the high period of the clock signal.

The data on the line must be changed during the low

period of the clock signal. There is one clock pulse per

bit of data.

Each dat a transfer is initiated with a S tart cond ition and

terminated with a Stop condition. The number of data

bytes transferred between Start and Stop conditions is

determined by the master device and is, theoretically

unlimited, (although only the last sixteen will be stored

when doing a write operation). When an overwrite does

occur it will replace data in a first-in first-out (FIFO)

fashion.

3.5 Acknowledge

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The mast er device mus t ge nera te a n ext ra c lock

pulse which is associated with this Acknowledge bit.

The device that acknowledges, has to pull down the

SDA line d uring th e ackn owledge clock pulse in such a

way that the SDA line is stable low during the high

period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into

account. During reads, a master must signal an end of

data to t he sla ve by no t gene rating a n Ack nowledg e bit

on the las t by te that has be en c loc ke d ou t of th e sl av e.

In this c as e, the sl ave (24 XX16) will le av e th e d at a line

high to enable the master to generate the Stop

condition.

FIGURE 3-1: DAT A TRANSFER SEQUENCE ON THE SERIAL BUS

Note: The 24XX16 does not generate any

Acknowledge bits if an internal

programming cycle is in progress.

SCL

SDA

(A) (B) (D) (D) (A)(C)

Start

Condition Address or

Acknowledge

Valid

Data

Allowed

to Change

Stop

Condition

24AA16/24LC16B

3.6 Device Addressing

A control byte is the first byte received following the

Start condition from the master device (Figure 3-2).

The control byte consists of a four-bit control code.

For the 24XX16, this is set as ‘1010’ binary for read

and write operations. The next three bits of the control

byte are the block-select bits (B2, B1, B0). They are

used by the master device to select which of the eight

256 word-blocks of memory are to be accessed.

These bits ar e in effe ct t he thr ee Mo st S ignif ica nt bits

of the word address. It should be noted that the

protoco l limits the si ze of th e memory to eight bl ocks

of 25 6 words, th erefore, th e pr o to c ol c an s u pp o r t on ly

one 24XX 16 per syst em .

The last bit of the control byte defines the operation to

be performed. When set to ‘1’, a read operation is

select ed. W hen set to ‘0’ , a write operati on is se lecte d.

Follow in g the Start condi tio n, the 24XX16 moni tors the

SDA bus, checking the device type identifier being

transmitted and, upon receiving a ‘1010’ code, the

slave device outputs an Acknowledge signal on the

SDA line. Depending on the state of the R/W bit, the

24XX16 will select a read or write operation.

FIGU RE 3-2 : CONT ROL BY TE

ALLOCATION

Operation Control

Code Blo ck Sele ct R/W

Read 1010 Block Address 1

Write 1010 Block Address 0

10 10B2 B1 B0 R/W ACK

Start Bit

Read/Write Bit

Slave Address

Acknowled ge Bit

Control Code

Block

Select

Bits

24AA16/24LC16B

4.0 WRITE OPERATION

4.1 Byte Write

Following the Start condition from the master, the

dev ice co de (4 bits), the block address (3 bits) and t he

R/W bi t, wh ich is a logic-low, is placed onto the bus by

the master transmitter. This indicates to the addressed

slave receiver that a byte with a word address will

follow once it has generated an Ack nowledge b it during

the nint h clock cycl e. Therefor e, the next byt e transmit-

ted by the master is the word address and will be

written into the Address Pointer of the 24XX16. After

receiving another Acknowledge signal from the

24XX16, the master device will transmit the data word

to be written into the addressed memory location. The

24XX16 acknowledges again and the master

generates a Stop condition. This initiates the internal

write cycle and, during this time, the 24XX16 will not

generate Acknowledge signals (Figure 4-1).

4.2 Page Write

The write control byte, word address and the first data

byte are transm itted to the 24 XX16 in the s ame wa y as

in a byte write. However, instead of generating a Stop

condition, the master transmits up to 16 data bytes to

the 24XX16, which are temporarily stored in the on-

chip page buffer and will be written into memory once

the master has transmitted a Stop condition. Upon

receipt of each word, the four lower-order Address

Pointer bits are internally incremented by ‘1’. The

higher-order 7 bits of the word address remain

constant. If the master should transmit more than 16

bytes prior to generating the Stop condition, the

address counter will roll over and the previously

receive d dat a will be overwri tten. As w ith the byte w rite

operation, once the Stop condition is received an

internal write cycle will begin (Figure 4-2).

FIGURE 4-1: BYTE WRITE

FIGURE 4-2: PAGE WRITE

Note: Page write opera tions are l imited to wri ting

bytes within a single physical page,

regardless of the number of bytes

actually being written. Physical page

boundaries start at addresses that are

integer multiples o f the page buf fer size (or

‘pag e-siz e’) and end a t addre sses that a re

integer multiples of [page size – 1]. If a

Page Write command attempts to write

across a physical page boundary, the

result is that the data wraps around to the

beginning of the current page (overwriting

data previously stored there), instead of

being w ritten to the next page, as migh t be

expected. It is therefore necessary for the

application software to prevent page write

operations that would attempt to cross a

page boundary.

S P

Bus Acti vity

Master

SDA Line

Bus Activity

Control

Byte Word

Address Data

1010B2 B1 B0 0

Block

Select

Bits

S P

Bus Acti vity

Master

SDA Line

Bus Activit y

Control

Byte Word

Address (n) Data (n) Data (n + 15)

Data (n + 1)

B2 B0

10 100

Block

Select

Bits

24AA16/24LC16B

5.0 ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the Stop condition for a Write

comma nd has been is sued from the master , the device

initiate s the internall y-timed write cycle and ACK pollin g

can then be initiated immediately. This involves the

master sending a S tart c ondition fo llowed by t he contro l

byte for a W rite command (R/W = 0). If the device is still

busy wi th the write cycle, no ACK will be returned. If the

cycle is complete, the device will return the ACK and

the master can then proceed with the next Read or

Write command. See Figure 5-1 for a flow diagram of

this operation.

FIGURE 5-1: ACKNOWLEDGE POLLING

FLOW

6.0 WRITE PROTECTION

The W P pin a llows th e user t o writ e-prote ct the entire

array (000-7FF) when the pin is tied to VCC. If tied to

VSS the write protection is disabled.

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Operation

Yes

24AA16/24LC16B

7.0 READ OPERATION

Read operations are initiated in the same way as write

operations, with the exception that the R/W bit of the

slave address is set to ‘1’. There are three basic types

of read operat ions: current address read , rand om rea d

and sequential read.

7.1 Current Address Read

The 24XX16 contains an address counter that main-

tains the address of the last word accessed, internally

incremented by ‘1’. Therefore, if the previous access

(either a re ad or write opera tio n) w as to ad dre ss n, the

next curren t address read operati on would access dat a

from address n + 1. Upon receipt of the sl ave add res s

with R/W bit set to ‘1’, the 24XX16 issues an acknowl-

edge and tran smits the 8-bit dat a word. The maste r will

not acknowledge the transfer , but does generate a S top

condition and the 24XX16 discontinues transmission

(Figure 7-1).

7.2 Random Read

Random read operations allow the master to access

any memory location in a random manner. To perform

this typ e of re ad ope ratio n, th e w ord add res s mus t firs t

be set. This is accomplished by sending the word

address to the 24XX16 as part of a write operation.

Once th e word address is s ent, the master ge nerates a

Start condition following the acknowledge. This

terminates the write operation, but not before the inter-

nal Address Pointer is set. The master then issues the

control byt e agai n, but wi th the R/ W bit se t to a ‘ 1’. The

24XX16 will then issue an acknowledge and transmit

the 8-bit data word. The master will not acknowledge

the transfer , but do es generate a S top condition and the

24XX16 will discontinue transmission (Figure 7-2).

7.3 Sequentia l Read

Sequential reads are initiated in the same way as a

random read, except that once the 24XX16 transmits

the first data byte, the master issues an acknowledge

as opposed to a Stop condition in a random read. This

directs the 24XX16 to transmit the next sequentially-

addressed 8-bit word (Figure 7-3).

To provide sequential reads, the 24XX16 contains an

internal Address Pointer that is incremented by one

upon completion of each operation. This Address

Pointer allows the entire memory contents to be serially

read during one operation.

7.4 Noise Protection

The 24XX16 employs a VCC threshold detector circuit

which disables the internal erase/write logic if the VCC

is below 1.5V at nominal conditions.

The SCL and SDA inputs have Schmitt Trigger and

filter circuits which suppress noise spikes to assure

proper device operation, even on a noisy bus.

FIGURE 7-1: CURRENT ADDRESS READ

Bus Activity

Master

SDA Line

Bus Activity

Control

Byte Data (n)

1010 1

B2 B1 B0

Block

Select

Bits

24AA16/24LC16B

FIGURE 7-2: RANDOM READ

FIGURE 7-3: SEQUENTIAL READ

S P

Bus Acti vity

Master

SDA Line

Bus Acti vity

Control

Byte

Word

Address (n) Control

Byte

TData (n)

10 10 0

B2B1B0 11

001

B2B1B0

Block

Select

Bits

Block

Select

Bits

Bus Acti vity

Master

SDA Line

Bus Acti vity

Control

Byte

Data (n) Data (n + 1) Data (n + 2) Data (n + x)

24AA16/24LC16B

8.0 PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 8-1.

TABLE 8-1: PIN FUNCTION TABLE

8.1 Serial Address/Data Input/Output

(SDA)

SDA is a bidirectional pin used to transfer addresses

and data into and out of the de vice . Sinc e it i s an open-

drain terminal, the SDA bus requires a pull-up resistor

to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for 400 kHz).

For normal data transfer, SDA is allowed to change

only during SCL low. Changes during SCL high are

reserved for indicating Start and Stop conditions.

8.2 Serial Clock (SCL)

The SCL in pu t is u se d to s ynchro ni ze th e da t a tra ns fer

to and from the device.

8.3 Wr ite-Protect (WP)

The WP pin must be connected to either VSS or VCC.

If tied to VSS, normal memory operation is enabled

(read/wri te the ent ire memory 0007 -FF).

If tied to VCC, write operations are inhibited. The entire

memory will be write-protected. Read operations are

not affected.

This feature allows the user to use the 24XX16 as a

serial ROM when WP is enabled (tied to VCC).

8.4 A0, A1, A2

The A0, A1 and A2 pins are not used by the 24XX16.

They may be left floating or tied to either VSS or VCC.

Name PDIP SOIC TSSOP DFN MSOP SOT-23 Description

A0 1 1 1 1 1 — Not Connected

A1 2 2 2 2 2 — Not Connected

A2 3 3 3 3 3 — Not Connected

VSS 4 4 4 4 4 2 Ground

SDA 5 5 5 5 5 3 Serial Address/Data I/O

SCL 6 6 6 6 6 1 Serial Clock

WP 7 7 7 7 7 5 Write-Protect Input

VCC 8 8 8 8 8 4 +1.8V to 5.5V Power Supply

24AA16/24LC16B

9.0 PACKAGING INFORMATION

9.1 Package Marking Information

XXXXXXXX

T/XXXNNN

YYWW

8-Lead PDIP (300 mil) Example:

8-Lead SOIC (150 mil) Example:

XXXXXXXT

XXXXYYWW

NNN

8-Lead TSSOP Example:

24LC16B

I/P 13F

0527

24LC16BI

SN 0527

13F

8-Lead MSOP Example:

XXXX

TYWW

NNN

XXXXXT

YWWNNN

4L16

I527

13F

4L16I

52713F

5-Le a d S OT-23 Example:

XXNN B53F

8-Lead 2x3 DFN Example:

254

527

XXX

YWW

24AA16/24LC16B

Part Number

1st Line Marking Codes

TSSOP MSOP SOT-23 DFN

I Temp. E Temp. I Temp. E Temp.

24AA16 4A16 4A16T B5NN — 251 —

24LC16B 4L16 4L16T M5NN N5NN 254 255

Note: T = Temperature grade (I, E)

NN = Alphanumeric traceability code

Legend: XX...X Part number or part number code

T Temperature (I, E)

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week o f January 1 is week ‘01’)

NNN Alphanumeric traceability code (2 characters for small packages)

Pb-free JEDEC designator for Matte Tin (Sn)

Note: For very small packages with no room for the Pb-free JEDEC designator

, the marking will only appear on the outer carton or reel label.

Note: In the event the full Mi croch ip pa rt numbe r canno t be marke d on one line , it wil

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

Note: Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion.

*Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.

24AA16/24LC16B

8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)

Units INCHES* MILLIMETERS

Dime nsion Limits MIN NOM MAX MIN NOM M AX

Number of Pins n88

Pitch p.100 2.54

Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32

Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68

Base to Seating Plane A1 .015 0.38

Shoulder to Shoulder W idt h E .300 .313 .325 7.62 7.94 8.26

Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60

Overall Length D .360 .373 .385 9.14 9.46 9.78

Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43

Lead Thickness c.008 .012 .015 0.20 0.29 0.38

Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78

Lower Lead Width B .014 .018 .022 0.36 0.46 0.56

Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92

Mold Draft Angle Top α51015 51015

Mold Draft Angle Bottom β51015 51015

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

JEDEC Equivalent: MS-001

Drawing No. C04-018

.010” (0.254mm) per side.

§ Significant Characteristic

24AA16/24LC16B

8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)

Foot A ngle φ048048

1512015120

Mold Draft Angle Bottom 1512015120

Mold Draft Angle Top 0.510.420.33.020.017.013BLead Width 0.250.230.20.010.009.008

Lead Thickness

0.760.620.48.030.025.019LFoot Length 0.510.380.25.020.015.010hChamfer Distance 5.004.904.80.197.193.189DOverall Length 3.993.913.71.157.154.146E1Molded Pa ckag e Width 6.206.025.79.244.237.228EOverall Width 0.250.180.10.010.007.004

Standoff § 1.551.421.32.061.056.052A2Molded Packag e Thickness 1.751.551.35.069.061.053AOverall Height 1.27.050

Pitch 88

Numb er of Pin s MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units

45°

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-012

Drawing No. C04-057

§ Significant Characteristic

24AA16/24LC16B

8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)

10501050

Mold Draft Angle Bottom 10501050

Mold Draft Angle Top 0.300.250.19.012.010.007BLead Width 0.200.150.09.008.006.004

Lead Thickness

0.700.600.50.028.024.020LFoot Lengt h 3.103.002.90.122.118.114DMolded Package Length 4.504.404.30.177.173.169E1M old ed Packag e Width 6.506.386.25.256.251.246EOverall Width 0.150.100.05.006.004.002

Standoff § 0.950.900.85.037.035.033A2Molded Packag e Thickness 1.10.043AOverall Height 0.65.026

Pitch 88

Number of Pins MAXNOMMINMAXNOMMINDimensi on Li mits MILLIMETERS*INCHES

Units

Foot A ngle φ048048

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.005” (0.127mm) per side.

JEDEC Equivalent: MO-153

Drawing No. C04-086

§ Significant Characteristic

24AA16/24LC16B

8-Lead Plastic Dual Flat No Lead Package (MC) 2x3x0.9 mm Body (DFN) – Saw Singulated

Exposed Pad Width

Exposed Pad Length

Contact Length

*Controlling Parameter

Contact Width

Drawing No. C04-123

Notes:

Exposed pad dimensions vary with paddle size.

Overall Width

.016

.012

.008

.047

.055

.010

.118 BSC

Number of Pins

Standoff

Contact Thickness

Overall Length

Overall Height

Pitch p

Units

Dimension Limits

.000 .001

.008 REF.

.079 BSC

.031

.020 BSC

MIN

INCHES

NOM

0.40

0.25

3.00 BSC

0.30

.020

.071

.012

.064

0.20

1.20

1.39

0.50

0.30

1.80

1.62

0.02

0.80

2.00 BSC

0.20 REF.

0.50 BSC

MILLIMETERS*

.002

.039

0.00

MINMAX NOM

0.05

1.00

MAX

Package may have one or more exposed tie bars at ends.1.

Pin 1 visual index feature may vary, but must be located within the hatched area.2.

0.90.035

(Note 3)

4. JEDEC equivalent: MO-229

A3 A1

TOP VIEW

EXPOSED

PAD

METAL

BOTTOM VIEW

(NOTE 1)

EXPOSED

TIE BAR

PIN 1

(NOTE 2)

ID INDEX

AREA

Revised 05/24/04

-- --

24AA16/24LC16B

8-Lead Plastic Micro Small Outline Package (MS) (MSOP)

(F)

n 1

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not

.037 REFFFootprint (Reference)

exceed .010" (0.254mm) per side.

Notes:

Drawing No. C04-111

*Controlling Parameter

Mold Draft Angle Top

Mold Draft Angle Bottom

Foot Angle

Lead Width

Lead Thickness

.003

.009

.006

.012

Dimension Limits

Overall Height

Molded Package Thickness

Molded Package Width

Overall Length

Foot Length

Standoff

Overall Width

Number of Pins

Pitch

.016 .024

.118 BSC

.000

.030

.193 TYP.

.033

MIN

Units

.026 BSC

NOM

INCHES

0.95 REF

.009

.016

0.08

0.22

0°

0.23

0.40

8°

MILLIMETERS*

0.65 BSC

0.85

3.00 BSC

0.60

4.90 BSC

.043

.031

.037

.006

0.40

0.00

0.75

MIN

MAX NOM

1.10

0.80

0.15

0.95

MAX

15°5° -

JEDEC Equivalent: MO-187

0° - 8°

5°

5° -

15°

24AA16/24LC16B

5-Lead Plastic Small Outline Transistor (OT) (SOT-23)

10501050

Mold Draft Angle Bottom 10501050

Mold Draft Angle Top 0.500.430.35.020.017.014BLead Width 0.200.150.09.008.006.004

Lead Thickness 10501050

Foot A ngle 0.550.450.35.022.018.014LFoot Lengt h 3.102.952.80.122.116.110DOverall Length 1.751.631.50.069.064.059E1Molded Pa ckag e Width 3.002.802.60.118.110.102EOverall Width 0.150.080.00.006.003.000A1Standoff § 1.301.100.90.051.043.035A2Molded Packag e Thickness 1.451.180.90.057.046.035AOverall Height 1.90.075

Outside lead pitch (basic) 0.95

.038

Pitch 55

Number of Pins MAXNOMMINMAXNOMMINDimensi on Li mits MILLIMETERSINCHES*Units

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MO-178

Drawing No. C04-091

§ Significant Characteristic

24AA16/24LC16B

APPENDIX A: REVISION HIST ORY

Revision D

Corrections to Section 1.0, Electrical Characteristics.

Revision E

Added DFN package.

Revision F

Revi se d F ig ur e 3 -2 C o nt ro l B yte Al l oc at io n; Fi g ure 4- 1

Byte Write; Figure 4-2 Page Write; Section 6.0 Write

Protectio n; Figure 7-1 Curre nt Address Read ; Figure 7-

2 Random Read; Figure 7-3 Sequential Read; Section

8.3 Write-Protect (WP).

24AA16/24LC16B

THE MICROCHIP WEB SITE

Microc hip pro vides onl ine s upport v ia our W WW site at

www.microchi p.c om . Thi s web si te i s us ed as a m ean s

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

•Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

docume nts , latest softw are releas es and archived

software

•General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online dis cu ss io n gr oups, Micro chi p con sul tant

program member listing

•Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specif ied produ ct family or develo pment tool of interes t.

To register, access the Microchip web site at

www.microchip.com, click on Customer Change

Notification and follow the registration instructions.

CUSTOMER SUPPORT

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Development Systems Information Line

Customers should contact their distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

Technical s upport is a vailable through the web site

at: http://support.microchip.com

24AA16/24LC16B

READER RESPONSE

It is ou r intentio n to provide you with the b es t do cument a t ion po ss ib le to e ns ure suc c es sfu l u se of y ou r M icr oc hip pro d-

uct. If you wi sh to prov ide you r comment s on org anizatio n, clar ity, subj ect matte r , and ways i n which o ur docum entatio n

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

To: Technical Publications Manager

RE: Reader Response Total Pages Sent ________

From: Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

Application (optional):

Would you like a reply? Y N

Device: Literature Number:

Questions:

FAX: (______) _________ - _________

DS21703F24AA16/24LC16B

1. What are the be st features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

24AA16/24LC16B

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Note 1: Most products manufactured after January 2005 will have a Matte Tin (Pb-free) finish. Most products manufactured

before January 2005 will have a finish of approximately 63% Sn and 37% Pb (Sn/Pb).

Please visit www.microchip.com for the latest information on Pb-free conversion, including conversion date codes.

Sales and Support

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and

recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office

2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277

3. The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Dat a Sheet (include Literature #) you are using.

New Customer Notification System

PART NO. X/XX

PackageTemperature

Range

Device

24A A16: = 1.8V, 16 Kbit I2C Serial EEPROM

24AA16T: = 1.8V, 16 Kbit I2C Serial EEPROM

(Tape and Reel)

24LC16B: = 2.5V, 16 Kbit I2C Serial EEPROM

24LC16BT: = 2.5V, 16 Kbit I2C Serial EEPROM

(Tape and Reel)

Temperature

Range: I = -40°C to +85°C

E = -40°C to +125°C

Package: MC = 2x3 DFN, 8-lead

P = Plastic DIP (300 mil body), 8-lead

SN = Plastic SOIC (150 mil body), 8-lead

ST = Plastic TSSOP (4.4 mm), 8-lead

MS = Plastic Micro Small Outline (MSOP), 8-lead

OT = SOT-23, 5-lead (Tape and Reel only)

Lead Finis h: Blank = Pb-free – Matte Tin (see Note 1)

G = Pb-free – Matte Tin only

Examples:

a) 24AA16-I/P: Industrial Temperature,1.8V,

PDIP package

b) 24AA16-I/SN: Industrial Temperature,1.8V,

SOIC package

c) 24AA16T -I/OT: Industrial Temperature,

1.8V, SOT-23 package, Tape and Reel

d) 24LC16B-I/P: Industrial T emperature, 2.5V,

PDIP package

e) 24LC16B-E/SN: Automotive Temp.,2.5V

SOIC package

f) 24LC16BT-I/OT: Industrial Tem perat ure,

2.5V, SOT-23 package, Tape and Reel

Lead Finish

24AA16/24LC16B

NOTES:

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR WAR-

RANTIES OF ANY KIN D WHETHER EXPRESS OR IMPLIED ,

WRITTEN OR ORAL, STATUTORY OR OTHERWISE,

RELATED TO THE INFORMATION, INCLUDING BUT NOT

LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,

MERCHANTABILITY OR FITNESS FOR PURPOSE.

Microchip disclaims all liability arising from this information and

its use. U se of Microc hip’s products as critical com ponents in

life support systems is not authorized except with express

written approval by Microchip. No licenses are conveyed,

implicitly or otherwise, under any Microchip intellectual property

rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICST ART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXD EV, MXLAB,

PICMASTER, SEEVAL, SmartSensor and The Embedded

Control Solutions Company are registered trademarks of

Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM,

dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,

FanSense, FlexROM, fuzzyLAB, In-Circuit Serial

Programming, ICSP, ICEPIC, Linear Active Thermistor,

MPASM , MPLIB, MPL I N K, MPSIM, PI Ckit , PICDEM,

PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo,

PowerMate, Powe rTool, rfLAB, rfPICDEM , Select Mode,

Smart Serial, SmartTel, Total Endurance and WiperLock are

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its f amily of products is one of the most secure families of its kind on the market today, when used in t he

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Dat a

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microchip are committed to continuously improving the c ode prot ection f eatures of our

products. Attempts to break Microchip’ s code protection f eature may be a violati on of t he Digit al Millennium Copyright Act. If such act s

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 quality system certification for

its worldwide headquarters, design and wafer fabrication facilities in

Chandler and Tempe, Arizona and Mountain View, California in

October 2003. The Company’s quality system processes and

procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping

devices, Serial EEPROMs, micro peripherals, nonvolat ile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

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08/24/05