VNH5050A-E Automotive fully integrated H-bridge motor driver Features Type RDS(on) Iout Vccmax VNH5050A-E 50 m max (per leg) 30 A 41 V Output current: 30 A 3 V CMOS compatible inputs Undervoltage and overvoltage shutdown Overvoltage clamp Thermal shutdown Cross-conduction protection Current and power limitation Very low standby power consumption PWM operation up to 20 KHz Protection against loss of ground and loss of VCC Current sense output proportional to motor current Output protected against short to ground and short to VCC Package: ECOPACK(R) Description The VNH5050A-E is a full bridge motor driver intended for a wide range of automotive applications. The device incorporates a dual monolithic high-side driver and two low-side switches. All switches are designed using STMicroelectronics(R) well known and proven Table 1. PowerSSO-36 TP proprietary VIPower(R) M0 technology that allows to efficiently integrate on the same die a true Power MOSFET with an intelligent signal/protection circuitry. The three dies are assembled in a PowerSSO-36 TP package on electrically isolated lead frames. This package, specifically designed for the harsh automotive environment offers improved thermal performance thanks to exposed die pads. Moreover, its fully symmetrical mechanical design allows superior manufacturability at board level. The input signals INA and INB can directly interface to the microcontroller to select the motor direction and the brake condition. The DIAGA/ENA or DIAGB/ENB, when connected to an external pull-up resistor, enables one leg of the bridge. Each DIAGA/ENA provides a digital diagnostic feedback signal as well. The normal operating condition is explained in the truth table. The CS pin allows monitoring the motor current by delivering a current proportional to its value when CS_DIS pin is driven low or left open. When CS_DIS is driven high, CS pin is in high impedance condition. The PWM, up to 20 KHz, allows to control the speed of the motor in all possible conditions. In all cases, a low level state on the PWM pin turns off both the LSA and LSB switches. Device summary Order codes Package PowerSSO-36 TP September 2013 Tube Tape and reel VNH5050A-E VNH5050ATR-E Doc ID 16009 Rev 11 1/33 www.st.com 1 Contents VNH5050A-E Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1 4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1 5 6 2/33 Reverse battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 PowerSSO-36 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1.1 Thermal calculation in clockwise and anti-clockwise operation in steady-state mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1.2 Thermal resistances definition (values according to the PCB heatsink area) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1.3 Thermal calculation in transient mode . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1 ECOPACK(R) packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2 PowerSSO-36 TP package information . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.3 PowerSSO-36 TP packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Doc ID 16009 Rev 11 VNH5050A-E List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Block description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin functions description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Logic inputs (INA, INB, ENA, ENB, PWM, CS_DIS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Switching (VCC = 13 V, RLOAD = 1.5 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Current sense (9 V < VCC < 18 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Truth table in normal operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Truth table in fault conditions (detected on OUTA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Electrical transient requirements (part 1/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Electrical transient requirements (part 2/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Electrical transient requirements (part 3/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Thermal calculation in clockwise and anti-clockwise operation in steady-state mode . . . . 25 Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 PowerSSO-36 TP mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Doc ID 16009 Rev 11 3/33 List of figures VNH5050A-E List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. 4/33 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Definition of the delay times measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Definition of the low-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Definition of the high-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Definition of dynamic cross conduction current during a PWM operation. . . . . . . . . . . . . . 16 Definition of delay response time of sense current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Waveforms in full-bridge operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Waveforms in full-bridge operation (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Typical application circuit for DC to 20 kHz PWM operation short circuit protection . . . . . 21 Behavior in fault condition (how a fault can be cleared) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Half-bridge configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Multi-motors configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PowerSSO-36TM PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Chipset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Auto and mutual Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . . 25 Detailed chipset configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 PowerSSO-36 HSD thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . 27 PowerSSO-36 LSD thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . 27 Thermal fitting model of an H-bridge in PowerSSO-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 PowerSSO-36 TP package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 PowerSSO-36 TP tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 PowerSSO-36 TP tape and reel shipment (suffix "TR") . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Doc ID 16009 Rev 11 VNH5050A-E 1 Block diagram and pin description Block diagram and pin description Figure 1. Block diagram 9&& VCC 6,*1$/ &/$03 )$8/7 '(7(&7,21 FAULT 32:(5 /,0,7$7, POWER 21 DETECTION LIMITATION /6$B29(57(03(5$785( /6%B29(57(03(5$785( LSA_OVERTEMPERATURE +6$B29(57(03(5$785( HSA_OVERTEMPERATURE &/$03B+6 $ CLAMP_HS +6$ LSB_OVERTEMPERATURE 2989 OV + UV +6%B29(57(03(5$785( HSB_OVERTEMPERATURE &/$03B+6% CLAMP_HS B A /2*,& LOGIC '5,9(5DRIVER +6$ HSA HSA '5,9(5 DRIVER HS +6B% CURRENT &855(17 LIMITATION_A /,0,7$7,21B$ SOURCE_HSA 6285&(B+6$ SIGNAL CLAMP CURRENT &855(17 LIMITATION_B /,0,7$7, 21B% . 1/K SOURCE_HSB 1/K CLAMP_LSB &/$03B/6$ '5$,1B/6$ DRIVER LSB '5$,1B/6% LSB '5,9(5 /6% '5,9(5 /6$ OVERLOAD /6% OVERLOAD DETECTOR_B DETECTOR_A 29(5/2$' '(7(&725B$ GNDA *1'$ DRAIN_LSB &/$03B/6% DRIVER LSA LSA /6$ 6285&(B+6% . CLAMP_LSA DRAIN_LSA HS+6 B % DIAGA/ENA INA CS CS_DIS PWM INB ',$*$(1$ ,1$ &6 &6B',6 3:0 ,1% DIAGB/ENB 29(5/2$' '(7(&725B% ',$*%(1% GNDB *1'% ("1($'5 Table 2. Block description Name Description Logic control Allows the turn-on and the turn-off of the high-side and the low-side switches according to the truth table. Undervoltage/overvoltage Shuts down the device for battery voltage outside the range (4,5...24V). High-side and low-side clamp voltage Protect the high-side and the low-side switches from high voltage on the battery line. High-side and low-side driver Drive the gate of the concerned switch to allow a proper RDS(on) for the leg of the bridge. Current limitation Limits the motor current in case of short circuit. High-side and low-side overtemperature protection In case of short-circuit with the increase of the junction temperature, it shuts down the concerned driver to prevent degradation and to protect the die. Low-side overload detector Detects when low-side current exceeds shutdown current and latches off the concerned low-side. Fault detection Signalizes an abnormal condition of the switch (output shorted to ground or output shorted to battery) by pulling down the concerned ENx/DIAGx pin. Power limitation Limits the power dissipation of the high-side driver inside safe range in case of short to ground condition. Doc ID 16009 Rev 11 5/33 Block diagram and pin description Table 3. VNH5050A-E Suggested connections for unused and not connected pins Connection / pin Current sense N.C. SOURCE_HSx DRAIN_LSx INPUTx, PWM DIAGx/ENx CS_DIS Floating Not allowed X X X X To ground Through 1 k resistor X Not allowed X Through 10 k resistor Figure 2. Configuration diagram (top view) GND_A 1 36 DRAIN LSA GND_A GND_A GND_A GND_A GND_A DRAIN LSA SOURCE HSA SOURCE HSA SOURCE HSA SOURCE HSA VCC SOURCE HSA INA ENA/DIAGA IN_PWM NC Table 4. 6/33 Slug2 Slug3 SOURCE HSB INB Slug1 19 18 GND_B DRAIN LSB GND_B GND_B GND_B GND_B GND_B DRAIN LSB SOURCE HSB SOURCE HSB SOURCE HSB SOURCE HSB VCC ENB/DIAGB CS_DIS CS Pin definitions and functions Pin N Symbol Function 13, 24 VCC, Heat slug1 18 NC Not connected. 15 INA Clockwise input. 16 ENA/DIAGA 17 IN_PWM 19 CS Drain of high-side switches and power supply voltage. Status of high-side and low-side switches A; Open drain output. PWM input. Output of current sense. Doc ID 16009 Rev 11 VNH5050A-E Block diagram and pin description Table 4. Pin definitions and functions (continued) Pin N Symbol Function 20 CS_DIS Active high CMOS compatible pin to disable current sense pin. 21 ENB/DIAGB 22 INB 23, 25, 26, 27, 28, 29, 35 GND_B Source of low-side switch B. OUTA, Heat Source of high-side switch A / drain of low-side switch A. Slug2 1, 3, 4, 5, 6, 7 Table 5. Counter clockwise input. OUTB, Heat Source of high-side switch B / drain of low-side switch B. Slug3 30, 31, 32, 33, 34,36 2, 8, 9, 10, 11, 12, 14 Status of high-side and low-side switches B; Open drain output. GND_A Source of low-side switch A. Pin functions description Name Description VCC Battery connection. GND Power ground. OUTA OUTB Power connections to the motor. INA INB Voltage controlled input pins with hysteresis, CMOS compatible. These two pins control the state of the bridge in normal operation according to the truth table (brake to VCC, Brake to GND, clockwise and counterclockwise). PWM Voltage controlled input pin with hysteresis, CMOS compatible.Gates of low-side FETS get modulated by the PWM signal during their on phase allowing speed control of the motor. ENA/DIAGA ENB/DIAGB Open drain bidirectional logic pins.These pins must be connected to an external pull up resistor. When externally pulled low, they disable half-bridge A or B. In case of fault detection (thermal shutdown of a high-side FET or excessive on-state voltage drop across a low-side FET), these pins are pulled low by the device (see truth table in fault condition). CS Analog current sense output. This output delivers a current proportional to the motor current if CS_DIS is low or left open. The information can be read back as an analog voltage across an external resistor. CS_DIS Active high CMOS compatible pin to disable the current sense pin. Doc ID 16009 Rev 11 7/33 Electrical specifications 2 VNH5050A-E Electrical specifications Figure 3. Current and voltage conventions IS VCC IINA IINB IENA IENB VCC INA INB CS CS_DIS DIAGB/ENB PWM IGND ICSD VOUTB VSENSE VCSD Vpw Absolute maximum ratings Table 6. Absolute maximum ratings Symbol Parameter VCC Supply voltage Imax DC output current (continuous)(1) Value Unit + 41 V Internally limited A 25 A IR Reverse output current IIN Input current (INA and INB pins) +/- 10 mA IEN Enable input current (DIAGA/ENA and DIAGB/ENB pins) +/- 10 mA Ipw PWM Input current +/- 10 mA CS_DIS input current +/- 10 mA VCC-41/+VCC V 2 kV Junction operating temperature -40 to 150 C TSTG Storage temperature -55 to 150 C IGND DC reverse ground pin current 200 mA ICS_DIS VCS Current sense maximum voltage VESD Electrostatic discharge (Human body model: R = 1.5 k, C = 100 pF) Tc 1. Based on the internal wires capability. 8/33 VOUTA ISENSE GND Ipw 2.1 IOUTB OUTB DIAGA/ENA VINA VINB VENA VENB IOUTA OUTA Doc ID 16009 Rev 11 VNH5050A-E 2.2 Electrical specifications Thermal data Table 7. Symbol Thermal data Parameter Rthj-case Thermal resistance junction-case (per leg) Rthj-amb Thermal resistance junction-ambient Doc ID 16009 Rev 11 Max. value Unit HSD 3.7 C/W LSD 3.9 C/W See Figure 17 C/W 9/33 Electrical specifications 2.3 VNH5050A-E Electrical characteristics VCC = 9 V up to 18 V; -40 C < Tj < 150 C, unless otherwise specified. Table 8. Power section Symbol Parameter Test conditions VCC Operating supply voltage Min. 5.5 Supply current V 6 A Off-state with all fault cleared and ENx = 0 (standby) VCC = 13 V; INA = INB = PWM = 0; Tj = -40 C to 150 C 10 A Off-state (no standby) INA = INB = PWM = 0; ENx = 5 V; Tj = -40 C to 150 C 5 mA 6 mA 8 mA 3 On-state: INA or INB = 5V; no PWM 3 On-state: INA or INB = 5 V; PWM = 20 kHz IOUT = 8.5 A; Tj = -40 C RONHS OUT Static high-side resistance = 8.5 A; Tj = 25 C IOUT = 8.5 A; Tj = 150 C 17 m 26 m 52 m IOUT = 8.5 A; Tj = - 40 C to 150 C 60 IOUT = 8.5 A; Tj = 25 C RONLS Vf IL(off) IRM 10/33 Static low-side resistance High-side free-wheeling diode forward voltage High-side off-state output current (per channel) Dynamic crossconduction current Unit 18 Off-state with all fault cleared and ENx = 0 (standby) INA = INB = PWM = 0; Tj = 25 C; VCC = 13 V IS Typ. Max. 20 IOUT = 8.5 A; Tj = - 40 C to 150 C IOUT = -8.5 A; Tj = 150 C 0.7 m m 40 m 0.9 V Tj = 25 C; VCC = 13V; VOUTX = ENX = 0 V 0 3 A Tj = 125C; VCC = 13V; VOUTX = ENX = 0 V 0 5 A IOUT = 8.5 A (see Figure 7) Doc ID 16009 Rev 11 1 A VNH5050A-E Electrical specifications Table 9. Symbol Logic inputs (INA, INB, ENA, ENB, PWM, CS_DIS) Parameter Test conditions Min. Typ. Max. Unit 0.9 V VIL Input low level voltage Normal operation (DIAGX/ENX pin acts as an input pin) VIH Input high level voltage Normal operation (DIAGX/ENX pin acts as an input pin) 2.1 V VIHYST Input hysteresis voltage Normal operation (DIAGX/ENX pin acts as an input pin) 0.15 V IIN = 1 mA 5.5 6.3 7.5 V IIN = -1 mA -1.0 -0.7 -0.3 V 1 VICL Input clamp voltage IINL Input current VIN = 0.9 V IINH Input current VIN = 2.1 V 10 A Enable output low level voltage Fault operation (DIAGX/ENX pin acts as an output pin); IEN = 1 mA 0.4 V Max. Unit 20 kHz VDIAG Table 10. Symbol f A Switching (VCC = 13 V, RLOAD = 1.5 ) Parameter Test conditions PWM frequency Min. Typ. 0 td(on) Turn-on delay time Input rise time < 1s (see Figure 6) 250 s td(off) Turn-off delay time Input rise time < 1s (see Figure 6) 250 s tr Rise time See Figure 5 1 2 s tf Fall time See Figure 5 1 2 s Delay time during change of operating mode See Figure 4 400 1600 s High-side free wheeling diode reverse recovery time See Figure 7 tDEL trr Table 11. Symbol 200 100 ns Protections and diagnostics Parameter Test conditions Min. Typ. Max. Unit 5 V VUSD Undervoltage shutdown 3 VUSDhyst Undervoltage shutdown hysteresis 0.5 V VOV VCC overvoltage shutdown 24 27 30 V ILIM_H High-side current limitation 30 42 60 A Doc ID 16009 Rev 11 11/33 Electrical specifications Table 11. Symbol VNH5050A-E Protections and diagnostics (continued) Parameter Test conditions Min. Typ. Max. Unit 30 50 70 A ISD_LS Shutdown LS current VCLP Total clamp voltage (VCC to GND) IOUT = 8.5 A 41 46 52 V VCLPH High-side clamp voltage (VCC to OUTA =0 or OUTB =0) IOUT = 8.5 A 41 46 52 V TSD_LS Time to shutdown for the low-side VCLPLS Low-side clamp voltage (OUTA = VCC or OUTB = VCC to GND) IOUT = 8.5 A 25 28 31 V TTSD(1) Thermal shutdown temperature VIN = 2.1 V 150 175 200 C TTR(2) Thermal reset temperature THYST(2) Thermal hysteresis (TSD-TR) TTSD_LS Low-side thermal shutdown temperature 10 s 135 C 16 VIN = 0 V 150 175 C 200 C Unit 1. TTSD is the minimum threshold temperature between HS and LS 2. Valid for both HSD and LSD. Table 12. Symbol 12/33 Current sense (9 V < VCC < 18 V) Parameter Test conditions Min. Typ. Max. K1 IOUT/ISENSE IOUT = 5 A; VSENSE = 0.8 V; VCSD = 0 V; Tj = - 40 C to 150 C 4350 5100 6270 K2 IOUT/ISENSE IOUT = 10 A; VSENSE = 1.6 V; VCSD = 0 V; Tj = - 40 C to 150 C 4350 5030 5870 K3 IOUT/ISENSE IOUT = 25 A; VSENSE = 4 V; VCSD = 0 V; Tj = - 40 C to 150 C 4100 4930 5490 dK1/K1(1) Analog sense current drift IOUT = 5 A; VSENSE = 0.8 V; VCSD = 0 V; Tj = - 40 C to 150C -14 14 % dK2/K2(1) Analog sense current drift IOUT = 10 A; VSENSE = 1.6 V; VCSD = 0 V; Tj = - 40 C to 150C -13 13 % dK3/K3(1) Analog sense current drift IOUT = 25 A; VSENSE = 4 V; VCSD = 0 V; Tj = - 40 C to 150 C -13 13 % Doc ID 16009 Rev 11 VNH5050A-E Electrical specifications Table 12. Symbol VSENSE Current sense (9 V < VCC < 18 V) (continued) Parameter Max analog sense output voltage ISENSETYP_500 Typical analog sense ISENSE0 Analog sense leakage current Test conditions IOUT = 10 A; VCSD = 0 V; RSENSE = 800 Min. Typ. Max. 5 Unit V IOUT = 500 mA; VCC = 13 V; Tj = - 40 C 87 A IOUT = 500 mA; VCC = 13 V; Tj = 25 C 91 A IOUT = 500 mA; VCC = 13 V; Tj = 150 C 100 A IOUT = 0 A; VSENSE = 0 V; VCSD = 5 V; VIN = 0 V; Tj = - 40 C to 150C 0 5 A VCSD = 0 V; VIN = 5 V; Tj = - 40 C to 150 C 0 180 A VCSD = 5 V; VIN = 5 V; IOUT = 8.5 A 0 5 A tDSENSEH Delay response time from falling edge of CS_DIS pin VIN = 5 V; VSENSE < 4 V, IOUT = 8.5 A; ISENSE = 90 % of ISENSEmax (see Figure 8) 50 s tDSENSEL Delay response time from rising edge of CS_DIS pin VIN = 5 V; VSENSE < 4 V; IOUT = 8.5 A; ISENSE = 10 % of ISENSEmax (see Figure 8) 20 s 1. Analog sense current drift is deviation of factor K for a given device over (-40C to 150C and 9 V < VCC < 18 V) with respect to its value measured at Tj = 25 C, VCC = 13 V. Doc ID 16009 Rev 11 13/33 Electrical specifications Figure 4. VNH5050A-E Definition of the delay times measurement VINA t VINB t PWM t ILOAD tDEL tDEL t 14/33 Doc ID 16009 Rev 11 VNH5050A-E Figure 5. Electrical specifications Definition of the low-side switching times PWM t VOUTA, B 90% tf Figure 6. 80% 20% 10% tr t Definition of the high-side switching times VINA tD(off) tD(on) t VOUTA 90% 10% t Doc ID 16009 Rev 11 15/33 Electrical specifications Figure 7. VNH5050A-E Definition of dynamic cross conduction current during a PWM operation INA = 1, INB = 0 PWM t IMOTOR t VOUTB t ICC IRM t trr Figure 8. Definition of delay response time of sense current INPUT CS_DIS LOAD CURRENT SENSE CURRENT tDSENSEH 16/33 Doc ID 16009 Rev 11 tDSENSEL VNH5050A-E Electrical specifications Table 13. Truth table in normal operating conditions INA INB DIAGA/ENA DIAGB/ENB OUTA OUTB 1 H 1 CS High Imp. H 0 1 1 H 0 Brake to VCC Clockwise (CW) L 1 Operating mode ISENSE = IOUT/K Counterclockwise (CCW) L 0 Table 14. INA L High Imp. Brake to GND Truth table in fault conditions (detected on OUTA) INB DIAGA/ENA DIAGB/ENB OUTA OUTB CS (VCSD=0V) 1 H 0 L High impedance H IOUTB/K L High impedance 1 1 1 0 OPEN 0 0 X X 0 Fault Information Note: OPEN Protection Action In normal operating conditions the DIAGX/ENX pin is considered as an input pin by the device. This pin must be externally pulled high. Doc ID 16009 Rev 11 17/33 Electrical specifications Table 15. ISO 7637-2: 2004(E) Test pulse VNH5050A-E Electrical transient requirements (part 1/3) Test levels(1) III IV 1 -75V -100V 2a +37V 3a Number of pulses or test times Burst cycle/pulse repetition time Delays and Impedance Min. Max. 5000 pulses 0.5s 5s 2 ms, 10 +50V 5000 pulses 0.2s 5s 50s, 2 -100V -150V 1h 90ms 100ms 0.1s, 50 3b +75V +100V 1h 90ms 100ms 0.1s, 50 4 -6V -7V 1 pulse 100ms, 0.01 5b(2) +65V +87V 1 pulse 400ms, 2 1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b. 2. Valid in case of external load dump clamp: 40V maximum referred to ground. Table 16. Electrical transient requirements (part 2/3) ISO 7637-2: 2004E Test pulse Test level results III VI 1 C C 2a C C 3a C C 3b C C 4 C C 5b(1) C C 1. Valid in case of external load dump clamp: 40V maximum referred to ground. Table 17. Class 18/33 Electrical transient requirements (part 3/3) Contents C All functions of the device performed as designed after exposure to disturbance. E One or more functions of the device did not perform as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device. Doc ID 16009 Rev 11 VNH5050A-E 2.4 Electrical specifications Waveforms Figure 9. Waveforms in full-bridge operation NORMAL OPERATION (DIAGA/ENA=1, DIAGB/ENB=1) LOAD CONNECTED BETWEEN OUTA, OUTB DIAGA/ENA DIAGB/ENB INA INB PWM OUTA OUTB IOUTA->OUTB CS (*) tDEL CS_DIS tDEL (*) CS BEHAVIOUR DURING PWM MODE DEPENDS ON PWM FREQUENCY AND DUTY CYCLE NORMAL OPERATION (DIAGA/ENA=1, DIAGB/ENB=0 and DIAGA/ENA=0, DIAGB/ENB=1) LOAD CONNECTED BETWEEN OUTA, OUTB DIAGA/ENA DIAGB/ENB INA INB PWM OUTA OUTB IOUTA->OUTB CS CS_DIS CURRENT LIMITATION/THERMAL SHUTDOWN or OUTA SHORTED TO GROUND INA INB ILIM IOUTA->OUTB Tj =TTSD TTSD_HSA TTR_HSA Tj < TTSD TjHSA Tj > TTR DIAGA/ENA DIAGB/ENB CS CS_DIS current limitation normal operation power limitation OUTA shorted to ground Doc ID 16009 Rev 11 normal operation 19/33 Electrical specifications VNH5050A-E Figure 10. Waveforms in full-bridge operation (continued) OUTA shorted to VCC (resistive short) and undervoltage shutdown CS_DIS INA INB OUTA OUTB IOUTA->OUTB ISD_LS ILSA TTSD_LS Tj_LSA DIAGB/ENB DIAGA/ENA CS V<nominal normal operation OUTA softly shorted to VCC normal operation undervoltage shutdown OUTA shorted to VCC (pure short) and undervoltage shutdown CS_DIS INA INB OUTA OUTB IOUTA->OUTB ISD_LS ILSA TTSD_LS Tj_LSA DIAGB/ENB DIAGA/ENA CS V<nominal normal operation OUTA hardly shorted to VCC 20/33 Doc ID 16009 Rev 11 normal operation undervoltage shutdown VNH5050A-E 3 Application information Application information In normal operating conditions the DIAGX/ENX pin is considered as an input pin by the device. This pin must be externally pulled high. PWM pin usage: In all cases, a "0" on the PWM pin turns off both LSA and LSB switches. When PWM rises back to "1", LSA or LSB turn on again depending on the input pin state. Figure 11. Typical application circuit for DC to 20 kHz PWM operation short circuit protection VCC Reg 5V +5V + 5V VCC 3.3K 3.3K DIAGB/ENB 1K 1K DIAGA/ENA 1K HSA HSB PWM C OUTA 1K OUTB INA INB LSA 10K 33nF 1K LSB CS C M 1.5K GNDB GNDA S 100K G b) N MOSFET D Note: The value of the blocking capacitor (C) depends on the application conditions and defines voltage and current ripple on supply line at PWM operation. Stored energy of the motor inductance may fly back into the blocking capacitor, if the bridge driver goes into 3-state. This causes a hazardous overvoltage if the capacitor is not big enough. As basic orientation, 500F per 10A load current is recommended. In case of a fault condition the DIAGX/ENX pin is considered as an output pin by the device. The fault conditions are: - Overtemperature on one or both high-sides - Short to battery condition on the output (over current detection on the low-side Power MOSFET) Possible origins of fault conditions may be: OUTA is shorted to ground overtemperature detection on high-side A OUTA is shorted to VCC low-side Power MOSFET over current detection When a fault condition is detected, the user can identify which power element is in fault by monitoring the INA, INB, DIAGA/ENA and DIAGB/ENB pins. Doc ID 16009 Rev 11 21/33 Application information VNH5050A-E In any case, when a fault is detected, the faulty leg of the bridge is latched off. To turn on the respective output (OUTX) again, the input signal must rise from low to high level. Figure 12. Behavior in fault condition (how a fault can be cleared) Note: In case of the fault condition is not removed, the procedure for unlatching and sending the device in Stby mode is: - Clear the fault in the device (toggle: INA if ENA = 0 or INB if ENB = 0) - Pull low all inputs, PWM and Diag/EN pins within tDEL. If the Diag/En pins are already low, PWM = 0, the fault can be cleared simply toggling the input. The device enters in stby mode as soon as the fault is cleared. 3.1 Reverse battery protection Three possible solutions can be considered: - A Schottky diode D connected to VCC pin - An N-channel MOSFET connected to the GND pin (see Figure 11) - A P-channel MOSFET connected to the VCC pin The device sustains no more than -25 A in reverse battery conditions because of the two body diodes of the Power MOSFETs. Additionally, in reverse battery condition the I/Os of VNH5050A-E is pulled down to the VCC line (approximately -1.5 V). 22/33 Doc ID 16009 Rev 11 VNH5050A-E Application information Series resistor must be inserted to limit the current sunk from the microcontroller I/Os. If IRmax is the maximum target reverse current through C I/Os, series resistor is: V -V IOs CC R = --------------------------------I Rmax Figure 13. Half-bridge configuration VCC INA INB DIAGA/ENA DIAGB/ENB PWM INA INB DIAGA/ENA DIAGB/ENB PWM OUTA M OUTB GND GND Note: OUTB OUTA The VNH5050A-E can be used as a high power half-bridge driver. Figure 14. Multi-motors configuration VCC INA INB DIAGA/ENA DIAGB/ENB PWM INA INB DIAGA/ENA DIAGB/ENB PWM OUTA OUTB M2 GND GND M1 Note: OUTB OUTA M3 The VNH5050A-E can easily be designed in multi-motors driving applications such as seat positioning systems where only one motor has to be driven at a time. DIAGX/ENX pins allow to put unused half-bridges in high impedance. Doc ID 16009 Rev 11 23/33 Package and PCB thermal data VNH5050A-E 4 Package and PCB thermal data 4.1 PowerSSO-36 thermal data Figure 15. PowerSSO-36TM PC board Double layers: footprint Double layers: 2cm2 of Cu Double layers: 8cm2 of Cu Four layers: Cu on top layer: 16 cm2; Cu on bottom layer: 32 cm2; Cu on middle layer: total coverage Note: 24/33 Board finish thickness 1.6 mm +/- 10%, Board double layers and four layers, Board dimension 129x60, Board Material FR4, Cu thickness 0.070mm (front and back side), Thermal vias spaced on a 1.2 mm x 1.2 mm grid, Vias pad clearance thickness 0.2 mm, Thermal via diameter 0.3 mm +/- 0.08 mm, Cu thickness on vias 0.025 mm, Footprint dimension 4.1 mm x 6.5 mm. Doc ID 16009 Rev 11 VNH5050A-E Package and PCB thermal data Figure 16. Chipset configuration HIGH SIDE CHIP HSAB LOW SIDE CHIP A LOW SIDE CHIP B LSA LSB Figure 17. Auto and mutual Rthj-amb vs PCB copper area in open box free air condition 80 RthA 70 RthB = RthC 60 RthAB = RthAC RthBC 50 40 C/W 30 20 10 0 0 2 4 6 8 10 12 cm2 of Cu Area (refer to PCB layout) 4.1.1 Thermal calculation in clockwise and anti-clockwise operation in steady-state mode Table 18. Thermal calculation in clockwise and anti-clockwise operation in steadystate mode HSA HSB LSA LSB 4.1.2 TjHSAB TjLSA TjLSB ON OFF OFF ON PdHSA x RthHS + PdLSB PdHSA x RthHSLS + x RthHSLS + Tamb PdLSB x RthLSLS + Tamb PdHSA x RthHSLS + PdLSB x RthLS + Tamb OFF PdHSB x RthHS + PdLSA PdHSB x RthHSLS + x RthHSLS + Tamb PdLSA x RthLS + Tamb PdHSB x RthHSLS + PdLSA x RthLSLS + Tamb ON ON OFF Thermal resistances definition (values according to the PCB heatsink area) RthHS = RthHSA = RthHSB = High Side Chip Thermal Resistance Junction to Ambient (HSA or HSB in ON state) RthLS = RthLSA = RthLSB = Low Side Chip Thermal Resistance Junction to Ambient Doc ID 16009 Rev 11 25/33 Package and PCB thermal data VNH5050A-E RthHSLS = RthHSALSB = RthHSBLSA = Mutual Thermal Resistance Junction to Ambient between High Side and Low Side Chips RthLSLS = RthLSALSB = Mutual Thermal Resistance Junction to Ambient between Low Side Chips 4.1.3 Thermal calculation in transient mode(a) TjHSAB = ZthHS x PdHSAB + ZthHSLS x (PdLSA + PdLSB) + Tamb TjLSA = ZthHSLS x PdHSAB + ZthLS x PdLSA + ZthLSLS x PdLSB + Tamb TjLSB = ZthHSLS x PdHSAB + ZthLSLS x PdLSA + ZthLS x PdLSB + Tamb Single pulse thermal impedance definition (values according to the PCB heatsink area). ZthHS = High Side Chip Thermal Impedance Junction to Ambient ZthLS = ZthLSA = ZthLSB = Low Side Chip Thermal Impedance Junction to Ambient ZthHSLS = ZthHSABLSA = ZthHSABLSB = Mutual Thermal Impedance Junction to Ambient between High Side and Low Side Chips ZthLSLS = ZthLSALSB = Mutual Thermal Impedance Junction to Ambient between Low Side Chips Figure 18. Detailed chipset configuration CHIP 1 Zhs Zhsls Zhsls CHIP 3 CHIP 2 Zls Zlsls Zls Equation 1: pulse calculation formula Z TH = R TH * ( + Z THtp ( 1 - ) ) where = t p T a. Calculation is valid in any dynamic operating condition. Pd values set by user. 26/33 Doc ID 16009 Rev 11 VNH5050A-E Package and PCB thermal data Figure 19. PowerSSO-36 HSD thermal impedance junction ambient single pulse 100 C/W 10 HSD-footprint HSD-2 cm^2 Cu HSD-8 cm^2 Cu HSD-4 Layer HsLsD-footprint HsLsD-2 cm^2 Cu HsLsD-8 cm^2 Cu HsLsD-4 Layer 1 0.1 0.001 0.01 0.1 time (sec) 1 10 100 1000 Figure 20. PowerSSO-36 LSD thermal impedance junction ambient single pulse 100 10 C/W Z ls Z lsls LSD-footprint LSD-2 cm^2 Cu LSD-8 cm^2 Cu LSD-4 Layer LsLsD-footprint LsLsD-2 cm^2 Cu LsLsD-8 cm^2 Cu LsLsD-4 Layer 1 0.1 0.001 0.01 0.1 time (sec) 1 Doc ID 16009 Rev 11 10 100 1000 27/33 Package and PCB thermal data VNH5050A-E Figure 21. Thermal fitting model of an H-bridge in PowerSSO-36 Table 19. Thermal parameters(1) Area/island (cm2) Footprint R1 = R7 (C/W) 0.4 R2 = R8 (C/W) 2 2 8 4L R3 (C/W) 8 R4 (C/W) 30 16 16 10 R5 (C/W) 40 22 12 5 R6 (C/W) 36 28 10 6 R9 = R15 (C/W) 0.1 R10 = R16 (C/W) 3.6 R11 = R17 (C/W) 22 14 14 14 R12 = R18 (C/W) 49 30 30 20 R13 = R19 (C/W) 52 36 28 16 R14 = R20 (C/W) 50 32 26 18 R21 = R22 (C/W) 80 60 50 40 R23 (C/W) 80 50 45 30 0.8 C1 = C7 = C9 = C15 (W.s/C) 0.0005 C2 = C8 (W.s/C) 0.008 C3 (W.s/C) 0.09 C4 (W.s/C) 0.5 0.8 0.8 C5 (W.s/C) 0.8 1.4 2 3 C6 (W.s/C) 5 6 8 10 C10 = C16 (W.s/C) 0.009 C11 = C17 (W.s/C) 0.07 C12 = C18 (W.s/C) 0.45 0.45 0.45 0.6 C13 = C19 (W.s/C) 0.8 1 1.2 2.5 C14 = C20 (W.s/C) C21 = C22 = C23 (W.s/C) 4 5 6 8 0.01 0.006 0.005 0.005 1. The blank space means that the value is the same as the previous one. 28/33 Doc ID 16009 Rev 11 VNH5050A-E Package and packing information 5 Package and packing information 5.1 ECOPACK(R) packages In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 5.2 PowerSSO-36 TP package information Figure 22. PowerSSO-36 TP package dimensions Doc ID 16009 Rev 11 29/33 Package and packing information Table 20. VNH5050A-E PowerSSO-36 TP mechanical data Millimeters Symbol Min. Typ. Max. A 2.15 - 2.47 A2 2.15 - 2.40 a1 0 - 0.1 b 0.18 - 0.36 c 0.23 - 0.32 D 10.10 - 10.50 E 7.4 - 7.6 e - 0.5 - e3 - 8.5 - F 2.3 G - - 0.1 H 10.1 - 10.5 h - - 0.4 k 0 deg L 0.6 M N 30/33 8 deg - 1 4.3 - - O 1.2 Q 0.8 S 2.9 T 3.65 U 1.0 10 deg X1 1.85 2.35 Y1 3 3.5 X2 1.85 2.35 Y2 3 3.5 X3 4.7 - 5.2 Y3 3 - 3.5 Z1 0.4 Z2 0.4 Doc ID 16009 Rev 11 VNH5050A-E 5.3 Package and packing information PowerSSO-36 TP packing information Figure 23. PowerSSO-36 TP tube shipment (no suffix) Base Qty Bulk Qty Tube length (0.5) A B C (0.1) C B 49 1225 532 3.5 13.8 0.6 All dimensions are in mm. A Figure 24. PowerSSO-36 TP tape and reel shipment (suffix "TR") Reel dimensions Base Qty Bulk Qty A (max) B (min) C (0.2) F G (+2 / -0) N (min) T (max) 1000 1000 330 1.5 13 20.2 24.4 100 30.4 Tape dimensions According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 (0.1) P D (0.05) D1 (min) F (0.1) K (max) P1 (0.1) 24 4 12 1.55 1.5 11.5 2.85 2 End All dimensions are in mm. Start Top cover tape No components Components 500mm min No components 500mm min Empty components pockets sealed with cover tape. User direction of feed Doc ID 16009 Rev 11 31/33 Revision history 6 VNH5050A-E Revision history Table 21. Document revision history Date Revision 06-Jul-2009 1 Initial release. 2 Updated Figure 1: Block diagram. Updated following tables: - Table 2: Block description - Table 6: Absolute maximum ratings - Table 8: Power section - Table 11: Protections and diagnostics - Table 12: Current sense (9 V < VCC < 18 V) - Table 14: Truth table in fault conditions (detected on OUTA) Updated Chapter 3: Application information. Modified Table 12: Current sense (9 V < VCC < 18 V). 02-Dec-2009 3 Updated following tables: - Table 8: Power section - Table 10: Switching (VCC = 13 V, RLOAD = 1.5 ) - Table 11: Protections and diagnostics - Table 12: Current sense (9 V < VCC < 18 V) Added Chapter 4: Package and PCB thermal data 16-Dec-2009 4 Updated Table 4: Pin definitions and functions 02-Mar-2010 5 Updated Table 14: Truth table in fault conditions (detected on OUTA). 30-Apr-2010 6 Updated following tables: - Table 10: Switching (VCC = 13 V, RLOAD = 1.5 ) - Table 11: Protections and diagnostics 30-Jun-2010 7 Updated following tables: - Table 7: Thermal data - Table 8: Power section - Table 12: Current sense (9 V < VCC < 18 V) 05-Jul-2010 8 Updated Table 19: Thermal parameters. 9 Updated Table 12: Current sense (9 V < VCC < 18 V) Updated Section 4.1.3: Thermal calculation in transient mode Added Figure 18: Detailed chipset configuration 22-Dec-2011 10 Updated Figure 1: Block diagram Added Table 3: Suggested connections for unused and not connected pins Table 11: Protections and diagnostics: - TTSD, TTR, THYST: added note Updated Figure 9: Waveforms in full-bridge operation and Figure 10: Waveforms in full-bridge operation (continued) 19-Sep-2013 11 Updated Disclaimer. 15-Sep-2009 19-Oct-2010 32/33 Description of changes Doc ID 16009 Rev 11 VNH5050A-E Please Read Carefully: Information in this document is provided solely in connection with ST products. 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