Precision JFET, High Speed, Dual Operational Amplifier OP249 PIN CONFIGURATIONS Fast slew rate: 22 V/s typical Settling time (0.01%): 1.2 s maximum Offset voltage: 200 V typical High open-loop gain: 1000 V/mV minimum Low total harmonic distortion: 0.002% typical OUT A 1 -IN A 2 +IN A 3 V- 4 OP249 A B 8 V+ 7 OUT B 6 -IN B 5 +IN B 00296-001 FEATURES Figure 1. 8-Lead CERDIP (Q-8) and 8-Lead PDIP (N-8) Output amplifier for fast DACs Signal processing Instrumentation amplifiers Fast sample-and-holds Active filters Low distortion audio amplifiers Input buffer for ADCs Servo controllers +IN A 1 8 -IN A V- 2 A 7 OUT A +IN B 3 OP249 6 V+ -IN B 4 B 5 OUT B 00296-002 APPLICATIONS Figure 2. 8-Lead SOIC (R-8) GENERAL DESCRIPTION The OP249 is a high speed, precision dual JFET op amp, similar to the popular single op amp. The OP249 outperforms available dual amplifiers by providing superior speed with excellent dc performance. Ultrahigh open-loop gain (1 kV/mV minimum), low offset voltage, and superb gain linearity makes the OP249 the industry's first true precision, dual high speed amplifier. Symmetrical slew rate, even when driving large load, such as, 600 or 200 pF of capacitance and ultralow distortion, make the OP249 ideal for professional audio applications, active filters, high speed integrators, servo systems, and buffer amplifiers. With a slew rate of 22 V/s typical and a fast settling time of less than 1.2 s maximum to 0.01%, the OP249 is an ideal choice for high speed bipolar DAC and ADC applications. The excellent dc performance of the OP249 allows the full accuracy of high resolution CMOS DACs to be realized. 10mV 500ns Figure 3. Fast Settling (0.01%) TA = 25C VS = 15V VO = 10V p-p RL = 10k AV = 1 0.001 20 100 90 100 1k 10 0% 5V 1s 10k 20k Figure 4. Low Distortion, AV = 1, RL = 10 k 00296-005 10 0% 00296-003 100 90 00296-004 0.01 870ns Figure 5. Excellent Output Drive, RL = 600 Rev. G Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)1989-2010 Analog Devices, Inc. All rights reserved. OP249 TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ..............................................7 Applications ....................................................................................... 1 Applications Information .............................................................. 13 Pin Configurations ........................................................................... 1 Open-Loop Gain Linearity ....................................................... 14 General Description ......................................................................... 1 Offset Voltage Adjustment ........................................................ 14 Revision History ............................................................................... 2 Settling Time ............................................................................... 14 Specifications..................................................................................... 3 DAC Output Amplifier .............................................................. 15 Electrical Characteristics ............................................................. 3 Discussion on Driving ADCs ................................................... 16 Absolute Maximum Ratings............................................................ 6 Outline Dimensions ....................................................................... 17 ESD Caution .................................................................................. 6 Ordering Guide .......................................................................... 18 REVISION HISTORY 4/10--Rev. F to Rev. G Changes to Features Section and General Description Section . 1 Changes to Offset Voltage Parameter, Table 1 .............................. 3 Deleted Long Term Offset Voltage Parameter and Note 1, Table 1 ................................................................................... 3 Changes to Offset Voltage Parameter, Offset Voltage Temperature Coefficient Parameter, and Note 1, Table 3 ........... 5 Delete OP249F Columns, Table 3................................................... 5 Changes to Offset Voltage Parameter and Offset Voltage Temperature Coefficient Parameter, Table 4................................. 5 Inserted OP249F Columns, Table 4 ............................................... 5 Changes to Discussion on Driving ADCs Section ..................... 16 Deleted Figure 52 and Figure 53 ................................................... 17 9/01--Rev. D to Rev. E Edits to Features and Pin Connections ..........................................1 Edits to Electrical Characteristics .............................................. 2, 3 Edits to Absolute Maximum Ratings, Package Type, and Ordering Guide..................................................................................4 Deleted Wafer Test Limits and Dice Characteristics Section ......5 Edits to Typical Performance Characteristics ................................8 Edits to Macro-Model Figure........................................................ 15 Edits to Outline Dimensions......................................................... 17 5/07--Rev. E to Rev. F Updated Format .................................................................. Universal Changes to Table 1 ............................................................................ 3 Changes to Table 2 ............................................................................ 4 Changes to Table 3 and Table 4 ....................................................... 5 Changes to Table 5 ............................................................................ 6 Changes to Figure 31 ...................................................................... 11 Changes to Figure 37 and Figure 38 ............................................. 12 Deleted OP249 SPICE Macro-Model Section ............................ 14 Deleted Figure 18; Renumbered Sequentially ............................ 14 Deleted Table I ................................................................................ 15 Changes to Discussion on Driving ADCs Section ..................... 17 Updated Outline Dimensions ....................................................... 18 Changes to Ordering Guide .......................................................... 19 Rev. G | Page 2 of 20 OP249 SPECIFICATIONS ELECTRICAL CHARACTERISTICS VS = 15 V, TA = 25C, unless otherwise noted. Table 1. Parameter Offset Voltage Offset Stability Input Bias Current Input Offset Current Input Voltage Range 1 Symbol VOS Conditions VCM = 0 V Min IB IOS IVR VCM = 0 V, TA = 25C VCM = 0 V, TA = 25C OP249A Typ 0.2 1.5 30 6 12.5 Max 0.75 75 25 11 Common-Mode Rejection Power-Supply Rejection Ratio Large Signal Voltage Gain Output Voltage Swing CMR PSRR AVO VO VCM = 11 V VS = 4.5 V to 18 V VO = 10 V, RL = 2 k RL = 2 k 80 1000 ISC 80 31.6 500 20 Supply Current Slew Rate Gain Bandwidth Product 2 Settling Time Phase Margin Differential Input Impedance Open-Loop Output Resistance Voltage Noise Voltage Noise Density ISY SR GBW tS M ZIN RO en p-p en Current Noise Density Voltage Supply Range in VS 1 2 3 No load, VO = 0 V RL = 2 k, CL = 50 pF 18 3.5 10 V step 0.01% 3 0 dB gain 0.1 Hz to 10 Hz fO = 10 Hz fO = 100 Hz fO = 1 kHz fO = 10 kHz fO = 1 kHz 4.5 Guaranteed by CMR test. Guaranteed by design. Settling time is sample tested. Rev. G | Page 3 of 20 Max 0.9 75 25 -12.5 90 12 1200 12.5 50 12.0 -12.5 36 Output shorted to ground OP249F Typ 0.2 1.5 30 6 12.5 11 -12.5 90 12 1400 12.5 12.0 Short-Circuit Current Limit Min -12.5 36 50 -33 5.6 22 4.7 0.9 55 1012||6 35 2 75 26 17 16 0.003 15 20 7.0 18 3.5 1.2 18 4.5 50 -33 5.6 22 4.7 0.9 55 1012||6 35 2 75 26 17 16 0.003 15 7.0 1.2 18 Unit mV V/month pA pA V V V dB V/V V/mV V V V mA mA mA mA V/s MHz s Degrees ||pF V p-p nV/Hz nV/Hz nV/Hz nV/Hz pA/Hz V OP249 VS = 15 V, TA = 25C, unless otherwise noted. Table 2. Parameter Offset Voltage Input Bias Current Input Offset Current Input Voltage Range 1 Symbol VOS IB IOS IVR Conditions VCM = 0 V VCM = 0 V, TA = 25C VCM = 0 V TA = 25C Min OP249G Typ 0.4 40 10 12.5 Max 2.0 75 25 -12.0 90 12 1100 12.5 50 11 Common-Mode Rejection Power Supply Rejection Ratio Large Signal Voltage Gain Output Voltage Swing CMR PSRR AVO VO VCM = 11 V VS = 4.5 V to 18 V VO = 10 V; RL = 2 k RL = 2 k 76 500 12.0 Short-Circuit Current Limit ISC -12.5 36 Output shorted to ground 20 Supply Current Slew Rate Gain Bandwidth Product 2 Settling Time Phase Margin Differential Input Impedance Open-Loop Output Resistance Voltage Noise Voltage Noise Density ISY SR GBW tS M ZIN RO en p-p en Current Noise Density Voltage Supply Range in VS 1 2 No load; VO = 0 V RL = 2 k, CL = 50 pF 18 10 V step 0.01% 0 dB gain 0.1 Hz to 10 Hz fO = 10 Hz fO = 100 Hz fO = 1 kHz fO = 10 kHz fO = 1 kHz 4.5 Guaranteed by CMR test. Guaranteed by design. Rev. G | Page 4 of 20 50 -33 5.6 22 4.7 0.9 55 1012||6 35 2 75 26 17 16 0.003 15 7.0 1.2 18 Unit mV pA pA V V V dB V/V V/mV V V V mA mA mA mA V/s MHz s Degree ||pF V p-p nV/Hz nV/Hz nV/Hz nV/Hz pA/Hz V OP249 VS = 15 V, -55C TA +125C for A grade, unless otherwise noted. Table 3. Parameter Offset Voltage Symbol VOS Conditions VCM = 0 V Offset Voltage Temperature Coefficient Input Bias Current 1 Input Offset Current1 Input Voltage Range 2 TCVOS IB IOS IVR VCM = 0 V Min OP249A Typ Max 0.12 1.0 1 4 0.04 12.5 10 20 4 11 Common-Mode Rejection Power Supply Rejection Ratio Large Signal Voltage Gain Output Voltage Swing CMR PSRR AVO VO VCM = 11 V VS = 4.5 V to 18 V RL = 2 k; VO = 10 V RL = 2 k 76 500 -12.5 110 5 1400 12.5 50 12 Supply Current 1 2 ISY -12.5 5.6 No load, VO = 0 V 7.0 Unit mV V/C nA nA V V V dB V/V V/mV V V V mA TA = 125C. Guaranteed by CMR test. VS = 15 V, -40C TA +85C, unless otherwise noted. Table 4. Parameter Offset Voltage Offset Voltage Temperature Coefficient Input Bias Current 1 Input Offset Current1 Input Voltage Range 2 Symbol VOS TCVOS IB IOS IVR Conditions VCM = 0 V VCM = 0 V Min OP249F Typ 0.5 2.2 0.3 0.02 12.5 Max 1.1 12 4.0 1.2 11 Common-Mode Rejection Power Supply Rejection Ratio Large Signal Voltage Gain Output Voltage Swing CMR PSRR AVO VO VCM = 11 V VS = 4.5 V to 18 V RL = 2 k; VO = 10 V RL = 2 k 80 250 1 2 ISY No load, VO = 0 V TA = 85C. Guaranteed by CMR test. Rev. G | Page 5 of 20 OP249G Typ 1.0 6 0.5 0.04 12.5 Max 3.6 25 4.5 1.5 -12.5 95 10 1200 12.5 100 11 -12.5 90 7 1200 12.5 76 100 250 12 Supply Current Min 12.0 -12.5 5.6 7.0 -12.5 5.6 7.0 Unit mV V/C nA nA V V V dB V/V V/mV V V V mA OP249 ABSOLUTE MAXIMUM RATINGS Table 5. 1 Parameter Supply Voltage Input Voltage 2 Differential Input Voltage2 Output Short-Circuit Duration Storage Temperature Range Operating Temperature Range OP249A (Q) OP249F (Q) OP249G (N, R) Junction Temperature Range OP249A (Q), OP249F (Q) OP249G (N, R) Lead Temperature (Soldering, 60 sec) 1 2 Rating 18 V 18 V 36 V Indefinite -65C to +175C -55C to +125C -40C to +85C -40C to +85C -65C to +175C -65C to +150C 300C Absolute maximum ratings apply to packaged parts, unless otherwise noted. For supply voltages less than 18 V, the absolute maximum input voltage is equal to the supply voltage. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 6. Thermal Resistance Package Type 8-Lead CERDIP (Q) 8-Lead PDIP (N) 8-Lead SOIC (R) 1 JA1 134 96 150 JC 12 37 41 Unit C/W C/W C/W JA is specified for worst-case mounting conditions, that is, JA is specified for device in socket for CERDIP and PDIP packages; JA is specified for device soldered to printed circuit board for SOIC package. ESD CAUTION Rev. G | Page 6 of 20 OP249 TYPICAL PERFORMANCE CHARACTERISTICS 120 120 GAIN 60 40 45 90 PHASE m = 55 20 135 0 180 10k 100k 1M 225 100M 10M FREQUENCY (Hz) +PSRR 60 -PSRR 40 20 0 10 00296-006 -20 1k 80 m 6 GBW 4 -50 -25 0 25 50 75 100 2 125 TEMPERATURE (C) 24 -SR 22 +SR 20 16 -75 -25 0 25 50 75 100 125 Figure 10. Slew Rate vs. Temperature 28 140 TA = 25C VS = 15V TA = 25C VS = 15V RL = 2k 26 SLEW RATE (V/s) 100 80 60 24 22 20 40 0 100 1k 10k 100k 1M 16 10M 00296-011 18 20 00296-008 COMMON-MODE REJECTION (dB) -50 TEMPERATURE (C) Figure 7. Phase Margin, Gain Bandwidth Product vs. Temperature 120 1M 18 00296-007 45 -75 100k VS = 15V RL = 2k CL = 50pF 26 SLEW RATE (V/s) PHASE MARGIN (C) GAIN BANDWIDTH PRODUCT (MHz) 8 50 10k 28 10 55 1k Figure 9. Power Supply Rejection vs. Frequency VS = 15V 60 100 FREQUENCY (Hz) Figure 6. Open-Loop Gain, Phase vs. Frequency 65 00296-009 0 PHASE (C) OPEN-LOOP GAIN (dB) 80 100 00296-010 100 POWER SUPPLY REJECTION (dB) TA = 25C VS = 15V TA = 25C VS = 15V RL = 2k 0 0.2 0.4 0.6 0.8 DIFFERENTIAL INPUT VOLTAGE (V) FREQUENCY (Hz) Figure 11. Slew Rate vs. Differential Input Voltage Figure 8. Common-Mode Rejection vs. Frequency Rev. G | Page 7 of 20 1.0 OP249 35 0.01 TA = 25C VS = 15V VO = 10V p-p RL = 10k AV = 1 TA = 25C VS = 15V SLEW RATE (V/s) 30 25 NEGATIVE 20 POSITIVE 15 5 0 100 200 300 400 0.001 20 500 00296-015 00296-012 10 100 1k 10k 20k CAPACITIVE LOAD (pF) Figure 15. Distortion vs. Frequency Figure 12. Slew Rate vs. Capacitive Load 10 8 6 TA = 25C VS = 15V VO = 10V p-p RL = 2k AV = 1 0.1% 4 0.01% 2 0 -2 0.01% -4 0.1% 00296-013 -6 -8 -10 0 200 400 600 800 0.001 20 1000 00296-016 OUTPUT STEP SIZE (V) 0.01 TA = 25C VS = 15V AVCL = 1 100 1k 10k 20k 10k 20k SETTLING TIME (ns) Figure 13. Step Size vs. Settling Time Figure 16. Distortion vs. Frequency 100 0.01 TA = 25C VS = 15V VO = 10V p-p RL = 600 AV = 1 80 60 40 20 0 0 100 1k 10k 0.001 20 FREQUENCY (Hz) 00296-017 00296-014 VOLTAGE NOISE DENSITY (nV/ Hz) TA = 25C VS = 15V 100 1k Figure 17. Distortion vs. Frequency Figure 14. Voltage Noise Density vs. Frequency Rev. G | Page 8 of 20 OP249 500mV 0.1 1s TA = 25C VS = 15V VO = 10V p-p RL = 10k AV = 1 +1V 00296-018 0.01 20 00296-021 -1V 100 1k 10k BANDWIDTH (0.1Hz TO 10Hz) TA = 25C, VS = 15V 20k Figure 21. Low Frequency Noise Figure 18. Distortion vs. Frequency 60 TA = 25C VS = 15V 0.1 TA = 25C VS = 15V VO = 10V p-p RL = 2k AV = 10 CLOSED-LOOP GAIN (dB) 50 40 AVCL = 100 30 20 10 0 AVCL = 10 AVCL = 5 AVCL = 1 0.01 20 100 1k 10k -20 1k 00296-022 00296-019 -10 10k 20k 100k 1M 10M 100M FREQUENCY (Hz) Figure 19. Distortion vs. Frequency Figure 22. Closed-Loop Gain vs. Frequency 50 TA = 25C VS = 15V 0.1 TA = 25C VS = 15V VO = 10V p-p RL = 600k AV = 10 IMPEDANCE () 40 30 AVCL = 1 20 AVCL = 10 10 0.01 20 100 1k 10k 0 100 20k 1k 10k 00296-023 00296-020 AVCL = 100 100k 1M FREQUENCY (Hz) Figure 20. Distortion vs. Frequency Figure 23. Closed-Loop Output Impedance vs. Frequency Rev. G | Page 9 of 20 10M OP249 30 20 OUTPUT VOLTAGE SWING (V) 20 15 AD8512 10 OP249 5 0 1k 1M 5 0 -5 -10 -15 00296-024 AD712 10 -20 10M 00296-027 OUTPUT VOLTAGE (V p-p) TA = 25C RL = 2k 15 25 0 5 FREQUENCY (Hz) Figure 24. Output Voltage vs. Frequency VS = 15V NO LOAD AVCL = 1 NEGATIVE EDGE 50 AVCL = 1 POSITIVE EDGE 40 30 10 00296-025 20 AVCL = 5 0 100 200 300 400 5.8 5.6 5.4 5.2 -75 500 00296-028 60 SUPPLY CURRENT (mA) 70 OVERSHOOT (%) 20 6.0 VS = 15V RL = 2k VIN = 100mV p-p 80 -50 -25 0 LOAD CAPACITANCE (pF) 50 75 100 125 Figure 28. Supply Current vs. Temperature 16 14 25 TEMPERATURE (C) Figure 25. Small Overshoot vs. Load Capacitance 6.0 TA = 25C VS = 15V 5.8 SUPPLY CURRENT (mA) 12 +VOHM = |-VOHM| 10 8 6 4 TA = +25C 5.6 TA = +125C 5.4 TA = -55C 2 0 100 1k 00296-029 5.2 00296-026 MAXIMUM OUTPUT SWING (V) 15 Figure 27. Output Voltage Swing vs. Supply Voltage 90 0 10 SUPPLY VOLTAGE (V) 5.0 10k 0 LOAD RESISTANCE () 5 10 15 SUPPLY VOLTAGE (V) Figure 29. Supply Current vs. Supply Voltage Figure 26. Maximum Output Voltage Swing vs. Load Resistance Rev. G | Page 10 of 20 20 OP249 180 10k TA = 25C VS = 15V 415 x OP249 (830 OP AMPS) INPUT BIAS CURRENT (pA) 140 VS = 15V VCM = 0V UNITS 120 100 80 60 40 0 -1000 -800 -600 -400 -200 00296-030 20 0 200 400 600 800 1k 100 10 1 -75 1000 00296-033 160 -50 -25 VOS (V) Figure 30. VOS Distribution (N-8) 240 100 125 103 BIAS CURRENT (pA) 180 150 120 90 102 101 00296-031 60 30 0 2 4 6 8 10 12 14 16 18 20 22 100 -15 24 00296-034 UNITS 75 TA = 25C VS = 15V 210 -10 TCVOS (V/C) -5 0 5 10 15 COMMON-MODE VOLTAGE (V) Figure 31. TCVOS Distribution (N-8) Figure 34. Bias Current vs. Common-Mode Voltage 50 50 TA = 25C VS = 15V VS = 15V 40 INPUT BIAS CURRENT (pA) 40 30 20 10 30 20 0 1 2 3 4 0 5 TIME AFTER POWER APPLIED (Minutes) 00296-035 10 00296-032 OFFSET VOLTAGE (V) 50 104 VS = 15V -40C TO +85C (830 OP AMPS) 270 0 25 Figure 33. Input Bias Current vs. Temperature 300 0 0 TEMPERATURE (C) 0 2 4 6 8 TIME AFTER POWER APPLIED (Minutes) Figure 32. Offset Voltage Warm-Up Drift Figure 35. Bias Current Warm-Up Drift Rev. G | Page 11 of 20 10 OP249 80 80 40 20 0 -75 -50 -25 0 25 50 75 100 VS = 15V 8000 RL = 10k RL = 2k 2000 00296-037 OPEN-LOOP GAIN (V/mV) 10000 -50 -25 0 25 50 40 20 -50 -25 0 25 50 75 100 125 Figure 38. Short-Circuit Output Current vs. Junction Temperature 12000 0 -75 SINK TEMPERATURE (C) Figure 36. Input Offset Current vs. Temperature 4000 SOURCE 60 0 -75 125 TEMPERATURE (C) 6000 VS = 15V 00296-038 SHORT-CIRCUIT OUTPUT CURRENT (mA) 60 00296-036 INPUT OFFSET CURRENT (pA) TA = 25C VCM = 0V 75 100 125 TEMPERATURE (C) Figure 37. Open-Loop Gain vs. Temperature Rev. G | Page 12 of 20 OP249 APPLICATIONS INFORMATION V+ +IN 100 90 VOUT -IN 10 0% 5V 1s A) OP249 00296-039 100 90 V- Figure 39. Simplified Schematic (1/2 OP249) 10 0% 1/2 OP249 +3V 5V 1 3 B) LT1057 5k 100 90 +18V 8 1/2 OP249 +3V 5 7 4 -18V 5k 00296-040 6 1s 10 0% Figure 40. Burn-In Circuit 5V The OP249 represents a reliable JFET amplifier design, featuring an excellent combination of dc precision and high speed. A rugged output stage provides the ability to drive a 600 load and still maintain a clean ac response. The OP249 features a large signal response that is more linear and symmetric than previously available JFET input amplifiers. Figure 41 compares the large signal response of the OP249 to other industry-standard dual JFET amplifiers. Typically, the slewing performance of the JFET amplifier is specified as a number of V/s. There is no discussion on the quality, that is, linearity and symmetry of the slewing response. 1s C) AD712 00296-041 2 Figure 41. Large-Signal Transient Response, AV = 1, VIN = 20 V p-p, ZL = 2 k//200 pF, VS = 15 V The OP249 was carefully designed to provide symmetrically matched slew characteristics in both the negative and positive directions, even when driving a large output load. The slewing limitation of the amplifier determines the maximum frequency at which a sinusoidal output can be obtained without significant distortion. However, it is important to note that the nonsymmetric slewing typical of previously available JFET amplifiers adds a higher series of harmonic energy content to the resulting response--and an additional dc output component. Examples of potential problems of nonsymmetric slewing behavior can be in audio amplifier applications, where a natural low distortion sound quality is desired and in servo or signal processing systems where a net dc offset cannot be tolerated. The linear and symmetric slewing feature of the OP249 makes it an ideal choice for applications that exceed the full power bandwidth range of the amplifier. Rev. G | Page 13 of 20 OP249 R4 R3 VIN 1/2 R5 50k VOUT OP249 R1 200k R2 31 VOS ADJUST RANGE = V R2 R1 00296-044 +V 100 90 -V Figure 44. Offset Adjustment for Inverting Amplifier Configuration +V 10 R5 1s R3 50k R1 200k R2 33 Figure 42. Small-Signal Transient Response, AV = 1, ZL = 2 k||100 pF, No Compensation, VS = 15 V -V As with most JFET input amplifiers, the output of the OP249 can undergo phase inversion if either input exceeds the specified input voltage range. Phase inversion does not damage the amplifier, nor does it cause an internal latch-up condition. Supply decoupling should be used to overcome inductance and resistance associated with supply lines to the amplifier. A 0.1 F and a 10 F capacitor should be placed between each supply pin and ground. OPEN-LOOP GAIN LINEARITY The OP249 has both an extremely high open-loop gain of 1 kV/mV minimum and constant gain linearity, which enhances its dc precision and provides superb accuracy in high closed-loop gain applications. Figure 43 illustrates the typical open-loop gain linearity--high gain accuracy is assured, even when driving a 600 load. OFFSET VOLTAGE ADJUSTMENT The inherent low offset voltage of the OP249 makes offset adjustments unnecessary in most applications. However, where a lower offset error is required, balancing can be performed with simple external circuitry, as shown in Figure 44 and Figure 45. R4 1/2 VOUT OP249 VOS ADJUST RANGE = V VIN GAIN = VOUT VIN =1+ R2 R1 R5 R4 + R2 00296-045 50mV 00296-042 0% R5 IF R2 << R4 =1+ R4 Figure 45. Offset Adjustment for Noninverting Amplifier Configuration In Figure 44, the offset adjustment is made by supplying a small voltage at the noninverting input of the amplifier. Resistors R1 and R2 attenuate the potentiometer voltage, providing a 2.5 mV (with VS = 15 V) adjustment range, referred to the input. Figure 45 shows the offset adjustment for the noninverting amplifier configuration, also providing a 2.5 mV adjustment range. As shown in the equations in Figure 45, if R4 is not much greater than R2, a resulting closed-loop gain error must be accounted for. SETTLING TIME The settling time is the time between when the input signal begins to change and when the output permanently enters a prescribed error band. The error bands on the output are 5 mV and 0.5 mV, respectively, for 0.1% and 0.01% accuracy. Figure 46 shows the settling time of the OP249, which is typically 870 ns. Moreover, problems in settling response, such as thermal tails and long-term ringing, are nonexistent. VERTICAL 50V/DIV INPUT VARIATION 870ns 100 90 10 10mV HORIZONTAL 5V/DIV OUTPUT CHARGE Figure 43. Open-Loop Gain Linearity; Variation in Open-Loop Gain Results in Errors in High Closed-Loop Gain Circuits; RL = 600 , VS = 15 V Rev. G | Page 14 of 20 500ns Figure 46. Settling Characteristics of the OP249 to 0.01% 00296-046 00296-043 0% OP249 Because the DAC output capacitance appears at the inputs of the op amp, it is essential that the amplifier be adequately compensated. Compensation increases the phase margin and ensures an optimal overall settling response. The required lead compensation is achieved with Capacitor C in Figure 48. DAC OUTPUT AMPLIFIER Unity-gain stability, a low offset voltage of 300 V typical, and a fast settling time of 870 ns to 0.01%, makes the OP249 an ideal amplifier for fast DACs. For CMOS DAC applications, the low offset voltage of the OP249 results in excellent linearity performance. CMOS DACs, such as the PM7545, typically have a code-dependent output resistance variation between 11 k and 33 k. The change in output resistance, in conjunction with the 11 k feedback resistor, results in a noise gain change, which causes variations in the offset error, increasing linearity errors. The OP249 features low offset voltage error, minimizing this effect and maintaining 12-bit linearity performance over the full-scale range of the converter. VDD 75 0.1F 18 VDD REFERENCE OR VIN 500 19 C 33pF 20 RFB OUT1 1 VREF 2 +15V 0.1F 8 1/2 PM7545 AGND 2 3 4 VOUT 1 OP249 0.1F DB11 TO DB0 DGND 3 -15V 00296-047 12 DATA INPUT Figure 47. Fast Settling and Low Offset Error of the OP249 Enhances CMOS DAC Performance--Unipolar Operation R4 20k 1% REFERENCE OR VIN 500 18 20 VDD RFB 19 VREF C +15V 33pF 0.1F OUT1 1 2 AGND 2 3 8 1/2 PM7545 OP249 DB11 TO DB0 DGND 12 R5 10k 1% 75 0.1F 1 R3 10k 1% 5 3 1/2 OP249 6 4 -15V DATA INPUT 7 VOUT 0.1F 00296-048 VDD Figure 48. Fast Settling and Low Offset Error of the OP249 Enhances CMOS DAC Performance--Bipolar Operation Rev. G | Page 15 of 20 OP249 A B 4s 4s 100 90 100 90 10 10 0% 0% 1s 500mV C = 5pF RESPONSE IS GROSSLY UNDERDAMPED, AND EXHIBITS RINGING 1s C = 15pF FAST RISE TIME CHARACTERISTICS, BUT AT EXPENSE OF SLIGHT PEAKING IN RESPONSE 00296-049 500mV Figure 49. Effect of Altering Compensation from Circuit in Figure 47--PM7545 CMOS DAC with 1/2 OP249, Unipolar Operation; Critically Damped Response Is Obtained with C 33 pF +15V Figure 49 illustrates the effect of altering the compensation on the output response of the circuit in Figure 47. Compensation is required to address the combined effect of the output capacitance of the DAC, the input capacitance of the op amp, and any stray capacitance. Slight adjustments to the compensation capacitor may be required to optimize settling response for any given application. 1/2 OP249 2 t S DAC t S AMP 4 7A13 PLUG-IN 1 0.1F * 7A13 PLUG-IN -15V 1k 300pF IOUT = +15V 2 |VREF | 1k 1.5k 2N3904 TTL INPUT 1N4148 +15V DISCUSSION ON DRIVING ADCs 2N2907 1k 1.8k 220 0.01F 0.1F Settling characteristics of op amps also include the ability of the amplifier to recover, that is, settle, from a transient current output load condition. An example of this includes an op amp driving the input from a SAR-type ADC. Although the comparison point of the converter is usually diode clamped, the input swing of plus-and-minus a diode drop still gives rise to a significant modulation of input current. If the closed-loop output impedance is low enough and bandwidth of the amplifier is sufficiently large, the output settles before the converter makes a comparison decision, which prevents linearity errors or missing codes. 10F + The actual overall settling time is affected by the noise gain of the amplifier, the applied compensation, and the equivalent input capacitance at the input of the amplifier. 0.47F * VREF 00296-050 t S TOTAL 8 3 The settling time of the combination of the current output DAC and the op amp can be approximated by 2 0.1F *DECOUPLE CLOSE TOGETHER ON GROUND PLANE WITH SHORT LEAD LENGTHS. Figure 50. Transient Output Impedance Test Fixture As seen in Figure 51, the OP249 has an extremely fast recovery of 247 ns (to 0.01%) for a 1 mA load transient. The performance makes it an ideal amplifier for data acquisition systems. Figure 50 shows a settling measurement circuit for evaluating recovery from an output current transient. An output disturbing current generator provides the transient change in output load current of 1 mA. 247.4ns 100 90 10 0% 2mV Rev. G | Page 16 of 20 2V 100ns OP249 0.005 (0.13) MIN 8 0.055 (1.40) MAX 5 0.310 (7.87) 0.220 (5.59) 1 4 0.100 (2.54) BSC 0.320 (8.13) 0.290 (7.37) 0.405 (10.29) MAX 0.060 (1.52) 0.015 (0.38) 0.200 (5.08) MAX 0.150 (3.81) MIN 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) SEATING PLANE 15 0 0.015 (0.38) 0.008 (0.20) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 54. 8-Lead Ceramic Dual In-Line Package [CERDIP] (Q-8) Dimensions shown in inches and (millimeters) ORDERING GUIDE Model 1 OP249AZ OP249FZ OP249GP OP249GPZ OP249GS OP249GS-REEL OP249GS-REEL7 OP249GSZ OP249GSZ-REEL OP249GSZ-REEL7 1 Temperature Range -55C to +125C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package Description 8-Lead CERDIP 8-Lead CERDIP 8-Lead PDIP 8-Lead PDIP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N Package Option Q-8 Q-8 N-8 N-8 R-8 R-8 R-8 R-8 R-8 R-8 Z = RoHS Compliant Part. For military processed devices, see the standard microcircuit drawings (SMD) available at www.dscc.dla.mil/programs/milspec/default.asp. Table 7. SMD Part Number 5962-9151901M2A 5962-9151901MPA Analog Devices, Inc. Equivalent OP249ARCMDA OP249AZMDA Rev. G | Page 18 of 20 OP249 NOTES Rev. G | Page 19 of 20 OP249 NOTES (c)1989-2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00296-0-4/10(G) Rev. G | Page 20 of 20