1. General description
The 74HC299; 74HCT299 are high-speed Si-gate CMOS devices which are
pin-compatible with Low-power Schottky TTL (LSTTL) devices. They are specified in
compliance with JEDEC standard no. 7A.
The 74HC299; 74HCT299 contain eight edge-triggered D-type flip-flops and the
interstage logic necessary to perform synchronous shift-right, shift-left, parallel load and
hold operations. An operation is determined by the mode select inputs S0 and S1, as
shown in Table 3.
Pins I/O0 to I/O7 are flip-flop 3-state buffer outputs which allow them to operate as data
inputs in parallel load mode. The serial outputs Q0 and Q7 are used for expansion in
serial shifting of longer words.
A LOW signal on the asynchronous master reset input MR overrides the Sn and clock CP
inputs and resets the flip-flops. All other state changes are initiated by the rising edge of
the clock pulse. Inputs can change when the clock is in either state, provided that the
recommended set-up and hold times are observed.
A HIGH signal on the 3-state output enable inputs OE1 or OE2 disables the 3-state
buffers and the I/On outputs are set to the high-impedance OFF-state. In this condition,
the shift, hold, load and reset operations still occur when preparing for a parallel load
operation. The 3-state buffers are also disabled by HIGH signals on both S0 and S1.
2. Features
nMultiplexed inputs/outputs provide improved bit density
nFour operating modes:
uShift left
uShift right
uHold (store)
uLoad data
nOperates with output enable or at high-impedance OFF-state (Z)
n3-state outputs drive bus lines directly
nCascadable for n-bit word lengths
nESD protection:
uHBM JESD22-A114E exceeds 2000 V
uMM JESD22-A115-A exceeds 200 V
nSpecified from −40 °C to +85 °C and from −40 °C to +125 °C
74HC299; 74HCT299
8-bit universal shift register; 3-state
Rev. 03 — 28 July 2008 Product data sheet
74HC_HCT299_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 28 July 2008 2 of 24
NXP Semiconductors 74HC299; 74HCT299
8-bit universal shift register; 3-state
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74HC299
74HC299D −40 °C to +125 °C SO20 plastic small outline package; 20 leads; body
width 7.5 mm SOT163-1
74HC299DB −40 °C to +125 °C SSOP20 plastic shrink small outline package; 20 leads;
body width 5.3 mm SOT339-1
74HC299N −40 °C to +125 °C DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1
74HC299PW −40 °C to +125 °C TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm SOT360-1
74HCT299
74HCT299D −40 °C to +125 °C SO20 plastic small outline package; 20 leads; body
width 7.5 mm SOT163-1
74HCT299DB −40 °C to +125 °C SSOP20 plastic shrink small outline package; 20 leads;
body width 5.3 mm SOT339-1
74HCT299N −40 °C to +125 °C DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1
74HCT299PW −40 °C to +125 °C TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm SOT360-1
Fig 1. Functional diagram
001aai460
INPUT/3-STATE OUTPUT CIRCUITRY
8-BIT SHIFT REGISTER
I/O0
CP
Q0
MR
2
8
9
3
12
11 DSR
7
I/O1
13
I/O2
6
I/O3
14
I/O4
515
I/O5
119
I/O6
4
I/O7
16
Q7
S0 S1 DSL
17
18
OE1
OE2
74HC_HCT299_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 28 July 2008 3 of 24
NXP Semiconductors 74HC299; 74HCT299
8-bit universal shift register; 3-state
Fig 2. Logic symbol Fig 3. IEC logic symbol
001aai458
MR
OE
2
9
3
16
4
17
8
15
5
14
6
13
7
18
11
19
1
I/O7
I/O6
Q7
Q0
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
CP
S0
S1
DSR
DSL
12
9
2
3
R SRG8
3EN5
0
1
19
1
C4/1 /2
M0
3
12
11 8
1, 4D
3, 4D
6, 5
18 2, 4D
7Z6
17
Z7
6
14
5
15
4
7, 5
001aai459
&
16
3, 4D
3, 4D
5
13
74HC_HCT299_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 28 July 2008 4 of 24
NXP Semiconductors 74HC299; 74HCT299
8-bit universal shift register; 3-state
Fig 4. Logic diagram
001aai461
DQ
CP
RD
FF0
DQ
CP
RD
FF1
DQ
CP
RD
FF2
DQ
CP
RD
FF3
DQ
CP
RD
FF4
DQ
CP
RD
FF5
DQ
CP
RD
FF6
DQ
CP
RD
FF7
DSR
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
S0
S1
CP
Q0
OE1
OE2
MR
DSL
Q7
74HC_HCT299_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 28 July 2008 5 of 24
NXP Semiconductors 74HC299; 74HCT299
8-bit universal shift register; 3-state
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 5. Pin configuration (SO20 and (T)SSOP20) Fig 6. Pin configuration (DIP20)
74HC299
74HCT299
S0 VCC
OE1 S1
OE2 DSL
I/O6 Q7
I/O4 I/O7
I/O2 I/O5
I/O0 I/O3
Q0 I/O1
MR CP
GND DSR
001aai511
1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19
74HC299
74HCT299
S0 VCC
OE1 S1
OE2 DSL
I/O6 Q7
I/O4 I/O7
I/O2 I/O5
I/O0 I/O3
Q0 I/O1
MR CP
GND DSR
001aai457
1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19
Table 2. Pin description
Symbol Pin Description
S0 1 mode select input
OE1 2 3-state output enable input (active LOW)
OE2 3 3-state output enable input (active LOW)
I/O6 4 parallel data input or 3-state parallel output (bus driver)
I/O4 5 parallel data input or 3-state parallel output (bus driver)
I/O2 6 parallel data input or 3-state parallel output (bus driver)
I/O0 7 parallel data input or 3-state parallel output (bus driver)
Q0 8 serial output (standard output)
MR 9 asynchronous master reset input (active LOW)
GND 10 ground (0 V)
DSR 11 serial data shift-right input
CP 12 clock input (LOW to HIGH, edge-triggered)
I/O1 13 parallel data input or 3-state parallel output (bus driver)
I/O3 14 parallel data input or 3-state parallel output (bus driver)
I/O5 15 parallel data input or 3-state parallel output (bus driver)
I/O7 16 parallel data input or 3-state parallel output (bus driver)
Q7 17 serial output (standard output)
74HC_HCT299_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 28 July 2008 6 of 24
NXP Semiconductors 74HC299; 74HCT299
8-bit universal shift register; 3-state
6. Functional description
[1] H = HIGH voltage level;
L = LOW voltage level;
↑= LOW to HIGH CP transition;
X = don’t care.
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DSL 18 serial data shift-left input
S1 19 mode select input
VCC 20 positive supply voltage
Table 2. Pin description
…continued
Symbol Pin Description
Table 3. Function table[1]
Input Response
MR S1 S0 CP
L X X X asynchronous reset; Q0 to Q7 = LOW
HHH↑parallel load; I/On → Qn
HLH↑shift right; DSR → Q0, Q0 → Q1, etc.
HHL↑shift left; DSL → Q7, Q7 → Q6, etc.
H L L X hold
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage −0.5 +7 V
IIK input clamping current VI < −0.5 V or VI>V
CC + 0.5 V [1] -±20 mA
IOK output clamping current VO<−0.5 V or VO>V
CC + 0.5 V [1] -±20 mA
IOoutput current −0.5 V < VO < VCC + 0.5 V
standard outputs - ±25 mA
bus driver outputs - ±35 mA
ICC supply current
standard outputs - 50 mA
bus driver outputs - 70 mA
IGND ground current
standard outputs −50 - mA
bus driver outputs −70 - mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation Tamb = −40 °C to +125 °C
DIP20 package [2] - 750 mW
SO20 package [3] - 500 mW
(T)SSOP20 package [4] - 500 mW
74HC_HCT299_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 28 July 2008 7 of 24
NXP Semiconductors 74HC299; 74HCT299
8-bit universal shift register; 3-state
[2] Ptot derates linearly at 12 mW/K above 70 °C.
[3] Ptot derates linearly at 8 mW/K above 70 °C.
[4] Ptot derates linearly at 5.5 mW/K above 60 °C.
8. Recommended operating conditions
9. Static characteristics
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 74HC299 74HCT299 Unit
Min Typ Max Min Typ Max
VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
VIinput voltage 0 - VCC 0- V
CC V
VOoutput voltage 0 - VCC 0- V
CC V
Tamb ambient temperature −40 - +125 −40 - +125 °C
∆t/∆V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V
VCC = 4.5 V - 1.67 139 - 1.67 1.39 ns/V
VCC = 6.0 V - - 83 - - - ns/V
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 °C−40 °C to
+85 °C−40 °C to
+125 °CUnit
Min Typ Max Min Max Min Max
74HC299
VIH HIGH-level
input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V
VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V
VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V
VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V
74HC_HCT299_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 28 July 2008 8 of 24
NXP Semiconductors 74HC299; 74HCT299
8-bit universal shift register; 3-state
VOH HIGH-level
output voltage VI = VIH or VIL
all outputs
IO = −20 µA; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO = −20 µA; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO = −20 µA; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V
standard outputs
IO = −4.0 mA;
VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V
IO = −5.2 mA;
VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V
bus driver outputs
IO = −6.0 mA;
VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V
IO = −7.8 mA;
VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage VI = VIH or VIL
all outputs
IO = 20 µA; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 µA; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO = 20 µA; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V
standard outputs
IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
bus driver outputs
IO = 6.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
IO = 7.8 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI = VCC or GND;
VCC = 6.0 V --±0.1 - ±1.0 - ±1.0 µA
IOZ OFF-state output
current VI=V
IH or VIL;V
O=V
CC or
GND; VCC = 6.0 V --±0.5 - ±5.0 - ±10.0 µA
ICC supply current VI=V
CC or GND; IO=0A;
VCC = 6.0 V - - 8.0 - 80 - 160 µA
CIinput capacitance - 3.5 - - - - - pF
CI/O input/output
capacitance -10-----pF
CPD power dissipation
capacitance per package [1] -120-----pF
74HCT299
VIH HIGH-level
input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V
Table 6. Static characteristics
…continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 °C−40 °C to
+85 °C−40 °C to
+125 °CUnit
Min Typ Max Min Max Min Max
74HC_HCT299_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 28 July 2008 9 of 24
NXP Semiconductors 74HC299; 74HCT299
8-bit universal shift register; 3-state
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD=C
PD ×VCC2×fi+∑(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
VIL LOW-level
input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V
VOH HIGH-level
output voltage VI = VIH or VIL; VCC = 4.5 V
all outputs
IO = −20 µA 4.4 4.5 - 4.4 - 4.4 - V
standard outputs
IO = −4.0 mA 3.98 4.32 - 3.84 - 3.7 - V
bus driver outputs
IO = −6.0 mA 3.98 4.32 - 3.84 - 3.7 - V
VOL LOW-level
output voltage VI = VIH or VIL; VCC = 4.5 V
all outputs
IO = 20 µA - 0 0.1 - 0.1 - 0.1 V
standard outputs
IO = 4.0 mA - 0.15 0.26 - 0.33 - 0.4 V
bus driver outputs
IO = 6.0 mA - 0.16 0.26 - 0.33 - 0.4 V
IIinput leakage
current VI = VCC or GND;
VCC = 5.5 V --±0.1 - ±1.0 - ±1.0 µA
IOZ OFF-state output
current VI=V
IH or VIL;V
O=V
CC or
GND per input pin; other
inputs at VCC or GND;
IO= 0 A; VCC = 5.5 V
--±0.5 - ±5.0 - ±10.0 µA
ICC supply current VI=V
CC or GND; IO=0A;
VCC = 5.5 V - - 8.0 - 80 - 160 µA
∆ICC additional supply
current per input pin;
VI=V
CC −2.1 V;
other inputs at VCC or
GND; IO=0A;
VCC = 4.5 V to 5.5 V
I/On, DSR, DSL, MR
and S1 - 25 90 - 112.5 - 122.5 µA
CP, S0 - 60 216 - 270 - 294 µA
OEn - 30 108 - 135 - 147 µA
CIinput capacitance - 3.5 - - - - - pF
CI/O input/output
capacitance -10-----pF
CPD power dissipation
capacitance per package [1] -125-----pF
Table 6. Static characteristics
…continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions 25 °C−40 °C to
+85 °C−40 °C to
+125 °CUnit
Min Typ Max Min Max Min Max
74HC_HCT299_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 28 July 2008 10 of 24
NXP Semiconductors 74HC299; 74HCT299
8-bit universal shift register; 3-state
∑(CL×VCC2×fo) = sum of outputs.
CL= output load capacitance in pF;
VCC = supply voltage in V;
VI= GND to VCC for 74HC299;
VI= GND to (VCC −1.5 V) for 74HCT299.
10. Dynamic characteristics
Table 7. Dynamic characteristics
GND (ground = 0 V); for test circuit, see Figure 11.
Symbol Parameter Conditions 25 °C−40 °C to
+85 °C−40 °C to
+125 °CUnit
Min Typ Max Min Max Min Max
74HC299
tpd propagation
delay CP to Q0, Q7; see Figure 7 [1]
VCC = 2.0 V - 66 200 - 250 - 300 ns
VCC = 4.5 V - 24 40 - 50 - 60 ns
VCC = 5.0 V; CL = 15 pF -20-----ns
VCC = 6.0 V - 19 34 - 43 - 51 ns
CP to I/On; see Figure 7
VCC = 2.0 V - 66 200 - 250 - 300 ns
VCC = 4.5 V - 24 40 - 50 - 60 ns
VCC = 5.0 V; CL = 15 pF -20-----ns
VCC = 6.0 V - 19 34 - 43 - 51 ns
MR to Q0, Q7 or I/On;
see Figure 8 [2]
VCC = 2.0 V - 66 200 - 250 - 300 ns
VCC = 4.5 V - 24 40 - 50 - 60 ns
VCC = 5.0 V; CL = 15 pF -20-----ns
VCC = 6.0 V - 19 34 - 43 - 51 ns
tttransition time bus driver (I/On); see Figure 7 [3]
VCC = 2.0 V - 14 60 - 75 - 90 ns
VCC = 4.5 V - 5 12 - 15 - 18 ns
VCC = 6.0 V - 4 10 - 13 - 15 ns
standard (Q0, Q7); see Figure 7
VCC = 2.0 V - 19 75 - 95 - 110 ns
VCC = 4.5 V - 7 15 - 19 - 22 ns
VCC = 6.0 V - 6 13 - 16 - 19 ns
74HC_HCT299_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 28 July 2008 11 of 24
NXP Semiconductors 74HC299; 74HCT299
8-bit universal shift register; 3-state
tWpulse width CP HIGH or LOW; see Figure 7
VCC = 2.0 V 80 17 - 100 - 120 - ns
VCC = 4.5 V 16 6 - 20 - 24 - ns
VCC = 6.0 V 14 5 - 17 - 20 - ns
MR LOW; see Figure 8
VCC = 2.0 V 80 19 - 100 - 120 - ns
VCC = 4.5 V 16 7 - 20 - 24 - ns
VCC = 6.0 V 14 6 - 17 - 20 - ns
tPZH OFF-state to
HIGH
propagation
delay
OEn to I/On; see Figure 10 [4]
VCC = 2.0 V - 50 155 - 195 - 235 ns
VCC = 4.5 V - 18 31 - 39 - 47 ns
VCC = 6.0 V - 14 26 - 33 - 40 ns
tPZL OFF-state to
LOW
propagation
delay
OEn to I/On; see Figure 10
VCC = 2.0 V - 41 130 - 165 - 195 ns
VCC = 4.5 V - 15 26 - 33 - 39 ns
VCC = 6.0 V - 12 22 - 28 - 33 ns
tPHZ HIGH to
OFF-state
propagation
delay
OEn to I/On; see Figure 10 [5]
VCC = 2.0 V - 66 185 - 230 - 280 ns
VCC = 4.5 V - 24 37 - 46 - 56 ns
VCC = 6.0 V - 19 31 - 39 - 48 ns
tPLZ LOW to
OFF-state
propagation
delay
OEn to I/On; see Figure 10
VCC = 2.0 V - 55 155 - 195 - 235 ns
VCC = 4.5 V - 20 31 - 39 - 47 ns
VCC = 6.0 V - 16 26 - 33 - 40 ns
trec recovery time MR to CP; see Figure 8
VCC = 2.0 V 5 −14-5-5-ns
VCC = 4.5 V 5 −5-5-5-ns
VCC = 6.0 V 5 −4-5-5-ns
Table 7. Dynamic characteristics
…continued
GND (ground = 0 V); for test circuit, see Figure 11.
Symbol Parameter Conditions 25 °C−40 °C to
+85 °C−40 °C to
+125 °CUnit
Min Typ Max Min Max Min Max
74HC_HCT299_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 28 July 2008 12 of 24
NXP Semiconductors 74HC299; 74HCT299
8-bit universal shift register; 3-state
tsu set-up time DSR, DSL to CP; see Figure 7
VCC = 2.0 V 100 33 - 125 - 150 - ns
VCC = 4.5 V 20 12 - 25 - 30 - ns
VCC = 6.0 V 17 10 - 21 - 26 - ns
S0, S1 to CP; see Figure 9
VCC = 2.0 V 100 33 - 125 - 150 - ns
VCC = 4.5 V 20 12 - 25 - 30 - ns
VCC = 6.0 V 17 10 - 21 - 26 - ns
I/On to CP; see Figure 7
VCC = 2.0 V 125 39 - 155 - 190 - ns
VCC = 4.5 V 25 14 - 31 - 38 - ns
VCC = 6.0 V 21 11 - 26 - 32 - ns
thhold time I/On, DSR, DSL to CP;
see Figure 7
VCC = 2.0 V 0 −14-0-0-ns
VCC = 4.5 V 0 −5-0-0-ns
VCC = 6.0 V 0 −4-0-0-ns
S0, S1 to CP; see Figure 9
VCC = 2.0 V 0 −28-0-0-ns
VCC = 4.5 V 0 −10-0-0-ns
VCC = 6.0 V 0 −8-0-0-ns
fmax maximum
frequency CP input; see Figure 7
VCC = 2.0 V 5.0 15 - 4.0 - 3.4 - MHz
VCC = 4.5 V 25 45 - 20 - 17 - MHz
VCC = 5.0 V; CL = 15 pF -50-----MHz
VCC = 6.0 V 29 54 - 24 - 20 - MHz
74HCT299
tpd propagation
delay CP to Q0, Q7; see Figure 7 [1]
VCC = 4.5 V - 22 37 - 46 - 56 ns
VCC = 5.0 V; CL = 15 pF -19-----ns
CP to I/On; see Figure 7
VCC = 4.5 V - 22 37 - 46 - 56 ns
VCC = 5.0 V; CL = 15 pF -19-----ns
MR to Q0, Q7 or I/On;
see Figure 8 [2]
VCC = 4.5 V - 27 46 - 58 - 69 ns
VCC = 5.0 V; CL = 15 pF -23-----ns
Table 7. Dynamic characteristics
…continued
GND (ground = 0 V); for test circuit, see Figure 11.
Symbol Parameter Conditions 25 °C−40 °C to
+85 °C−40 °C to
+125 °CUnit
Min Typ Max Min Max Min Max
74HC_HCT299_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 28 July 2008 13 of 24
NXP Semiconductors 74HC299; 74HCT299
8-bit universal shift register; 3-state
[1] tpd is the same as tPHL and tPLH.
[2] tpd is the same as tPHL.
[3] tt is the same as tTHL and tTLH.
[4] ten is the same as tPZH and tPZL.
[5] tdis is the same as tPHZ and tPLZ.
tttransition time bus driver (I/On); see Figure 7 [3]
VCC = 4.5 V - 5 12 - 15 - 18 ns
standard (Q0, Q7); see Figure 7
VCC = 4.5 V - 7 15 - 19 - 22 ns
tWpulse width clock HIGH or LOW; see Figure 7
VCC = 4.5 V 20 10 - 25 - 30 - ns
master reset LOW; see Figure 8
VCC = 4.5 V 20 11 - 25 - 30 - ns
ten enable time OEn to I/On; see Figure 10 [4]
VCC = 4.5 V - 19 30 - 38 - 45 ns
tPHZ HIGH to
OFF-state
propagation
delay
OEn to I/On; see Figure 10 [5]
VCC = 4.5 V - 24 37 - 46 - 56 ns
tPLZ LOW to
OFF-state
propagation
delay
OEn to I/On; see Figure 10
VCC = 4.5 V - 20 32 - 40 - 48 ns
trec recovery time MR to CP; see Figure 8
VCC = 4.5 V 10 2 - 9 - 11 - ns
tsu set-up time I/On, DSR, DSL to CP;
see Figure 7
VCC = 4.5 V 25 14 - 31 - 38 - ns
S0, S1 to CP; see Figure 9
VCC = 4.5 V 32 18 - 40 - 48 - ns
thhold time I/On, DSR, DSL to CP;
see Figure 7
VCC = 4.5 V 0 −11-0-0-ns
S0, S1 to CP; see Figure 9
VCC = 4.5 V 0 −17-0-0-ns
fmax maximum
frequency CP input; see Figure 7
VCC = 4.5 V 25 42 - 20 - 17 - MHz
VCC = 5.0 V; CL = 15 pF -46-----MHz
Table 7. Dynamic characteristics
…continued
GND (ground = 0 V); for test circuit, see Figure 11.
Symbol Parameter Conditions 25 °C−40 °C to
+85 °C−40 °C to
+125 °CUnit
Min Typ Max Min Max Min Max
74HC_HCT299_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 28 July 2008 14 of 24
NXP Semiconductors 74HC299; 74HCT299
8-bit universal shift register; 3-state
[6] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2× fi× N + Σ(CL× VCC2× fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
Σ(CL× VCC2× fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching.
11. Waveforms
The shaded areas indicate when the input is permitted to change for predictable output performance.
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Clock pulse to outputs I/On, Q0, Q7 propagation delays, the clock pulse width, the I/On, DSR and DSL to
clock pulse set-up and hold times, the output transition times and the maximum clock frequency
001aai462
th
tsu
th
tPHL
tTHL tTLH
tWtPLH
tsu
1/fmax
VM
VM
VM
CP input
VI
GND
VI
GND
VOH
VOL
I/On, DSR, DSL
inputs
I/On, Q0, Q7
outputs
74HC_HCT299_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 28 July 2008 15 of 24
NXP Semiconductors 74HC299; 74HCT299
8-bit universal shift register; 3-state
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8. The master reset pulse width (LOW), the master reset to outputs I/On, Q0, Q7 propagation delays and the
master reset to clock pulse removal time
001aai463
I/On, Q0, Q7
outputs
VM
tPHL
VM
MR input VM
GND
GND
VI
tWtrec
CP input
VOL
VI
VOH
Measurement points are given in Table 8.
Fig 9. Set-up and hold times from the mode control inputs S0, S1 to the clock pulse
001aai464
I/On, DSR, DSL, Sn
inputs
CP input
tsu th
VM
VI
GND
GND
VI
VM
tsu th
74HC_HCT299_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 28 July 2008 16 of 24
NXP Semiconductors 74HC299; 74HCT299
8-bit universal shift register; 3-state
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 10. 3-state enable and disable times for OEn inputs
tPLZ
trtf
tPHZ
outputs
disabled outputs
enabled
outputs
enabled
I/On output
LOW to OFF
OFF to LOW
I/On output
HIGH to OFF
OFF to HIGH
OEn input
VI
GND
VM
VM
10 %
10 %
90 %
90 % VM
tPZL
tPZH
001aai465
VOH
VOL
VOH
VOL
Table 8. Measurement points
Type Input Output
VIVMVM
74HC299 VCC 0.5VCC 0.5VCC
74HCT299 3 V 1.3 V 1.3 V
Test data is given in Table 9.
Definitions for test circuit:
DUT = Device Under Test.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch
Fig 11. Test circuit for measuring switching times
001aai466
DUT
VCC
VIVO
RT
RL = 1 kΩ
CL
50 pF
PULSE
GENERATOR DUT
VCC
S1 open
74HC_HCT299_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 28 July 2008 17 of 24
NXP Semiconductors 74HC299; 74HCT299
8-bit universal shift register; 3-state
Table 9. Test data
Type Input Load S1 position
VItr, tfCLRLtPHL, tPLH
74HC299 VCC 6 ns 15 pF, 50 pF 1 kΩopen
74HCT299 3 V 6 ns 15 pF, 50 pF 1 kΩopen
74HC_HCT299_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 28 July 2008 18 of 24
NXP Semiconductors 74HC299; 74HCT299
8-bit universal shift register; 3-state
12. Package outline
Fig 12. Package outline SOT163-1 (SO20)
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZ
ywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
2.65 0.3
0.1 2.45
2.25 0.49
0.36 0.32
0.23 13.0
12.6 7.6
7.4 1.27 10.65
10.00 1.1
1.0 0.9
0.4 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.1
0.4
SOT163-1
10
20
wM
bp
detail X
Z
e
11
1
D
y
0.25
075E04 MS-013
pin 1 index
0.1 0.012
0.004 0.096
0.089 0.019
0.014 0.013
0.009 0.51
0.49 0.30
0.29 0.05
1.4
0.055
0.419
0.394 0.043
0.039 0.035
0.016
0.01
0.25
0.01 0.004
0.043
0.016
0.01
0 5 10 mm
scale
X
θ
A
A1
A2
HE
Lp
Q
E
c
L
vMA
(A )
3
A
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
99-12-27
03-02-19
74HC_HCT299_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 28 July 2008 19 of 24
NXP Semiconductors 74HC299; 74HCT299
8-bit universal shift register; 3-state
Fig 13. Package outline SOT339-1 (SSOP20)
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQ(1)
Zywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.38
0.25 0.20
0.09 7.4
7.0 5.4
5.2 0.65 7.9
7.6 0.9
0.7 0.9
0.5 8
0
o
o
0.131.25 0.2 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
1.03
0.63
SOT339-1 MO-150 99-12-27
03-02-19
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
110
20 11
y
0.25
pin 1 index
0 2.5 5 mm
scale
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1
A
max.
2
74HC_HCT299_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 28 July 2008 20 of 24
NXP Semiconductors 74HC299; 74HCT299
8-bit universal shift register; 3-state
Fig 14. Package outline SOT146-1 (DIP20)
UNIT A
max. 1 2 b1cD E e M
H
L
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
SOT146-1 99-12-27
03-02-13
A
min. A
max. bZ
max.
w
ME
e1
1.73
1.30 0.53
0.38 0.36
0.23 26.92
26.54 6.40
6.22 3.60
3.05 0.2542.54 7.62 8.25
7.80 10.0
8.3 24.2 0.51 3.2
0.068
0.051 0.021
0.015 0.014
0.009 1.060
1.045 0.25
0.24 0.14
0.12 0.010.1 0.3 0.32
0.31 0.39
0.33 0.0780.17 0.02 0.13
SC-603MS-001
MH
c
(e )
1
ME
A
L
seating plane
A1
wM
b1
e
D
A2
Z
20
1
11
10
b
E
pin 1 index
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
(1)
(1) (1)
DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1
74HC_HCT299_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 28 July 2008 21 of 24
NXP Semiconductors 74HC299; 74HCT299
8-bit universal shift register; 3-state
Fig 15. Package outline SOT360-1 (TSSOP20)
UNIT A1A2A3bpcD
(1) E(2) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 6.6
6.4 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.5
0.2 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT360-1 MO-153 99-12-27
03-02-19
wM
bp
D
Z
e
0.25
110
20 11
pin 1 index
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
HE
E
c
vMA
X
A
y
0 2.5 5 mm
scale
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
A
max.
1.1
74HC_HCT299_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 28 July 2008 22 of 24
NXP Semiconductors 74HC299; 74HCT299
8-bit universal shift register; 3-state
13. Revision history
Table 10. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT299_3 20080728 Product data sheet - 74HC_HCT299_CNV_2
Modifications: •The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•Legal texts have been adapted to the new company name where appropriate.
•Section 3: Ordering information added
•Section 12: Package outline drawings added
•Section 9 “Static characteristics”: Family data added
•Section 11 “Waveforms”: Test circuit added
74HC_HCT299_CNV_2 19970828 Product specification - -
74HC_HCT299_3 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 03 — 28 July 2008 23 of 24
NXP Semiconductors 74HC299; 74HCT299
8-bit universal shift register; 3-state
14. Legal information
14.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
14.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
NXP Semiconductors 74HC299; 74HCT299
8-bit universal shift register; 3-state
© NXP B.V. 2008. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 28 July 2008
Document identifier: 74HC_HCT299_3
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
16. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 5
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
6 Functional description . . . . . . . . . . . . . . . . . . . 6
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
8 Recommended operating conditions. . . . . . . . 7
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
10 Dynamic characteristics . . . . . . . . . . . . . . . . . 10
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18
13 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 22
14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 23
14.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23
14.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
14.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 23
14.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 23
15 Contact information. . . . . . . . . . . . . . . . . . . . . 23
16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
