DD-42900 ARINC 429 Microprocessor Interface Device This Preliminary data sheet provides detailed functional capabilities for product currently in prototype production. These specifications are being provided to allow for electrical design, layout and operation. FEATURES DESCRIPTION DDC's DD-42900 provides a complete and flexible interface between a microprocessor and ARINC 429 data bus. The 42900 interfaces to a processor through a 128 x 32 bit static RAM as well as four 32 x 32 receive FIFO's and two 32 x 32 transmit FIFO's.The 42900 can be easily interfaced to 8- or 16-bit processors via a buffered shared RAM configuration. The 42900 supports four ARINC 429 Receive channels (Rx0, Rx1, Rx2 and Rx3) and each receive data independently.The recieve data rates (high or low speed) for channel Rx0 and Rx1 can be programmed independently from Rx2 and Rx3.The 42900 can decode and sort data based on the ARINC 429 Label and SDI bits via the Data Match Processor and store it in RAM and/or FIFO's via the Data Store Processor. The 42900 supports two ARINC 429 Transmit channels (Tx0 and Tx1) and * Four ARINC 429 Receive Channels can transmit data independently.The transmit data rate can be programmed independently as well.There are two 32 x 32 bit FIFO's for each of the transmitters for sending out data. * 128 x 32 Shared RAM Interface * Label and Destination Decoding and Sorting The device has the capability of programming three general purpose interrupts as well as generating an interrupt based on an error condition.The general purpose interrupts can be programmed to trigger other external hardware.They can either be LEVELtriggered or PULSE triggered. * Two ARINC 429 Transmit Channels * Two 32 x 32 Transmit FIFO's * Interfaces Easily to 8- or 16-Bit Microprocessors The features built into the DD-42900 enable the user to off-load the host processor and use that processing time to do other more important duties than polling the ARINC 429 Bus.The decoding and sorting of data allows the user to gather data much quicker that past designs. If the user requires a microprocessor in the avionics box, this device will enable a clean and quick design. * Built-in Fault Detection Circuitry 128 X 16 STATIC RAM DMT RAM CTRL ARINC 429 RECEIVE 0 WRAPAROUND ARINC 429 Rx LOGIC ARINC 429 RECEIVE 1 ARINC 429 WRAPAROUND Rx LOGIC ARINC 429 RECEIVE 2 WRAPAROUND ARINC 429 Rx LOGIC ARINC 429 RECEIVE 3 WRAPAROUND ARINC 429 Rx LOGIC Rx DATA DATA 128 X 32 STATIC RAM Rx RAM ADDR CTRL ADDR DMP DATA DATA MATCH PROCESSOR DATA DATA Rx0 FIFO 32 WORDS DATA STORE PROCESSOR ADDR ADDR DATA ADDR Rx2 FIFO 32 WORDS Rx3 FIFO 32 WORDS ADDR DATA ARINC 429 TRANSMIT 0 ARINC 429 TRANSMIT 1 2 2 ARINC 429 Tx LOGIC Tx FIFO 32 WORDS ARINC 429 Tx LOGIC Tx FIFO 32 WORDS DATA INTERRUPT CONTROLLER CPU INTERFACE 8 16 4 IRQ 12 DATA ADDR MICROPROCESSOR OR CPU FIGURE 1. DD-42900 BLOCK DIAGRAM (c) 1995 ILC Data Device Corporation Rx1 FIFO 32 WORDS CONTROL ARINC 429 RECEIVERS If and when all of the above conditions are satisfied then a Data Match has occurred and the data will be stored in a RAM location whose address equals the matching DMT entry minus 200 hex. The DD-42900 supports four ARINC 429 inputs, designated Receive channels 0 through 3 (Rx0, Rx1, Rx2 and Rx3). The architecture of each of the four receiver circuits is identical and each receive data independently. ARINC 429 data is directly received into the DD-42900 with no additional circuitry required. Input protection, IAW the ARINC 429 specification, is provided as well as the voltage level translation from +5 V Bipolar nonreturn to zero Data to conventional +5 V logic levels used internal to the DD-42900 device. Bit 11 of each DMT entry, when set, will cause the incoming ARINC 429 data to stored in the corresponding receive channel FIFO (as well as the Rx RAM) when the data match conditions are met. Bits 14 and 15 of each DMT entry provide the ability to cause one of three general purpose interrupts upon a data match condition. If set to "00" then no interrupt will occur upon a data match condition. (more information on interrupts is described later) Receive Data Rates can be programmed for channels 0 and 1 independently of channels 2 and 3 via bits 2 and 3 of Arinc Control Register 2. The receiver circuitry will successfully decode an incoming ARINC 429 data stream as long as the data rate is within 5% of the nominal rate as determined by the Hi Speed/Lo Speed Bit and the associated ARINC Clock input (ARINC CLK 0 or ARINC CLK 1). The two 1 MHz ARINC clock inputs may be tied to the 1 MHz receive clock output or may be connected to another clock source.The ARINC CLK input should nominally be 10 times (for High Speed Mode) or 80 times (for low speed mode) the desired ARINC Data Rate. ARINC CLK 0 is used by channels Rx0 and Rx1 while ARINC CLK 1 is used by channels Rx2 and Rx3. ARINC-429 TRANSMITTER(S) The DD-42900 supports two ARINC 429 transmitters. Each transmitter channel transmits data independently and are designated Tx0 and Tx1.The transmit output of the DD-42900 is a TTL encoded digital data stream which can be connected directly to DDC's DD-03182 ARINC 429 line driver. Transmit data rates can be programmed for channels 0 and 1 independently. The transmit data rate is determined by the Hi Speed/Lo Speed Bit for each of the Tx channels in Arinc Control Register 2 and the associated ARINC Clock input (ARINC CLK 0 or ARINC CLK 1). The two 1 MHz ARINC clock inputs may be tied to the 1 MHz clock output or may be connected to another clock source to achieve transmit data rates other than 100 kHz or 12.5 kHz.The transmit clock input should be 10 times (for High Speed Mode) or 80 times (for low speed mode) the desired ARINC transmit data rate. Filtering and Sorting Rx Data: The receiver circuitry converts the serial data stream to a 32 bit wide parallel data word. The 32 bit word is processed internally by a Data Match Processor (DMP). It compares the incoming data to a table of data initialized by the processor which determines what incoming data is to be saved, where it is going to be saved, and if any interrupts are to be generated. The table of data is stored in a 128 word x 16 bit Data Match Table (DMT) RAM. When a match between the received ARINC 429 data and the criteria stored in a DMT entry is found, the received data, the storage address and modes, and interrupt parameters are passed to the Data Store Processor (DSP). The storage address in the Receive RAM is the address of the first matching DMT entry minus 200 hex. Transmit FIFOs: Each transmitter channel is provided with an output FIFO which is 32 words deep by 32 bits wide. When writing data to the Tx FIFO the associated Disable Txn bit in Arinc Control Register 1 can be set to a logic zero until the FIFO is loaded with the desired data. Upon setting the Disable Txn low the transmit channel will send the 32 bit message words with appropriate interword gaps on the ARINC 429 output. A status bit indicating that the FIFO is empty is supplied for each transmitter in the Arinc Status Register. There are three requirements to matching incoming ARINC-429 data to each DMT entry. 1) System Address Label: Bits 0-7 of the DMT are compared to the System Address Label (SAL) of the incoming ARINC 429 data word. If the DMT SAL entry is zero then the SAL of the incoming data word is ignored (or considered a match). Wraparound testing can be performed from Tx0 to Rx0 and Rx1 and from Tx1 to Rx2 and Rx3. Wraparound testing is enabled by setting the appropriate bits in Arinc Control Register 2. The parity of the transmitted word can be altered to even parity (instead of the normally odd parity) by setting the associated Txn Parity bit in the Arinc Control Register 2 which is useful to verify proper operation of the parity check circuitry each of the receive circuits during wraparound test mode. 2) Source/Destination Bits: Bits 8 and 9 of each DMT entry are compared to the Source/Destination bits of the incoming ARINC-429 data word. If these bits match or if Bit 10 of the DMT entry is set to a one then the S/D bit comparison is considered a match. It is also possible through the DMP Control Register 1 to enable "All Call Mode" as defined in ARINC 429 specification. When enabled for a particular receive channel, the S/D bits will be considered a match when the incoming ARINC 429 data contains a 00 in its S/D bit pair. PROCESSOR INTERFACE The processor interface allows for the use of either a 8- or 16-bit data bus. Also Intel or Motorola control signal formats can be used. 3) Receive Channel Number: Bits 12 and 13 of each DMT entry are compared to the number of the channel which received the ARINC 429 data. 2 interrupt will remain until the associated IRQ Status Register is read thus clearing the associated bits in each interrupt register. INTERRUPT OPERATIONAL MODES The DD-42900 provides 4 interrupt outputs. Three of these interrupt outputs (IRQ1, IRQ2, and IRQ3) are general purpose programmable interrupts. The fourth interrupt is an Error interrupt output which is specifically used to provide indications of various error conditions and is nonmaskable. Each of the individual interrupt registers can be masked by setting their corresponding bit in IRQ Control Register 1. It should be noted that the masking function only prevents the associated IRQ pin from becoming active. When the mask bit is cleared an interrupt can occurr in LEVEL IRQ mode if one or more interrupt conditions occurred during the time when the mask was set. If the user needs to ensure the interrupt will not occur upon clearing the mask bit the CPU should be programmed to read the associated interrupt status register immediately prior to clearing the IRQ mask bit. ERROR INTERRUPT OPERATION When an error condition occurs the ERROR* output pin goes low to indicate the presence of an error. The error pin will go high again when the Error Status Register is clear. Each of these bits is cleared by either reading the Error Status Register or removing the error condition. Zero Wait Mode Operation: When Zero Wait Mode is enabled by grounding the ZERO WAIT pin the host microprocessor may read data from the DD-42900 shared memory resources (DMT and Rx RAM) without using the READY or DTACK signals to insert wait states into the microprocessor cycle. This is accomplished by an additional "dummy read" of the desired address.This dummy read causes the DD-42900 to fetch the data from the source and place it in a latch. The data can then be read from the latch (word by word or byte by byte) by reading the same addresses. Thus for a 32 bit read in 8 bit mode the microprocessor would perform a total of 5 read operations. The first read would be the dummy read, subsequent reads would transfer the data. GENERAL PURPOSE INTERRUPTS The three general purpose interrupt outputs can be used for multilevel interrupts or to trigger other external hardware on various conditions. Each condition can be mapped to any one of the three general purpose interrupts or disabled (by mapping to IRQ0 which does not exist). Each interrupt output can be programmed to be either a LEVEL interrupt or PULSE interrupt via IRQ Control Register 2. When programmed for pulse interrupt mode the associated interupt pin will go low for 1 S and return high again. When programmed for LEVEL interrupt mode the 0.520 [13.21] 0.200 0.025 [5.08] 0.100 [2.54] (TYP) 19 EQ SP @ 0.100 = 1.900 [2.54] = [48.26] (TOL NONCUM) (TYP) 2.050 0.025 [52.07] 0.018 [0.46] (TYP) 1 0.051 [1.30] (TYP) 0.037 0.022 [0.94] 0.150 0.025 [3.81] 0.605 [15.37] 1 0.011 [0.28] (TYP) LEAD CLUSTER TO BE CENTRALIZED ABOUT CASE CENTERLINE WITHIN +0.010 FIGURE 2A. DD-03282 DIP MECHANICAL OUTLINE 3 ORIENTATION MARK DENOTES PIN 1 D D1 A A1 D3 1 E 0.020/0.012 [0.51/0.31] (TYP) E3 E1 D2/E2 1 0.44/0.025 R [11.18/0.64] R 0.031/0.025 [0.79/0.02] e (TYP) 0.020/[0.51] MIN(TYP) MIN INCHES MAX MIN MM MAX 1 2 A A1 D1 D2 D3 E1 E1 E3 e D E 0.165 0.090 0.649 0.590 0.500 0.650 0.590 0.500 0.500 0.685 0.685 0.180 0.119 0.655 0.630 0.500 0.655 0.630 0.500 0.500 0.694 0.694 4.20 2.29 16.51 14.99 12.70 16.51 14.99 12.70 1.27 17.40 17.40 4.57 3.04 16.66 16.00 BSC 16.66 16.00 BSC BSC 17.65 17.65 LEAD CLUSTER TO BE CENTRALIZED ABOUT CASE CENTERLINE WITHIN 0.010 DIMENSIONS SHOWN ARE IN INCHES [MILLIMETERS] FIGURE 2B. DD-03282 PLCC MECHANICAL OUTLINE D D1 ORIENTATION MARK DENOTES PIN 1 1 34 44 33 1 E E1 e 1 (TYP) B 23 11 12 (TYP) 22 0.012 [0.3] R 0.016 [0.40] (TYP) MIN(TYP) A2 A L A1 A MIN MAX INCHES MIN MAX MM 0.093 2.35 A1 0.004 0.010 0.10 0.25 H 0.005 [0.13] R (TYP) (TYP) C MIN (TYP) A2 D D1 E 0.077 0.083 1.95 2.10 0.537 0.557 13.65 14.15 0.390 0.398 9.90 10.10 0.537 0.557 13.65 14.15 E1 L e 0.390 0.398 9.90 10.10 0.026 0.037 0.65 0.95 0.031 BSC 0.80 BSC B H C 0.012 0.018 0.30 0.45 0.077 REF 1.95 REF 0.005 0.009 0.13 0.23 1 LEAD CLUSTER TO BE CENTRALIZED ABOUT CASE CENTERLINE WITHIN [0.00039] 2 DIMENSIONS SHOWN ARE IN INCHES [MILLIMETERS] FIGURE 2C. DD-03282GP MECHANICAL OUTLINE 4 1.102 0.011 (27.99 0.1) 39 EQ. SP. @ 0.0256 = 0.998 (0.65 = 25.36) (TOL. NONCUM) 1 PIN NO. 1 INDEX SEE DETAIL "A" PIN NUMBERS FOR REF. ONLY 121 160 120 1 0.103 (2.61) 1.102 0.011 (27.99 0.27) 0.085 0.009 (2.159 0.23) 39 EQ. SP. @ 0.0256 = 0.998 (0.65 = 25.36) (TOL. NONCUM) 1 0.077(1.96) (TYP) 1.194 (30.3) (REF) 0.01 1.256 (31.9) (TYP) 0.031(0.79) (TYP) 0.012 +0.002 -0.001 0.0256 (.65) (TYP) 0.05) (0.3 +-0.03 40 0.025 x 45 (0.64 x 45) CHAMFER (4 PLCS) DETAIL "A" NTS (TYP) 81 41 80 0.008 0.040(1.01) (TYP) (0.18 0.003 0.08 ) (TYP) +0.002 0.006 -0.001 NOTES: LEAD CLUSTER TO BE CENTRALIZED ABOUT 1 CASE CENTERLINE WITHIN 0.010 (0.25). 2. DIMENSIONS IN INCHES (MILLIMETERS). +0.05 -0.03 ) (0.15 0.046(1.17) (REF) (TYP) FIGURE 3A. DD-42900 ASIC MECHANICAL OUTLINE (CERAMIC) 1.102 0.004 (27.99 0.1) 39 EQ. SP. @ 0.0256 = 0.998 (0.65 = 25.36) (TOL. NONCUM) 1 PIN NO. 1 INDEX PIN NUMBERS FOR REF. ONLY 121 160 SEE DETAIL "A" 120 1 +0.008 0.146 -0.000 (3.71) 0.133 (3.38) (REF) 1.102 0.004 (27.99 0.1) 39 EQ. SP. @ 0.0256 = 0.998 (0.65 = 25.36) (TOL. NONCUM) 1 +0.000 0.013 -0.003 (0.33) 0.077(1.96) (TYP) 0.01 1.256 (31.9) (TYP) 0.012 0.003 (0.3 0.08) (TYP) 0.0256 (.65) (TYP) 40 81 41 DETAIL "A" NTS 80 0.016 (0.41) (MIN) (TYP) 0.002 0.007 (0.18) (TYP) NOTES: LEAD CLUSTER TO BE CENTRALIZED ABOUT 1 CASE CENTERLINE WITHIN 0.010 (0.25). 2. DIMENSIONS IN INCHES (MILLIMETERS). 0.031(.79) (TYP) FIGURE 3B. DD-42900 ASIC MECHANICAL OUTLINE (PLASTIC) 5 1.800 0.550 .010 PIN NUMBERS FOR REF ONLY .010 7 EQ. SP. @ 0.100=0.700 (TOL NON CUM) 1 64 COMPONENT ENVELOPE 0.100 57 0.200(MAX) 0.040 .010 2.000 (TYP) 56 .010 SEE DETAIL "A" 0.020 (TYP) 2.400 .010 DETAIL "A" NTS .003 23 EQ. SP. @ 0.100 = 2.300 (TOL NON CUM) 1 0.070 (TYP) 0.34 (MIN) 0.080 (TYP) 0.100 (TYP) 24 25 32 0.020 R MAX (TYP) 0.015 (TYP) 0.010 .002 (TYP) 0.100 (REF) 33 FIGURE 4A. DD-42900 DIP MECHANICAL ASSEMBLY 1.800 .010 PIN NUMBERS FOR REF ONLY 7 EQ. SP. @ 0.100=0.700 (TOL NON CUM) 0.550 1 2.400 .010 COMPONENT ENVELOPE 0.200 (MAX) 0.185 64 57 .010 23 EQ. SP. @ 0.100 = 2.300 (TOL NON CUM) 0.100 (TYP) 0.080 (TYP) 0.040 (TYP) 0.075 (TYP) 33 LEAD CLUSTER TO BE CENTRALIZED ABOUT PWB CENTERLINE WITHIN .010 FIGURE 4B. DD-42900 FLAT PACK MECHANICAL ASSEMBLY 6 SEE DETAIL "A" 0.015 (TYP) 0.020 R MAX (TYP) 0.010 .002 (TYP) NOTES: 1 .010 DETAIL "A" NTS .003 1 32 0.040 2.170 (TYP) 0.020 (TYP) 24 25 .010 56 0.065 (TYP) 0.185 (REF) DD-42900 PINOUTS (DIP AND FLAT PIN NO. FUNCTION PIN NO. 1 POL SEL A1 33 2 POL SEL A0 34 3 INTEL / MOTO* 35 4 8/16* BIT 36 5 Tx0 A 37 6 Tx0 B 38 7 Tx1 A 39 8 Tx1 B 40 9 A0 41 10 A1 42 11 A2 43 12 A3 44 13 A4 45 14 A5 46 15 A6 47 16 A7 48 17 A8 49 18 A9 50 19 A10 51 20 CS0* 52 21 CS1* 53 22 CS2 54 23 GND 55 24 GND 56 25 ZERO WAIT MODE 57 26 READY 58 27 RD* (DS*) 59 28 WR* (RD/WR*) 60 29 DTACK* 61 30 ERROR* 62 31 MASTER RESET* 63 32 16 MHz CLOCK 64 PACK) FUNCTION D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 IRQ3* IRQ2* IRQ1* 1 MHz OUT ARINC CLK 1 ARINC CLK 0 +5 V +5 V Rx3 B Rx3 A Rx2 B Rx2 A Rx1 B Rx1 A Rx0 B Rx0 A ORDERING INFORMATION Full Assembly: Chip Set: DD-42900XY-300 DD-429X0XY-300 Burn-in 0 = No Burn-in 2 = Burn-in (Ceramic Only) Burn-in 0 = No Burn-in 2 = Burn-in (Ceramic Only) Temperature Range 3 = 0 - 70C 2 = -40 - +85C 1 = -55 - +125C (Ceramic Only) Temperature Range 3 = 0 - 70C 2 = -40 - +85C 1 = -55 - +125C (Ceramic Only) ASIC Package Type P = Plastic C = Ceramic Transceiver Package Type P = Plastic C = Ceramic Lead Type D = Dip F = Flat Pack Lead Type D = Dip (Ceramic Only) P = PLCC (Plastic Only) G = PQFP (Plastic Only) Chip Set 42910 = ASIC + one transceiver 42920 = ASIC + two transceivers Note: "ASIC" is a QFP package. 7 The information in this data sheet is believed to be accurate; however, no responsibility is assumed by ILC Data Device Corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. Specifications are subject to change without notice. 105 Wilbur Place, Bohemia, New York 11716-2482 For technical support: 1-800-DDC-1772, ext. 7402 or 7384 (outside N.Y.) 1-800-245-3413, ext. 7402 or 7384 (in Canada) Headquarters - Tel: (516) 567-5600, ext. 7402 or 7384, Fax: (516) 567-7358 West Coast - Tel: (714)895-9777, Fax: (714) 895-4988 Europe - Tel: 44 (1635) 40158, Fax: 44 (1635) 32264 Asia/Pacific - Tel: 81 (3) 3814-7688, Fax: 81 (3) 3814-7689 PRE-01-09/95-1M 8