Features
• Built using the advantages and compatibility
of CMOS and IXYS HDMOSTM processes
• Latch-Up Protected
• High Peak Output Current: Dual 15A Peak
• Wide Operating Range: 8V to 30V
• Rise And Fall Times of <3ns
• Minimum Pulse Width Of 6ns
• Ability to Disable Output under Faults
• High Capacitive Load
Drive Capability: 4nF in <5ns
• Matched Rise And Fall Times
• 32ns Input To Output Delay Time
• Low Output Impedance
• Low Supply Current
Applications
• Driving RF MOSFETs
• Class D or E Switching Amplifier Drivers
• Multi MHz Switch Mode Power Supplies (SMPS)
• Pulse Generators
• Acoustic Transducer Drivers
• Pulsed Laser Diode Drivers
• DC to DC Converters
• Pulse Transformer Driver
First Release
Copyright © IXYS CORPORATION 2001 Patent Pending
IXDD415SI
Dual 15 Ampere Low-Side Ultrafast MOSFET Driver
Figure 1 - Functional Diagram
INB (8)
IN A (7 )
ENA (6)
ENB (9)
OUTA (22, 23, 24)
OUTB (19, 20, 21)
200k
200k
GND (25, 26)
Vcc (11, 12) Vcc (13, 14)
Vcc (3, 4)
Vcc (1, 2)
GND (15, 16) GND (17, 18)
GND (27, 28)
General Description
The IXDD415 is a dual CMOS high speed high current gate
driver specifically designed to drive MOSFETs in Class D and E
HF RF applications, as well as other applications requiring
ultrafast rise and fall times or short minimum pulse widths.
Each output of the IXDD415 can source and sink 15A of peak
current while producing voltage rise and fall times of less than
3ns. The outputs of the IXDD415 may be paralleled, producing a
single output of up to 30A with comparable rise and fall times.
The input of the driver is compatible with TTL or CMOS and is
fully immune to latch up over the entire operating range.
Designed with small internal delays, cross conduction/current
shoot-through is virtually eliminated in the IXDD415. Its features
and wide safety margin in operating voltage and power make
the IXDD415 unmatched in performance and value.
The IXDD415 has two enable inputs, ENA and ENB. These
enable inputs can be used to independently disable either of the
outputs, OUTA or OUTB, for added flexibility. Additionally, the
IXDD415 incorporates a unique ability to disable the output
under fault conditions. When a logical low is forced into the
Enable inputs, both final output stage MOSFETs (NMOS and
PMOS) are turned off. As a result, the output of the IXDD415
enters a tristate mode and achieves a Soft Turn-Off of the
MOSFET when a short circuit is detected. This helps prevent
damage that could occur to the MOSFET if it were to be
switched off abruptly due to a dv/dt over-voltage transient.
The IXDD415 is available in a 28 pin SO package (IXDD415SI),
incorporating DEI's patented (1) RF layout techniques to minimize
stray lead inductances for optimum switching performance.
(1) DEI U.S. Patent #4,891,686
2
IXDD415SI
Parameter Value
Supply Voltage 30V
All Other Pins -0.3V to VCC + 0.3V
Powe r Dissipation
TAMBIENT ≤25 oC 1W
TCASE ≤25 oC 12W
Derating Factors (to Ambient)
28-Pin SOIC 0.1W/oC
Storage Temperature -65oC to 150oC
Soldering Lead Tempera ture
(10 seconds maximum) 300oC
Unless otherwise noted, TA = 25 oC, 4.5V ≤ VCC ≤ 25V .
All voltage measurements with respect to GND. IXDD415 configured as described in Test Conditions.
Electrical Characteristics
Absolute Maximum Ratings (Note 1) Operating Ratings
Parameter Value
Maximum Junction Temperature 150oC
Operating Temperature Range -40oC to 85oC
Thermal Impedance (Junction To Case)
28 Pin SOIC (SI) (θJC) 0.75oC/W
(1) Refer to Figures 2a and 2b
Specifications Subject To Change Without Notice
Symbol Parameter Test Conditions Min Typ Max Units
VIH H igh input voltage 3.5 V
VIL Low input voltage 0.8 V
VIN Input voltage range -5 VCC + 0.3 V
IIN Input current 0V ≤ V IN ≤ V CC
-10 10
µA
VOH High output voltage VCC - 0.025 V
VOL Low output voltage 0.025 V
ROH Output resistance
@ Ou tp u t Hig h IOUT = 10mA , VCC = 15V
0.8 1.2
Ω
ROL Output resistance
@ Ou tp u t L o w IOUT = 10mA, VCC = 15V 0.8 1.2 Ω
IPEAK Peak output current VCC = 15V, each output
15 A
IDC Continuous output
curren t 2 A
VEN Enable voltage range -0.3 Vcc + 0.3 V
VENH H igh En input voltage 2/3 Vcc V
VENL Low En input voltage 1/3 Vcc V
fMAX Maximum frequency CL=1.0nF V cc=15V, m ax CW frequency
limited by p ac k age p o we r d is sip a t io n 45 MHz
tR Rise time
(1) C
L=1nF Vcc=15V VOH= 2V to 12 V
CL=4nF Vcc=15V VOH= 2V to 12 V 2.5
4.5 ns
ns
tF Fall time
(1) C
L=1nF Vcc=15V VOH= 2V to 12 V
CL=4nF Vcc=15V VOH= 2V to 12 V 2.0
3.5 ns
ns
tONDLY On-time propagation
delay (1) CL=4nF V cc=15V 32 38 ns
tOFFDLY Off-time propagation
delay (1) CL=4nF V cc=15V 29 35 ns
PWmin Minimum pulse width FWHM CL=1nF
+3V to +3V C L=1nF 5.0
7.0 ns
ns
tENOL Enable to output lo w
delay tim e Vcc=15V 80 ns
tENOH Enable to output high
delay tim e Vcc=15V 170 ns
tDOLD D isable to output low
D isable dela y time Vcc=15V 30 ns
tDOHD D isable to output high
D isable dela y time Vcc=15V 30 ns
VCC Power supply voltage 8 15 30 V
ICC Power supply current VIN = 3.5V
VIN = 0 V
VIN = + VCC
1
0 3
10
10
mA
µA
µA
3
IXDD415SI
Pin Description
Note 1: Operating the device beyond parameters with listed “Absolute Maximum Ratings” may cause permanent
damage to the device. Typical values indicate conditions for which the device is intended to be functional, but do not
guarantee specific performance limits. The guaranteed specifications apply only for the test conditions listed.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD procedures
when handling and assembling this component.
PIN # SYM BOL FUNCTION DESCRIPTION
1-4
11-14 VCC Supply Voltage
Positive pow er-supply voltage input. This pin provides power
to the entire chip. The range for this voltage is from 8V to
30V.
7 IN A Input Input signal-T TL or C M O S com patible.
6 ENA Enable
The system enable pin. This pin, when driven low, disables
the chip, forcing high im pedance state to the output.
22-24 OUTA Output
Driver Output. For application purposes, this pin is
connected to the Gate of a MOSFET. In some applications,
a low-impedance series resistor may be required between
th is o u tp u t a n d th e MOS FET Ga te .
8 IN B Input Input signal-T TL or C M O S com patible.
9 ENB Enable
The system enable pin. This pin, when driven low, disables
the chip, forcing high im pedance state to the output.
19-21 OUTB Output
Driver Output. For application purposes, this pin is
connected to the Gate of a MOSFET. In some applications,
a low-impedance series resistor may be required between
th is o u tp u t a n d th e MOS FET Ga te .
5,10
15-18
25-28 GND Ground
The system ground pins. Internally connected to all circuitry,
these pins provide ground reference for the entire chip. All of
these pins should be connected to a low noise analog
ground plane for optimum performance.
Pin Configurations And Package Outline
Ordering Information
Part Number Package Type Temp. Range Grade
IXDD415SI 28-Pin SOIC -40°C to +85°C Industrial
NOTE: Bottom-side heat sinking metalization is connected to ground
4
IXDD415SI
Typical Performance Characteristics
V
IN
Figure 2a - Characteristics Test Diagram
R ise Tim e vs. Load Capacitance
VCC = 15V, VOH = 2V To 12V
Load C apacitance (pF)
1k 2k 3k 4k0
Rise Tim e (ns)
0
1
2
3
4
5
Fig. 3 Fall Tim e vs. Load C apacitance
VCC = 15V, VOH = 12V T o 2V
Load C apacitance (pF)
1k 2k 3k 4k0
Fall Tim e (ns)
0
1
2
3
4
5
Fig. 4
S upply C urrent vs. Frequency
Vcc=15V
Frequency (M Hz)
5 10152025
S upply C urrent (m A)
0
1000
2000
3000
4000
4 nF
2 nF
1 nF
CL = 0
Fig. 5 S upply C urrent vs. Load C apacitance
Vcc=15V
Load C apacitance (pF )
0k 1k 2k 3k 4k
S upply C urrent (m A)
0
1000
2000
3000
4000
1 M Hz
5 M Hz
10 M Hz
20 M Hz
15 M Hz
25 M Hz
Fig. 6
Figure 2b - Timing Diagram
INPUT
OUTPUT
5V
90%
2.5V
10%
0V
0V
Vcc
90%
10%
t
ONDLY
t
OFFDLY
t
R
t
F
PW
MIN
5
IXDD415SI
Propagation D elay vs. Supply Voltage
CL=4nF VIN=5V@100kHz
Supply Voltage (V)
8 1012141618
Propagation D elay (ns)
0
10
20
30
40
50
tONDLY
tOFFDLY
Fig. 7 Propagation D elay vs. Input Voltage
CL=4nF VCC=15V
Input Voltage (V)
24681012
Propagation D elay (ns)
0
10
20
30
40
50
tONDLY
tOFFDLY
Fig. 8
P ropagation D elay vs. Junction Temperature
CL=4nF, VCC=15V
Tem
p
erature
(
°C
)
-40-200 20406080100120
Time (ns)
10
15
20
25
30
35
40
45
50
tOFFDLY
tONDLY
Fig. 9
Figure 10 2.2ns Rise Time Figure 11 <6ns Minimum Pulse Width
Typical Output Waveforms
Unless otherwise noted, all waveforms are taken driving a 1nF load, 1MHz repetition frequency, VCC=15V, Case Temperature = 25°C
6
IXDD415SI
Figure 14 - High Frequency Gate Drive Circuit
Figure 12 500KHz CW Repetition Frequency Figure 13 50MHz Burst Repetition Frequency
7
IXDD415SI
APPLICATIONS INFORMATION
High Frequency Gate Drive Circuit
The circuit diagram in figure 14 is a circuit diagram for a
very high switching speed, high frequency gate driver
circuit using the IXDD415SI. This is the circuit used in
the EVDD415 Evaluation Board,and is capable of driving
a MOSFET at up to the maximum operating limits of the
IXDD415. The circuit's very high switching speed and
high frequency operation dictates the close attention to
several important issues with respect to circuit design.
The three key elements are circuit loop inductance, Vcc
bypassing and grounding.
Circuit Loop Inductance
Referring to Figure 14, the Vcc to Vcc ground current
path defines the loop which will generate the inductive
term. This loop must be kept as short as possible. The
output leads (pins 24, 23, 22, 21, 20, and 19) must be
no further than 0.375 inches (9.5mm) from the gate of
the MOSFET. Furthermore the output ground leads (pins
25, 26, 27 and 28 on one end of the IC and pins 15, 16,
17, and 18 on the other end of the IC) must provide a
balanced symmetric coplanar ground return for optimum
operation.
Vcc Bypassing
In order for the circuit to turn the MOSFET on properly,
the IXDD415 must be able to draw up to 15A of current
per output channel from the Vcc power supply in 2-6ns
(depending upon the input capacitance of the MOSFET
being driven). This means that there must be very low
impedance between the driver and the power supply.
The most common method of achieving this low
impedance is to bypass the power supply at the driver
with a capacitance value that is at least two orders of
magnitude larger than the load capacitance. Usually,
this is achieved by placing two or three different types of
bypassing capacitors, with complementary impedance
curves, very close to the driver itself. (These capacitors
should be carefully selected, low inductance, low
resistance, high-pulse current-service capacitors). Care
should be taken to keep the lengths of the leads
between these bypass capacitors and the IXDD415 to an
absolute minimum.
The bypassing should be comprised of several values of
chip capacitors symmetrically placed on ether side of
the IC. Recommended values are .01uF, .47uF chips
and at least two 4.7uF tantalums.
Grounding
In order for the design to turn the load off properly, the
IXDD415 must be able to drain this 15A of current into an
adequate grounding system. There are three paths for
returning current that need to be considered: Path #1 is
between the IXDD415 and its load. Path #2 is between the
IXDD415 and its power supply. Path #3 is between the
IXDD415 and whatever logic is driving it. All three of these
paths should be as low in resistance and inductance as
possible, and thus as short as practical.
Output Lead Inductance
Of equal importance to supply bypassing and grounding are
issues related to the output lead inductance. Every effort
should be made to keep the leads between the driver and
its load as short and wide as possible, and treated as
coplanar transmission lines.
In configurations where the optimum configuration of circuit
layout and bypassing cannot be used, a series resistance
of a few Ohms in the gate lead may be necessary to prevent
ringing.
Heat Sinking
For high power operation, the bottom side metalized heat
sink pad should be epoxied to the circuit board ground
plane, or attached to an appropriate heat sink, using
thermally conductive epoxy. The heat sink tab is connected
to ground.
Figure 15: IXDD415SI Bottom Side
Heat Sinking Metalization
8
IXDD415SI
IXYS Semiconductor GmbH
Edisonstrasse15 ; D-68623; Lampertheim
Tel: +49-6206-503-0; Fax: +49-6206-503627
e-mail: marcom@ixys.de
IXYS Corporation
3540 Bassett St; Santa Clara, CA 95054
Tel: 408-982-0700; Fax: 408-496-0670
e-mail: sales@ixys.net
www.ixys.com
Directed Energy, Inc.
An IXYS Company
2401 Research Blvd. Ste. 108, Ft. Collins, CO 80526
Tel: 970-493-1901; Fax: 970-493-1903
e-mail: deiinfo@directedenergy.com
www.directedenergy.com
The enable (EN) input to the IXDD415 is a high voltage
CMOS logic level input where the EN input threshold is ½ VCC,
and may not be compatible with 5V CMOS or TTL input levels.
The IXDD415 EN input was intentionally designed for
enhanced noise immunity with the high voltage CMOS logic
levels. In a typical gate driver application, VCC =15V and the
EN input threshold at 7.5V, a 5V CMOS logical high input
applied to this typical IXDD415 application’s EN input will be
misinterpreted as a logical low, and may cause undesirable
or unexpected results. The note below is for optional
adaptation of TTL or 5V CMOS levels.
The circuit in Figure 16 alleviates this potential logic level
misinterpretation by translating a TTL or 5V CMOS logic input
to high voltage CMOS logic levels needed by the IXDD415 EN
input. From the figure, VCC is the gate driver power supply,
typically set between 8V to 20V, and VDD is the logic power
supply, typically between 3.3V to 5.5V. Resistors R1 and R2
form a voltage divider network so that the Q1 base is posi-
tioned at the midpoint of the expected TTL logic transition
levels.
A TTL or 5V CMOS logic low, VTTLLOW=~<0.8V, input applied to
the Q1 emitter will drive it on. This causes the level translator
output, the Q1 collector output to settle to VCESATQ1 +
VTTLLOW=<~2V, which is sufficiently low to be correctly
interpreted as a high voltage CMOS logic low (<1/3VCC=5V for
VCC =15V given in the IXDD415 data sheet.)
A TTL high, VTTLHIGH=>~2.4V, or a 5V CMOS high,
V5VCMOSHIGH=~>3.5V, applied to the EN input of the circuit in
Figure 16 will cause Q1 to be biased off. This results in Q1
collector being pulled up by R3 to VCC=15V, and provides a
high voltage CMOS logic high output. The high voltage CMOS
logical EN output applied to the IXDD415 EN input will enable
it, allowing the gate driver to fully function as a 15 Ampere
output driver.
The total component cost of the circuit in Figure 16 is less
than $0.10 if purchased in quantities >1K pieces. It is
recommended that the physical placement of the level
translator circuit be placed close to the source of the TTL or
CMOS logic circuits to maximize noise rejection.
TTL to High Voltage CMOS Level Translation
10K R3
3.3K R2
Q1
2N3904
EN
Output
CC
(From Ga te Driver
Power Supply)
Inpu t)
TTL
CMOS
3.3K R1
V
DD
(From Lo gic
Power Supply)
or
Hi
g
h Volta
ge
(To IXDD415
EN Inpu t)
Figure 16 - TTL to High Voltage CMOS Level Translator
Doc #9200-0233 R2
