L6362A IO-Link communication transceiver device IC Datasheet - production data ESD IEC 61000-4-2 Surge EN60947-5-2 Miniaturized VFDFPN 12L (3x3x0.90 mm) package Applications Features Supply voltage from 7 V to 36 V 5 V and 3.3 V compatible I/Os 5 V or 3.3 V, 10 mA selectable linear regulator 0.3 A output current intervention threshold Fully protected Reverse polarity Overload with cut-off function Overtemperature Undervoltage and overvoltage GND and VCC open wire -40 to +125 C operating ambient temperature Selectable output stages: high-side, lowside, push-pull Suitable to drive L, C and R loads 30 F output load drive capability Switching capability of inductors up to 500 mJ Wake-up detection supported Fast demagnetization of inductive loads COM1, COM2 and COM3 mode supported Designed to meet: Burst IEC 61000-4-4 November 2017 Industrial sensors Factory automation Process control Description The L6362A is an IO-Link and SIO mode transceiver device compliant to PHY2 (3-wire connection) supporting COM1 (4.8 kbaud), COM2 (38.4 kbaud) and COM3 (230.4 kbaud) modes. The output stage can be configured as high-side, low-side or push-pull and it can drive resistive, capacitive and inductive loads. It can be connected to a sensor chip with the industrial 24 V environment. The industrial environment could be a PLC, an IO-Link master, a relay or a valve. The L6362A is protected against reverse polarity, among VCC, GND, OUTH, OUTL and I/Q pins. Furthermore, the IC is protected against output short-circuit, overvoltage and impulse voltage withstand (1 kV pulse amplitude,1.2/50 s pulse duration, 500 source impedance). Table 1: Device summary Order code Package Packing L6362ATR VFDFPN 12L (3x3x0.90 mm) Tape and reel DocID027660 Rev 10 This is information on a product in full production. 1/39 www.st.com Contents L6362A Contents 1 Block diagram.................................................................................. 6 2 Pin description ................................................................................ 7 2.1 IN1, IN2 ............................................................................................. 8 2.2 EN/DIAG ........................................................................................... 8 2.3 OUT I/Q ............................................................................................. 8 2.4 SEL ................................................................................................... 8 2.5 VDD .................................................................................................. 8 2.6 GND .................................................................................................. 8 2.7 OL ..................................................................................................... 9 2.8 VCC .................................................................................................. 9 2.9 OUTH ................................................................................................ 9 2.10 OUTL ................................................................................................ 9 2.11 I/Q ..................................................................................................... 9 3 Absolute maximum ratings........................................................... 10 4 Recommended operating conditions ........................................... 12 5 6 Electrical characteristics .............................................................. 13 Output logic ................................................................................... 18 7 Receiver logic ................................................................................ 19 8 Output stage operation ................................................................. 20 8.1 Set output stage .............................................................................. 20 8.2 Push-pull (PP) and IO-link operation ............................................... 20 8.3 High-side operation ......................................................................... 21 8.4 Low-side operation .......................................................................... 21 9 10 Active clamp .................................................................................. 23 Slow demagnetization ................................................................... 26 11 Protection and diagnostic............................................................. 28 2/39 11.1 Undervoltage lock-out ..................................................................... 28 11.2 Overtemperature ............................................................................. 28 11.3 Current limitation and cut-off ........................................................... 28 11.4 Dead time ........................................................................................ 29 11.5 EN/DIAG pin.................................................................................... 29 DocID027660 Rev 10 L6362A Contents 11.6 OL (overload) pin ............................................................................ 30 11.7 Reverse polarity protection.............................................................. 30 11.8 GND/VCC open wire protection ...................................................... 30 12 Typical application ........................................................................ 32 13 Package information ..................................................................... 34 14 13.1 VFDFPN 12L (3x3x0.90 mm) package information ......................... 34 13.2 VFDFPN 12L (3x3x0.90 mm) packing information .......................... 36 Revision history ............................................................................ 38 DocID027660 Rev 10 3/39 List of tables L6362A List of tables Table 1: Device summary ........................................................................................................................... 1 Table 2: Pin description .............................................................................................................................. 7 Table 3: Linear regulator voltage configuration .......................................................................................... 8 Table 4: Absolute maximum ratings ......................................................................................................... 10 Table 5: Thermal data ............................................................................................................................... 10 Table 6: Recommended operating conditions .......................................................................................... 12 Table 7: Supply ......................................................................................................................................... 13 Table 8: Output stage ............................................................................................................................... 13 Table 9: I/Q receiver ................................................................................................................................. 14 Table 10: Timing VCC = 24 V ................................................................................................................... 14 Table 11: Electrical characteristics, logic inputs (IN1, IN2, EN/DIAG and SEL)....................................... 15 Table 12: Protection and diagnostic ......................................................................................................... 15 Table 13: Linear voltage regulator ............................................................................................................ 16 Table 14: Output stage truth table ............................................................................................................ 18 Table 15: I/Q truth table ............................................................................................................................ 19 Table 16: Load connection identification by OUTI/Q ................................................................................ 19 Table 17: Configuration summary............................................................................................................. 20 Table 18: Configuration summary 2 .......................................................................................................... 20 Table 19: Diagnostic truth table ................................................................................................................ 28 Table 20: VFDFPN 12L (3x3x0.90 mm) package mechanical data ......................................................... 35 Table 21: Document revision history ........................................................................................................ 38 4/39 DocID027660 Rev 10 L6362A List of figures List of figures Figure 1: Block diagram .............................................................................................................................. 6 Figure 2: Pin connection (top through view) ............................................................................................... 7 Figure 3: IO-Link operation ....................................................................................................................... 21 Figure 4: High-side operation ................................................................................................................... 21 Figure 5: Low-side operation .................................................................................................................... 22 Figure 6: Active clamp equivalent principle schematic. HS configuration (load to GND) ......................... 23 Figure 7: Active clamp equivalent principle schematic. LS configuration (load to VCC) .......................... 23 Figure 8: Fast demagnetization operation example. HS configuration (load to GND) ............................. 24 Figure 9: Fast demagnetization operation example. LS configuration (load to VCC) .............................. 25 Figure 10: Slow demagnetization principle operation. (PP, load to GND) ................................................ 26 Figure 11: Slow demagnetization operation example. HS configuration (load to GND) .......................... 26 Figure 12: Slow demagnetization operation example. LS configuration (load to VCC) ........................... 27 Figure 13: Output current in overload condition ....................................................................................... 29 Figure 14: PP configuration, open wire external protections .................................................................... 30 Figure 15: IO-Link configuration, open wire external protections ............................................................. 31 Figure 16: Typical IO-Link sensor application 2 ....................................................................................... 32 Figure 17: Sensor application without microcontroller .............................................................................. 32 Figure 18: Inductive load driver ................................................................................................................ 33 Figure 19: VFDFPN 12L (3x3x0.90 mm) package outline ........................................................................ 34 Figure 20: VFDFPN 12L (3x3x0.90 mm) recommended footprint ............................................................ 36 Figure 21: VFDFPN 12L (3x3x0.90 mm) carrier tape outline ................................................................... 36 Figure 22: VFDFPN 12L (3x3x0.90 mm) reel outline ............................................................................... 37 DocID027660 Rev 10 5/39 Block diagram 1 L6362A Block diagram Figure 1: Block diagram 6/39 DocID027660 Rev 10 L6362A 2 Pin description Pin description Figure 2: Pin connection (top through view) Table 2: Pin description Number Name Function 1 VDD Linear regulator output voltage 2 IN1 Digital input Input 3 IN2 Digital input Input 4 EN/DIAG 5 OUTI/Q 6 OL 7 GND IC ground 8 SEL Linear regulator output voltage selection 9 OUTL Output enable/fault diagnostic I/Q channel logic output Overload (diagnostic) LS channel output I/Q receiver line Type Output Input/output open drain Output Output (open drain) Supply Input Output 10 I/Q 11 OUTH HS channel output Output Input 12 VCC IC supply voltage Supply 13 Exposed pad Not connected In order to guarantee all features and protections, the exposed pad cannot be electrically connected to any other net. To improve the thermal performance, it can be connected to a floating copper area. DocID027660 Rev 10 7/39 Pin description 2.1 L6362A IN1, IN2 These pins control the output stage on OUTH and OUTL pins, see Table 14: "Output stage truth table". When used in push-pull configuration (OUTH and OUTL wired together), the IC must be driven by the IN2 pin, to allow the dead time function to protect the output stage. The IN1 pin can be wired to GND or VDD depending on the desired polarity. In order to avoid IC overstress, in push-pull configuration, IN1 pin has to be hardwired to VDD or GND. IN1 could be also actively controlled, but must be switched only while EN/DIAG pin is at a low logic level. When used in high-side (OUTL left unconnected) or low-side (OUTH left unconnected) configurations, the IC should be driven by the IN1 pin, in order to avoid the unnecessary delay, which is introduced by the dead time function. The pin IN2 can be wired to GND or VDD depending on the desired polarity, or can be actively controlled (for example by a microcontroller). 2.2 EN/DIAG This pin controls the output stage on pins OUTH and OUTL. When EN/DIAG is at a low logic level (GND), the output stage is disabled. The EN/DIAG pin is also internally wired to an open drain transistor, used for diagnostic purposes and must be driven through a series resistor. The open drain transistor turns on in case of faults. EN/DIAG pin has an internal weak pull-down resistor. If the OUTH and OUTL pins are wired together the IC can be still used in HS or LS mode (with slow demagnetization) by applying a fixed high or low level voltage to IN1 pin, using the IN2 pin to set the polarity and the EN/DIAG pin to control the power stage. 2.3 OUT I/Q This pin reports the status of the receiver line (I/Q). It swings from GND to VDD and should generally be connected to a microcontroller input. OUT I/Q relation to I/Q is shown in Table 14: "Output stage truth table" . 2.4 SEL This pin cannot be left floating and it allows the linear regulator output voltage to be configured at 3.3 V or 5 V. Table 3: Linear regulator voltage configuration 2.5 SEL VDD supplied voltage GND 3.3 V VDD 5V VDD This is the output of the integrated linear voltage regulator and the supply voltage of the I/O interface. It can supply a small current (Iscr) to a microcontroller or external circuitry. The integrated liner regulator could supply the whole system, provided that the amount of required current is within IC limits, or the system can be supplied by an external regulator and the regulator integrated in the IC supplies the integrated logic only. 2.6 GND IC ground. 8/39 DocID027660 Rev 10 L6362A 2.7 Pin description OL This pin has an open drain structure and is active low. The open drain is active in case of overload (current limitation). It can be used by the host microcontroller to detect an IO-Link wake-up request event. 2.8 VCC IC supply voltage. 2.9 OUTH This pin is the output of the high-side power transistor. 2.10 OUTL This pin is the output of the low-side power transistor. 2.11 I/Q Input pin of the integrated receiver. The level of the signal on I/Q pin is transferred to the OUTI/Q pin, according to the receiver thresholds defined in Table 8: "Output stage", and truth table see Table 14: "Output stage truth table". In IO-Link mode, OUTH and OUTL outputs have to be connected to the load. I/Q pin has to be connected to the load as well, through a 22 k resistor. If it is not used, this pin can remain floating; it has to be connected to GND to improve EMC robustness. DocID027660 Rev 10 9/39 Absolute maximum ratings 3 L6362A Absolute maximum ratings Table 4: Absolute maximum ratings Symbol VCC VOUTH VOUTL Parameter Value Supply voltage (steady-state) -36 to +36 Supply voltage transient(1) Internally limited HS or LS output channel voltage (steady-state) HS or LS output channel voltage (transient) (1) Unit V -36 to +36 Internally limited V I/Q channel voltage (steady-state) -36 to +36 I/Q channel voltage (transient) (1) Internally limited IN voltage -0.3 to VDD+0.3 V VEN EN/DIAG voltage -0.3 to VDD+0.3 V VSEL SEL voltage -0.3 to VDD+0.3 V VOL OL voltage -0.3 to VDD+0.3 V Internally limited A A mA VI/Q VIN1, IN2 IOUTH,OUTL Output stage current (continuous) (1) ICC Supply current 2(2) IOUT_I/Q OUTI/Q current -10/+10 IOL OL -10/+10 IEN EN/DIAG current -10/+10 PD Power dissipation Internally limited TJ Junction temperature -40 to 150 Storage temperature range -55 to 150 TStor mA W C Notes: (1)During (2)Peak fast transients according to IEC61000-4-5 (1 kV, RC coupling R=500 , C=18 F). value during fast transient test only. Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltages are referred to GND. Table 5: Thermal data Symbol Rth(JC) Rth(JA) 10/39 Parameter Value Thermal resistance junction-case 2.5 Thermal resistance junction-ambient. (FR4, Cu thick. 35 m, 2 layers, the exposed pad is not soldered to total exposed area = 5 mm2) 200 Thermal resistance junction-ambient. (FR4, Cu thick. 35 m, 2 layers, the exposed pad is soldered to total exposed area = 5 mm2) 100 DocID027660 Rev 10 Unit C/W L6362A Absolute maximum ratings Symbol Parameter Thermal resistance junction-ambient. (FR4, Cu thick. 35 m, 2 layers, the exposed pad has to be soldered to total exposed area = 100 mm2 with vias) DocID027660 Rev 10 Value Unit 50 11/39 Recommended operating conditions 4 L6362A Recommended operating conditions Table 6: Recommended operating conditions Symbol Parameter Min. VCC Supply voltage 7 CVCC Capacity on VCC pin 1 CVDD Capacity on VDD pin 47 Typ. Max. Unit 36 V F 68 nF CVDD higher than recommend values is allowed but external protection nets on VDD could be necessary for high VCC slew rate (>15 V/s). 12/39 DocID027660 Rev 10 L6362A 5 Electrical characteristics Electrical characteristics (7 V < VCC < 36 V; -40 C < TJ < 125 C, unless otherwise specified) Table 7: Supply Symbol Parameter Test conditions Min. Typ. Max. Unit VUVON Undervoltage on threshold 5.5 6.5 V VUVOFF Undervoltage off threshold 5.1 5.9 V Undervoltage hysteresis 300 VUVH ICC Supply current mV VCC = 24 V, no-load on output stage and VDD, EN/DIAG=1 1.2 2.3 VCC = 36 V, no-load on output stage and VDD, EN/DIAG=1 1.4 2.5 mA VCC = 5 V, no-load on output stage and VDD, EN/DIAG=1 0.8 VCC = 24 V, no-load on output stage and VDD, EN/DIAG=0 SR Maximum slew rate of VCC increase from off condition to avoid current pulse on output stage (IOUT < 10 mA) 2 OUTH = GND or OUTL = VCC, EN=GND VCC = 36 V V/s 1.5 Table 8: Output stage Symbol Parameter Test conditions High-side onstate resistance IOUT = 0.1 A @ TJ = 25 C Low-side onresistance IOUT = 0.1 A @ TJ = 25 C RDS(on) VCC = 24 V; open load; EN/DIAG=0 VOLLS OUTL output voltage VCC = 24 V; open load; EN/DIAG = 0 Output leakage current HS Output leakage current (HS) IN1 = GND, IN2 = GND, EN = VDD and OUTH = GND Output leakage current LS Output leakage current (LS) IN1 = VDD, IN2 = GND, EN = VDD and OUTL = VCC Current from OUT pin in PP Output current (PP) EN = GND and OUT = VCC or OUT = GND DocID027660 Rev 10 Max. Unit 1 1.6 0.8 IOUT = 0.1 A @ TJ = 125 C OUTH output voltage IOPP Typ. IOUT = 0.1 A @ TJ = 125 C VOLHS IOlk Min. 1.4 3 VCC-3 V V 1 10 A 0.7 10 A 70 A 13/39 Electrical characteristics L6362A Table 9: I/Q receiver Symbol Parameter Test conditions VI/QTHLH I/Q upper voltage threshold VI/QTHHL I/Q lower voltage threshold 8 V < VCC < 18 V VCC 18 V Min. Typ. Max. Unit 69.4 %VCC 12.5 V 61.1 %VCC 11 V 61.1 11 11.75 8 V < VCC < 18 V 47.2 VCC 18 V 8.5 9.75 VCC 18 V 0.8 2 VQHY I/Q hysteresis voltage RI/Q Weak pull-down on I/Q pin 250 tdbq I/Q debounce time 30 V 50 550 k 110 ns Table 10: Timing VCC = 24 V Symbol Parameter DTHS-LS Dead time between HS switch-off and LS switch-on (push-pull configuration) DTLS-HS Dead time between LS switch-off and HS switchon (push-pull configuration) tpI/Q tpOUT 14/39 Test conditions Min. Max. Unit 110 IN2 commutations only LOADH = 120 between OUT and GND; LOADL = 120 between OUT and VCC ns 140 I/Q to OUTI/Q propagation delay time INx (or EN/DIAG) to OUTH or OUTL propagation delay time Typ. 200 EN/DIAG = VDD, IN1 commutations in HS or LS configurations only. R-L load (120 , 10 H) to GND in HS; to VCC in LS 370 ns EN/DIAG=VDD, IN2 commutations in PP configuration only. R-L load (120 , 10 H) to GND for high, low transitions of the output; to VCC for low, high transitions 270 ns EN/DIAG commutations in HS or LS configurations only. R-L load (120 , 10 H) to GND in HS; to VCC in LS 400 ns tr(ON) OUTX and I/Q rise time (from VCC 10% to VCC 80%) in push-pull and HS configuration (high-side switch turn-on) IOUT = 0.2 A, R-L load (L = 10 H) to GND. I = 0.2 A flowing from the IC to the load. EN/DIAG, IN1 or IN2 commutations 380 860 ns tf(ON) OUTX and I/Q fall time (from VCC 90% to VCC 10%) in push-pull and LS configuration (low-side switch turn-on) IOUT = 0.2 A, R-L load (L = 10 H) to VCC. I = 0.2 A flowing from the load to the IC. EN/DIAG, IN1 or IN2 commutations 380 860 ns DocID027660 Rev 10 L6362A Electrical characteristics Symbol tr(OFF) tf(OFF) Parameter OUTX and I/Q rise time (from VCC 10% to VCC 80%) in push-pull and LS configuration (low-side switch turn-off) OUTX and I/Q fall time (from VCC 90% to VCC 10%) in push-pull and HS configuration (high-side switch turn-off) Test conditions Min. IOUT = 0.2 A, R-L load (L = 10 H) to VCC. I = 0.2 A flowing from the load to the OUTL (OUTH floating). EN/DIAG or IN1 commutations 380 Typ. IOUT = 0.2 A, R-L load (L = 10 H) to VCC. I = 0.2 A flowing from the load to the OUT (OUTL=OUTH). IN2 commutations IOUT = 0.2 A, R-L load (L = 10 H) to GND. I = 0.2 A flowing from OUTH to the load (OUTL floating). EN/DIAG, or IN1 commutations 380 IOUT = 0.2 A, R-L load (L = 10 H) to GND. I = 0.2 A flowing from OUT to the load (OUTH =OUTL). IN2 commutations Max. Unit 860 ns 180 ns 860 ns 180 ns Table 11: Electrical characteristics, logic inputs (IN1, IN2, EN/DIAG and SEL) Symbol Parameter Test conditions Min. Typ. Max. Unit VIL Input low level voltage (INx, EN/DIAG) VIH Input high level voltage (INx, EN/DIAG) 0.7xVDD V VIHY Input level voltage hysteresis (INx, EN/DIAG) 0.08xVDD V IIN Input current at IN1, IN2, SEL pins VIN = 5 V 2 IEN Input current on EN/DIAG pin VEN = 5 V, internal open drain not active 15 A VEN Voltage drop on EN/DIAG pin IEN = 5 mA 0.15 V 0.3xVDD V Table 12: Protection and diagnostic Symbol Vclamp Vdemag IOLS Parameter Test conditions VCC active clamp Min. Typ. Max. Iclamp = 10 mA 38 39 40 Iclamp = 2 A (peak value during fast transient only) 40 41 42 38 39 40 Demagnetization voltage Low-side switch load current limitation level in overload and cut-off DocID027660 Rev 10 -220 -310 Unit V mA 15/39 Electrical characteristics Symbol L6362A Parameter Test conditions Min. Typ. Max. Unit IOLS-PEAK Low-side switch intervention threshold for current limitation and cut-off -300 -450 mA IOHS High-side switch load current limitation level in overload and cut-off 220 310 mA High-side switch intervention threshold for current limitation and cut-off 300 450 mA tdOUT Low and high-side cutoff current delay time 3.6 6.4 ms trOUT Output stage restart delay time after cut-off or thermal protection intervention 55 105 ms IOHSPEAK tOL Overload delay time OUTH = GND or OUTL = VCC. Turn on the outputs and measure the delay between limitation event and signalization on OL pin. OL pulled to VDD with R = 3.3 k, without any capacitor connected versus GND VOL Voltage drop on OL pin IOL = 1 mA OUTL short to VCC or OUTH short to GND IOL OL pin leakage current IGD s 2.5 0.1 V VOL = 5 V internal open drain not active 1 A Ground rail disconnection output current (HS mode) OUTH short-circuit to ground rail 500 A IVD VCC rail disconnection output current (LS mode) OUTL short-circuit to VCC rail 500 A TJSD Junction temperature shutdown 150 170 TJR Junction temperature restart 125 145 C TJHYST Junction temperature thermal hysteresis Unit 25 Table 13: Linear voltage regulator Symbol VDD5 VDD3.3 Iscr 16/39 Parameter Test conditions Min. Typ. Max. Regulated output voltage VCC from 7 V to 36 V, no-load on VDD 4.5 5 5.5 3.0 3.3 3.6 Short-circuit current limitation SEL = GND 12 20 SEL = VDD 10 20 DocID027660 Rev 10 V mA L6362A Electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit VLR Line regulation VCC = 8 to 36 V, TJ = 25 C, Io = 2 mA 8 mV VLDR Load regulation Io = 2 to 7 mA, TJ = 25 C 20 mV DocID027660 Rev 10 17/39 Output logic 6 L6362A Output logic Table 14: Output stage truth table Operation EN/DIAG IN1 IN2 HS configuration (OUTL not connected) LS configuration (OUTH not connected) PP (OUTH wired with OUTL) Normal 1 0 0 Off (active clamp)(1) On (GND) GND Normal 1 0 1 On (VCC) Off VCC Normal 1 1 0 On (VCC) Off VCC Normal 1 1 1 Off (active clamp) On (GND) GND Normal 0 X X Off Off High Z (slow demagnetization)(2) During DT(3) 1 X X Cut-off (4) X X Off (active clamp) Off (active clamp) High Z UVLO(5) 0 X X Off (active clamp) Off (active clamp) High Z Overtemperature 0 X X Off (active clamp) Off (active clamp) High Z High Z Notes: (1)Active (2)See clamp (fast demagnetization) is active in case of residual currents on OUTH or OUTL. slow demagnetization section. (3)Dead time is inserted between each HS switch-off and LS switch-on, and vice versa, only if the IC is driven by the IN2 pin. No dead time is inserted when the IN1 pin is commutated. (4)EN/DIAG pin is driven "high" through a resistor, but the internal open drain is active and the pin is pulled to GND. (5)When 18/39 VCC < 2.5 V (typ.), the device is completely turned off. DocID027660 Rev 10 L6362A 7 Receiver logic Receiver logic The level of the signal on I/Q pin is transferred to the OUT I/Q pin, according to the receiver thresholds defined in and truth table below. The receiver is always active independently on the EN/DIAG pin status. The IN1 pin sets the phase relation between I/Q and OUT I/Q. Table 15: I/Q truth table EN/DIAG IN2 IN1 I/Q OUTI/Q X X 0 0 0 X X 0 1 1 X X 1 0 1 X X 1 1 0 UVLO X X X 0 Overtemperature X X X IN1 XOR I/Q(1) Notes: (1)The receiver keeps working in overtemperature conditions. Thanks to the internal pull-up and pull-down resistors on OUTH, OUTL and I/Q pins, the receiver logic can be used for the automatic identification of the load connection (high-side or low-side) even in the 3-wire configurations. Referring to the table above, the microcontroller (C) can force the EN/DIAG = GND and read the information from OUT I/Q: considering the voltage thresholds VI/QTHLH and VI/QTHHL, C can know whether the load is connected in high-side or low-side. The table below summarize the OUT I/Q logic level according to the load connection and IN1 set-up. Table 16: Load connection identification by OUTI/Q OUTI/Q EN/DIAG IN2 IN1 PP-HS PP-LS X 0 0 1 X 1 1 0 GND DocID027660 Rev 10 19/39 Output stage operation L6362A 8 Output stage operation 8.1 Set output stage The IC can be operated in high-side, low-side and push-pull mode, according to the electrical connections on OUTH and OUTL pins. Depending on the chosen operation mode, the IC must be driven by the IN1, IN2 or EN/DIAG pins. Table below refers to normal operation mode. For example, in push-pull mode the driving signal (high = VDD, low = GND) could be applied to IN2 or EN/DIAG only, while IN1 is connected to VDD or GND. In high-side and low-side modes only, the driving signal can be applied to IN1. Table 17: Configuration summary Configuration IN1 EN/DIAG IN2 GND OUT High H Low L VDD VDD Drive signal X High L Low H X GND High impedance Push-pull GND GND GND L VDD H High VDD GND VDD VDD X Drive signal H L X Low High impedance Table 18: Configuration summary 2 Configuration IN1 IN2 EN/DIAG OUTL High OUTH H GND Low High-side Drive signal High L Drive signal or wire to GND or VDD VDD NC L VDD Low H X X GND High L H GND Low Low-side Drive signal High L Drive signal or wire to GND or VDD VDD L Low X 8.2 NC VDD H X GND H Push-pull (PP) and IO-link operation The IC can be operated in push-pull mode, with slow demagnetization, by wiring OUTH and OUTL together. When OUTH and OUTL are wired together, IC must be driven by the IN2 pin, to allow the dead time function to properly protect the output stage. IN1 pin sets 20/39 DocID027660 Rev 10 L6362A Output stage operation the phase relation between IN2 and the output stage (OUTH, OUTL). The IO-Link operation is active when I/Q pin is connected to OUTH and OUTL by a resistor. According to the required protections and EMC levels, it could be necessary to protect the I/Q pin by an RC net, see the figure below, Section 11.3: "Current limitation and cut-off" and Table 14: "Output stage truth table". Figure 3: IO-Link operation 8.3 High-side operation The IC can be operated in high-side mode, with active clamping, by leaving the OUTL pin unconnected. IC should be driven by the IN1 pin and IN2 pin sets the phase relation between IN1 and OUTH. See Table 14: "Output stage truth table". Figure 4: High-side operation enables /disables the output stage sets 3V3 / 5 V and provides fault feedbacks IN1 should be used output voltage in HS or LS SEL Mic ro controller VCC Linear regulator VDD 1 F Undervoltage lock-out GND IN1 GPIOs IRQ GPIOs UART or GPIO Output stage (transmitter) EN / DIAG IN2 Logic interface OUTI/Q OUTH - Current limit. - Cut-off - Over temp. - Active clamp n.c. OUTL VDD OL IRQ Overload detection to the load HS operation: OUTH is used as output OUTL is unconnected I/Q Receiver L6362A IN2 can be also wired to GND to change polarity 8.4 GIPG020320151030LM Low-side operation The IC can be operated in low-side mode, with active clamping, by leaving the OUTH pin unconnected. IC should be driven by the IN1 pin and IN2 pin sets the phase relation between IN1 and OUTL. See Table 14: "Output stage truth table". DocID027660 Rev 10 21/39 Output stage operation L6362A Figure 5: Low-side operation enables / disables the output stage sets 3V3 / 5 V and provides faults feedbacks IN1 should be used output voltage in HS or LS SEL VCC Linear regulator Microcontroller VDD 1 F Undervoltage lock-out GND IN1 GPIOs IRQ GPIOs UART or GPIO IRQ Output stage (Transmitter) EN / DIAG IN2 Logic interface OUT I/Q OUTHn.c. - Current limit. - Cut-off - Overtemp. - Active clamp to the load OUTL VDD OL Overload detection LS operation: OUTL is used as output OUTH is unconnected I/Q Receiver L6362A IN2 can be also wired to GND to change polarity 22/39 DocID027660 Rev 10 GIPG020320151044LM L6362A 9 Active clamp Active clamp Active clamping is always used in HS and LS configurations. In PP configuration slow demagnetization is used. Active clamp is also known as fast demagnetization of inductive loads or fast current decay. When a high-side driver turns off an inductance, a reversed polarity voltage appears across the load. The OUTH pin is pulled to a voltage below the ground until it reaches the demagnetization voltage, V CC-Vdemag. The conduction state is linearly modulated by an internal circuitry in order to keep the OUTH pin voltage at about VCC -Vdemag until the energy in the load has been dissipated. The energy is dissipated both in IC internal switch and load resistance. Similarly, in case of load connected between the LS pin and VCC, at the switch-off (of the low-side switch) the output is pushed to +Vdemag. See Table 14: "Output stage truth table" for the detailed behavior of the power stage in different configurations and conditions. Figure 6: Active clamp equivalent principle schematic. HS configuration (load to GND) VCC GND V DEMAG Indu ctive load OUTH OUTL n.c. L6362A GIPG020320151227LM Figure 7: Active clamp equivalent principle schematic. LS configuration (load to VCC) L6362A VCC GND OUTH n.c. OUTL Inductive load V DEMAG GIPG020320151050LM DocID027660 Rev 10 23/39 Active clamp L6362A Figure 8: Fast demagnetization operation example. HS configuration (load to GND) 24/39 DocID027660 Rev 10 L6362A Active clamp Figure 9: Fast demagnetization operation example. LS configuration (load to VCC) DocID027660 Rev 10 25/39 Slow demagnetization 10 L6362A Slow demagnetization Slow demagnetization is also known as synchronous rectification or slow current decay and it is active in push pull mode. When a high-side driver turns off an inductance, a reversed polarity voltage appears across the load. In push-pull configuration the low-side switch is ON and the OUTH pin is pulled at a voltage slightly (depending on the low-side switch drop) below the ground. The energy is dissipated in both IC internal switch and load resistance. Similarly, in case of load connected between the OUTL pin and VCC, at the switch-off of the low-side switch, the HS switch is ON and the output is pushed to a voltage slightly higher than VCC. Slow demagnetization is always active in PP configurations: the diodes of the integrated switches activate the slow demagnetization even when the IC is driven by EN/DIAG instead of IN2. See Table 14: "Output stage truth table" for the detailed behavior of the power stage in different configurations and conditions. Figure 10: Slow demagnetization principle operation. (PP, load to GND) Figure 11: Slow demagnetization operation example. HS configuration (load to GND) 26/39 DocID027660 Rev 10 L6362A Slow demagnetization Figure 12: Slow demagnetization operation example. LS configuration (load to VCC) DocID027660 Rev 10 27/39 Protection and diagnostic 11 L6362A Protection and diagnostic The IC integrates several protections to ease the design of a robust application. Protection functions are intended to avoid IC damage in fault conditions and are not intended for continuous operation. Continuous and repetitive operations of protection functions may reduce the IC lifetime. Table 19: Diagnostic truth table HS configuration (OUTL not connected) LS configuration (OUTH not connected) PP (OUTH wired to OUTL) Operation DIAG OL During DT 1 1 Cut-off 0 1 Off (active clamp)(1) Off (active clamp) High Z slow demagnetization Current limitation 1 0 Linearly controlled Linearly controlled Linearly controlled UVLO(2) 0 Not controlled Off (active clamp) Off (active clamp) High Z active clamp Overtemperature 0 1 Off (active clamp) Off (active clamp) High Z slow demagnetization High Z slow demagnetization Notes: (1)Active clamp (fast demagnetization) is active in case of residual currents on OUTH or OUTL. If OUTH and OUTL are wired together, slow demagnetization is used only in case of overtemperature protection intervention. (2)When 11.1 VCC < 2.5 V (typ.), the device is completely turned off. Undervoltage lock-out The output stage, the receiver and several internal circuitries turn off as the supply voltage falls below the turn-off threshold (VUVOFF). Normal operation restarts, after VCC exceeds the turn-on threshold (VUVON). Turn-on and turn-off thresholds are defined in table Table 7: "Supply". 11.2 Overtemperature The output stage turns off as the internal IC temperature (T J) exceeds the shutdown temperature see Table 11: "Electrical characteristics, logic inputs (IN1, IN2, EN/DIAG and SEL) ". Normal operation restarts when the TJ goes back below the restart temperature (T jr) and, in case the cut-off protection is triggered too, after the trout delay time expires. 11.3 Current limitation and cut-off The output current of the power stage is internally limited, see Table 12: "Protection and diagnostic". The current limitation circuit is active when the output current triggers peak threshold (I OHSPEAK for high-side, IOLS-PEAK for low-side) by limiting the output current to IOHS (or IOLS for lowside). The current limitation persists until the current required by the load becomes lower than the limitation level (IOHS or IOLS). 28/39 DocID027660 Rev 10 L6362A Protection and diagnostic If the output stage remains in a current limitation condition for a time longer than the tdOUT delay, the cut-off occurs, therefore the output stage turns off and restarts after the trOUT restart time. Please notice that the power dissipated by the IC can be significantly high in current limitation condition. Figure 13: Output current in overload condition 11.4 Dead time Dead time protection is also known as cross-conduction or shoot-through protection. When used in push-pull configuration, OUTH and OUTL pins are wired together. A dead time is necessary between each high-side switch (HS) turn-off and low-side switch (LS) turn-on, and vice versa, in order to avoid cross-conduction of the two switches. The IC integrates a dead time generator to properly drive the output stage avoiding cross-conduction. The dead time is inserted only when the IN2 pin changes its state. The dead time is not inserted when IN1 or EN/DIAG pin changes its state. The IC must be driven by the IN2 pin in case of push-pull configuration (OUTH and OUTL wired together). The IC should be driven by IN1 in case of HS (OUTL left unconnected) or LS (OUTH left unconnected) configurations, in order to avoid unnecessary delays when the output switch turns on. In any case, the EN/DIAG pin can be also driven by an external source (for example a microcontroller). 11.5 EN/DIAG pin The EN/DIAG pin is internally wired to a diagnostic open drain transistor, so it must be driven by a series resistor only. The open drain transistor is active (turn-on) while any of the following fault conditions is present, independently on the INx pin state: Undervoltage lock-out (2.5 V < VCC < VUVOFF) Overtemperature detected (TJ is above the threshold specified in Table 12: "Protection and diagnostic" The output turns off due to the cut-off protection Please note that in case of faults, the output stage (OUTH and OUTL) is disabled by an internal path, independently on the status of the EN/DIAG pin. Besides, note that the diagnostic signal is not visible if the EN/DIAG pin is pulled low from the microcontroller. DocID027660 Rev 10 29/39 Protection and diagnostic 11.6 L6362A OL (overload) pin The integrated open drain transistor is active (turn-on) in case of overload conditions. Overload is detected when the output current exceeds the IOLS-PEAK or IOHS-PEAK threshold. The open drain transistor is active with a small delay (t OL), after the overload condition is detected. Overload is not detected when EN/DIAG pin is at a low logic level. Overload is not detected in cut-off conditions: if the output stage remains in a current limitation (OL) condition for a time longer than the tdOUT delay, the output stage is turned off (cut-off condition) and the OL pin is released. The output stage is restarted after the t rOUT restart time. 11.7 Reverse polarity protection The integrated reverse polarity protection (RPP) avoids any damage to the IC in case of erroneous swapped connection of the high voltage pins to the supply and reference rails. These protected pins, despite reverse polarity, are: VCC, GND, OUTH, OUTL and I/Q. In order to protect the IC against any reverse current from load (e.g due to different and unbalanced supply load voltage rails), please refer to section below. 11.8 GND/VCC open wire protection The GND and VCC open wire protections are intended as protections against the disconnection of the application module from ground and/or supply rails. The IC is selfprotected against these events both for high-side and low-side configurations. For Push-Pull configuration an external blocking diode in series to OUTH is necessary if load is connected to VCC supply rail. An external diode in series to OUTL is necessary if the load is connected to GND reference rail. Figure 14: PP configuration, open wire external protections The same considerations for PP configuration are valid for IO-Link configuration. Furthermore, the external resistor between I/Q and load has to be selected to force the IC in UVLO off. A 22 kOhm resistor protects the IC up to VCC = 36 V, even though a lower value resistance can be used according to the following design rule: Rext = [VCC(max.) - Vuvoff(min.)]/ICC(min.) Despite the presence of the external components listed above, the IC is able to meet the standard EMC requirements according to IEC 60947-5-2. Only if higher voltage levels are necessary, then a small CI/Q capacitance between I/Q and GND could be necessary: the 30/39 DocID027660 Rev 10 L6362A Protection and diagnostic effects at high switching frequency of Rext and CI/Q can be limited by a further small capacitance in parallel to Rext. Figure 15: IO-Link configuration, open wire external protections DocID027660 Rev 10 31/39 Typical application 12 L6362A Typical application Figure 16: Typical IO-Link sensor application 2 SEL Microcontroller VCC Linear regulator VDD 1 F Undervoltage lock-out Sensor IRQ GPIOs UART or GPIOs GND IN1 Output stage (transmitter) EN/DIAG IN2 Logic interface OUTI/Q OUTH - Current limit. - Cut-off - Overtemp. - Active clamp OUTL IO-link line VDD IRQ OL I/Q Overload detection Receiver L6362A GIPG020320151308LM Figure 17: Sensor application without microcontroller 32/39 DocID027660 Rev 10 L6362A Typical application Figure 18: Inductive load driver DocID027660 Rev 10 33/39 Package information 13 L6362A Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK (R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 13.1 VFDFPN 12L (3x3x0.90 mm) package information Figure 19: VFDFPN 12L (3x3x0.90 mm) package outline 34/39 DocID027660 Rev 10 L6362A Package information Table 20: VFDFPN 12L (3x3x0.90 mm) package mechanical data mm Dim. Min. Typ. Max. A 0.80 0.90 1.00 A1 0.00 0.02 0.05 A3 b 0.20 BSC 0.15 0.30 D 3.00 BSC E 3.00 BSC D2 1.87 2.02 2.12 E2 1.06 1.21 1.31 e 0.45 BSC L 0.30 k 0.20 0.40 aaa 0.05 bbb 0.10 ccc 0.10 ddd 0.05 eee 0.08 0.50 VFDFPN stands for thermally enhanced plastic: very thin, fine pitch, dual flat package and no lead. The lead size is comprehensive of the thickness of the lead finishing material. Dimensions do not include mold protrusion, not to exceed 0.15 mm. Package outline exclusive of metal burr dimensions. Pits, visible to the naked eye, are not allowed on the marking area. DocID027660 Rev 10 35/39 Package information L6362A Figure 20: VFDFPN 12L (3x3x0.90 mm) recommended footprint 13.2 VFDFPN 12L (3x3x0.90 mm) packing information Figure 21: VFDFPN 12L (3x3x0.90 mm) carrier tape outline 36/39 DocID027660 Rev 10 L6362A Package information Figure 22: VFDFPN 12L (3x3x0.90 mm) reel outline DocID027660 Rev 10 37/39 Revision history 14 L6362A Revision history Table 21: Document revision history Date Revision 20-Mar-2015 1 Initial release. 2 Updated features. Updated section 2.3. Updated min. and max. value of IOLS-PEAK parameter in table 3. Added VEN parameter to table 11. Added VOL and IOL parameter to table 12. Updated EN/DIAG value in table 14 and DIAG value in table 17. 29-Jan-2016 3 Updated section"Features", section "Description", table 2: "Pin description", all tables related to section 5: "Electrical characteristics", section 6: "Output logic", section 9: "Active clamp", section 10: "Slow demagnetization", section 11: "Protection and diagnostic". 03-Feb-2016 4 Document status promoted from preliminary to production data. 16-Mar-2016 5 Updated the device summary table. 01-Apr-2016 6 Updated VFDFPN 12L (3x3x0.90 mm) package information. 28-Apr-2016 7 Updated table titled "Output stage". Updated "Current limitation and cut-off" section. Changed figure titled "Output current in overload condition". 13-Jun-2016 8 Added VFDFPN 12L (3x3x0.90 mm) packing information. 20-Jul-2016 9 Updated OUTI/Q 10 Updated the description and the device summary table. Updated Figure 1: "Block diagram". Updated Section 2.7: "OL". Updated Section 3: "Absolute maximum ratings". Updated Table 7: "Supply", Table 9: "I/Q receiver" and Table 18: "Configuration summary 2". Updated Section 8.1: "Set output stage". Updated Figure 3: "IO-Link operation", Figure 9: "Fast demagnetization operation example. LS configuration (load to VCC)", Figure 14: "PP configuration, open wire external protections" and Figure 15: "IO-Link configuration, open wire external protections". Added Section 11.8: "GND/VCC open wire protection". 04-May-2015 22-Nov-2017 38/39 Changes DocID027660 Rev 10 L6362A IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2017 STMicroelectronics - All rights reserved DocID027660 Rev 10 39/39