HSMS-281x
Surface Mount RF Schottky Barrier Diodes
Data Sheet
Description/Applications
These Schottky diodes are specically designed for both
analog and digital applications. This series oers a wide
range of specications and package congurations to
give the designer wide exibility. The HSMS‑281x series of
diodes features very low icker (1/f) noise.
Note that Avago’s manufacturing techniques assure that
dice found in pairs and quads are taken from adjacent
sites on the wafer, assuring the highest degree of match.
Package Lead Code Identication, SOT-23/SOT-143
(Top View)
COMMON
CATHODE
#4
UNCONNECTED
PAIR
#5
COMMON
ANODE
#3
SERIES
#2
SINGLE
#0
1 2
3
1 2
3 4
RING
QUAD
#7
1 2
3 4
BRIDGE
QUAD
#8
1 2
3 4
1 2
3
1 2
3
1 2
3
Package Lead Code Identication, SOT-323
(Top View)
Package Lead Code Identication, SOT-363
(Top View)
COMMON
CATHODE
F
COMMON
ANODE
E
SERIES
C
SINGLE
B
COMMON
CATHODE QUAD
M
UNCONNECTED
TRIO
L
BRIDGE
QUAD
P
COMMON
ANODE QUAD
N
RING
QUAD
R
1 2 3
6 5 4
HIGH ISOLATION
UNCONNECTED PAIR
K
1 2 3
6 5 4
1 2 3
6 5 4
1 2 3
6 5 4
1 2 3
6 5 4
1 2 3
6 5 4
Notes:
1.
Package marking provides orientation and identication.
2. See “Electrical Specications” for appropriate package marking.
Pin Connections and Package Marking
Features
• Surface Mount Packages
• Low Flicker Noise
• Low FIT (Failure in Time) Rate*
• Six‑sigma Quality Level
• Single, Dual and Quad Versions
• Tape and Reel Options Available
• Lead‑free
• For more information see the Surface Mount Schottky
Reliability Data Sheet.
GUx
1
2
3
6
5
4
2
Electrical Specications TC = 25°C, Single Diode[3]
Maximum Maximum
Minimum Maximum Forward Reverse Typical
Part Package Breakdown Forward Voltage Leakage Maximum Dynamic
Number Marking Lead Voltage Voltage VF (V) @ IR (nA) @ Capacitance Resistance
HSMS[4] Code Code Conguration VBR (V) VF (mV) IF (mA) VR (V) CT (pF) RD (Ω)[5]
2810 B0 0 Single 20 410 1.0 35 200 15 1.2 15
2812 B2 2 Series
2813 B3 3 Common Anode
2814 B4 4 Common Cathode
2815 B5 5 Unconnected Pair
2817 B7 7 Ring Quad[4]
2818 B8 8 Bridge Quad[4]
281B B0 B Single
281C B2 C Series
281E B3 E Common Anode
281F B4 F Common Cathode
281K BK K High Isolation
Unconnected Pair
281L BL L Unconnected Trio
Test Conditions IR = 10 mA IF = 1 mA VF = 0 V IF = 5 mA
f = 1 MHz
Absolute Maximum Ratings[1] TC = 25°C
Symbol Parameter Unit SOT-23/SOT-143 SOT-323/SOT-363
If Forward Current (1 μs Pulse) Amp 1 1
PIV Peak Inverse Voltage V Same as VBR Same as VBR
Tj Junction Temperature °C 150 150
Tstg Storage Temperature °C ‑65 to 150 ‑65 to 150
θjc Thermal Resistance[2] °C/W 500 150
Notes:
1. Operation in excess of any one of these conditions may result in permanent damage to the device.
2. TC = +25°C, where TC is dened to be the temperature at the package pins where contact is made to the circuit board.
ESD WARNING: Handling Precautions Should Be Taken To Avoid Static Discharge.
Notes:
1. ∆VF for diodes in pairs and quads in 15 mV maximum at 1 mA.
2. ∆CTO for diodes in pairs and quads is 0.2 pF maximum.
3. Eective Carrier Lifetime (τ) for all these diodes is 100 ps maximum measured with Krakauer method at 5 mA.
4. See section titled “Quad Capacitance.”
5. RD = RS + 5.2 Ω at 25°C and If = 5 mA.
3
Quad Capacitance
Capacitance of Schottky diode quads is measured using
an HP4271 LCR meter. This instrument eectively isolates
individual diode branches from the others, allowing ac‑
curate capacitance measurement of each branch or each
diode. The conditions are: 20 mV R.M.S. voltage at 1 MHz.
Avago denes this measurement as “CM”, and it is equiva‑
lent to the capacitance of the diode by itself. The equiva‑
lent diagonal and adjacent capaci‑tances can then be cal‑
culated by the formulas given below.
In a quad, the diagonal capacitance is the capacitance be‑
tween points A and B as shown in the gure below. The
diagonal capacitance is calculated using the following
formula
Cj
Rj
RS
Rj = 8.33 X 10-5 nT
Ib + Is
where
Ib = externally applied bias current in amps
Is = saturation current (see table of SPICE parameters)
T = temperature, °K
n = ideality factor (see table of SPICE parameters)
Note:
To effectively model the packaged HSMS-281x product,
please refer to Application Note AN1124.
RS = series resistance (see Table of SPICE parameters)
Cj = junction capacitance (see Table of SPICE parameters)
Linear Equivalent Circuit Model Diode Chip
ESD WARNING:
Handling Precautions Should Be Taken To Avoid Static Discharge.
SPICE Parameters
Parameter Units HSMS-281x
BV V 25
CJ0 pF 1.1
EG eV 0.69
IBV A E‑5
IS A 4.8E‑9
N 1.08
RS Ω 10
PB V 0.65
PT 2
M 0.5
C1 x C 2 C 3 x C 4
CDIAGONAL = _______ + _______
C1 + C 2 C 3 + C 4
1
CADJACENT = C 1 + ____________
1 1 1
–– + –– + ––
C 2 C3C4
Rj = 8.33 X 10 -5 nT
I b + I s
C1 x C 2 C 3 x C 4
CDIAGONAL = _______ + _______
C1 + C 2 C 3 + C 4
1
CADJACENT = C 1 + ____________
1 1 1
–– + –– + ––
C 2 C3C4
Rj = 8.33 X 10 -5 nT
I b + I s
The equivalent adjacent capacitance is the capacitance
between points A and C in the gure below. This capaci‑
tance is calculated using the following formula
This information does not apply to cross‑over quad di‑
odes.
4
Typical Performance, TC = 25°C (unless otherwise noted), Single Diode
Figure 1. Forward Current vs. Forward Voltage at
Temperatures.
0 0.1 0.30.2 0.5 0.60.4 0.80.7
IF – FORWARD CURRENT (mA)
VF – FORWARD VOLTAGE (V)
0.01
10
1
0.1
100
TA = +125C
TA = +75C
TA = +25C
TA = –25C
Figure 2. Reverse Current vs. Reverse Voltage at
Temperatures.
0 5 15
IR – REVERSE CURRENT (nA)
VR – REVERSE VOLTAGE (V)
10
1
1000
100
10
100,000
10,000
TA = +125C
TA = +75C
TA = +25C
Figure 3. Dynamic Resistance vs. Forward
Current.
0.1 1 100
RD – DYNAMIC RESISTANCE ()
IF – FORWARD CURRENT (mA)
10
1
10
1000
100
Figure 4. Total Capacitance vs. Reverse Voltage.
0 2 64 10 128 1614
CT – CAPACITANCE (pF)
VR – REVERSE VOLTAGE (V)
0
0.75
0.50
0.25
1.25
1
VF - FORWARD VOLTAGE (V)
Figure 5. Typical V
f
Match, Pairs and Quads.
30
10
1
0.3
30
10
1
0.3
IF - FORWARD CURRENT (mA)
V
F
- FORWARD VOLTAGE DIFFERENCE (mV)
0.2 0.4 0.6 0.8 1.0 1.2 1.4
IF (Left Scale)
VF (Right Scale)
5
Applications Information
Introduction — Product Selection
Avago’s family of Schottky products provides unique solu‑
tions to many design problems.
The rst step in choosing the right product is to select
the diode type. All of the products in the HSMS‑282x fam‑
ily use the same diode chip, and the same is true of the
HSMS‑281x and HSMS‑280x families. Each family has a dif‑
ferent set of characteristics which can be compared most
easily by consulting the SPICE parameters in Table 1.
A review of these data shows that the HSMS‑280x family
has the highest breakdown voltage, but at the expense of
a high value of series resistance (Rs). In applications which
do not require high voltage the HSMS‑282x family, with a
lower value of series resistance, will oer higher current
carrying capacity and better performance. The HSMS‑281x
family is a hybrid Schottky (as is the HSMS‑280x), oering
lower 1/f or icker noise than the HSMS‑282x family.
In general, the HSMS‑282x family should be the designer’s
rst choice, with the ‑280x family reserved for high volt‑
age applications and the HSMS‑281x family for low icker
noise applications.
Assembly Instructions
SOT-323 PCB Footprint
A recommended PCB pad layout for the miniature SOT‑
323 (SC‑70) package is shown in Figure 6 (dimensions are
in inches). This layout provides ample allowance for pack‑
age placement by automated assembly equipment with‑
out adding parasitics that could impair the performance.
Table 1. Typical SPICE Parameters.
Parameter Units HSMS-280x HSMS-281x HSMS-282x
BV V 75 25 15
CJ0 pF 1.6 1.1 0.7
EG eV 0.69 0.69 0.69
IBV A 1 E‑5 1 E‑5 1 E‑4
IS A 3 E‑8 4.8 E‑9 2.2 E‑8
N 1.08 1.08 1.08
RS Ω 30 10 6.0
PB (VJ) V 0.65 0.65 0.65
PT (XTI) 2 2 2
M 0.5 0.5 0.5
0.026
0.039
0.079
0.022
Dimensions in inches
Figure 6. Recommended PCB Pad Layout for Avago’s SC70 3L/SOT-323 Products.
Assembly Instructions
SOT-363 PCB Footprint
A recommended PCB pad layout for the miniature SOT‑
363 (SC‑70, 6 lead) package is shown in Figure 7 (dimen‑
sions are in inches). This layout provides ample allowance
for package placement by automated assembly equip‑
ment without adding parasitics that could impair the per‑
formance.
Figure 7. Recommended PCB Pad Layout for Avago’s SC70 6L/SOT-363 Products.
6
Figure 8. Surface Mount Assembly Prole.
25
Time
Temperature
Tp
T
L
tp
t
L
t 25°C to Peak
Ramp-up
ts
Ts
min
Ramp-down
Preheat
Critical Zone
T
L
to Tp
Ts
max
Lead-Free Reow Prole Recommendation (IPC/JEDEC J-STD-020C)
Reow Parameter Lead-Free Assembly
Average ramp‑up rate (Liquidus Temperature (TS(max) to Peak) 3°C/ second max
Preheat Temperature Min (TS(min)) 150°C
Temperature Max (TS(max)) 200°C
Time (min to max) (tS) 60‑180 seconds
Ts(max) to TL Ramp‑up Rate 3°C/second max
Time maintained above: Temperature (TL) 217°C
Time (tL) 60‑150 seconds
Peak Temperature (TP) 260 +0/‑5°C
Time within 5 °C of actual Peak temperature (tP) 20‑40 seconds
Ramp‑down Rate 6°C/second max
Time 25 °C to Peak Temperature 8 minutes max
Note 1: All temperatures refer to topside of the package, measured on the package body surface
SMT Assembly
Reliable assembly of surface mount components is a com‑
plex process that involves many material, process, and
equipment factors, including: method of heating (e.g., IR
or vapor phase reow, wave soldering, etc.) circuit board
material, conductor thickness and pattern, type of solder
alloy, and the thermal conductivity and thermal mass of
components. Components with a low mass, such as the
SOT package, will reach solder reow temperatures faster
than those with a greater mass.
Avago’s SOT diodes have been qualied to the time‑tem‑
perature prole shown in Figure 8. This prole is repre‑
sentative of an IR reow type of surface mount assembly
process.
After ramping up from room temperature, the circuit
board with components attached to it (held in place with
solder paste) passes through one or more preheat zones.
The preheat zones increase the temperature of the board
and components to prevent thermal shock and begin
evaporating solvents from the solder paste. The reow
zone briey elevates the temperature suciently to pro‑
duce a reow of the solder.
The rates of change of temperature for the ramp‑up and
cool‑down zones are chosen to be low enough to not
cause deformation of the board or damage to compo‑
nents due to thermal shock. The maximum temperature
in the reow zone (TMAX) should not exceed 260°C.
These parameters are typical for a surface mount assem‑
bly process for Avago diodes. As a general guideline, the
circuit board and components should be exposed only
to the minimum temperatures and times necessary to
achieve a uniform reow of solder.
7
Package Dimensions
Outline 23 (SOT-23) Outline SOT-323 (SC-70 3 Lead)
Part Number Ordering Information
No. of
Part Number Devices Container
HSMS‑281x‑TR2G 10000 13" Reel
HSMS‑281x‑TR1G 3000 7" Reel
HSMS‑281x‑BLKG 100 antistatic bag
x = 0, 2, 3, 4, 5, 7, 8, B, C, E, F, K, L
e
B
e2
e1
E1
C
EXXX
L
D
A
A1
Notes:
XXX-package marking
Drawings are not to scale
DIMENSIONS (mm)
MIN.
0.79
0.000
0.30
0.08
2.73
1.15
0.89
1.78
0.45
2.10
0.45
MAX.
1.20
0.100
0.54
0.20
3.13
1.50
1.02
2.04
0.60
2.70
0.69
SYMBOL
A
A1
B
C
D
E1
e
e1
e2
E
L
e
B
e1
E1
C
EXXX
L
D
A
A1
Notes:
XXX-package marking
Drawings are not to scale
DIMENSIONS (mm)
MIN.
0.80
0.00
0.15
0.08
1.80
1.10
1.80
0.26
MAX.
1.00
0.10
0.40
0.25
2.25
1.40
2.40
0.46
SYMBOL
A
A1
B
C
D
E1
e
e1
E
L
1.30 typical
0.65 typical
8
Device Orientation
For Outline SOT-143
Note: "AB" represents package marking code.
"C" re
p
resents date code.
END VIE
W
8 mm
4 mm
TOP VIEW
ABC ABC ABC ABC
For Outlines SOT-23, -323
For Outline SOT-363
USER
FEED
DIRECTION
COVER TAPE
CARRIER
TAPE
REEL
Note: "AB" represents package marking code.
"C" represents date code.
END VIE
W
8 mm
4 mm
TOP VIEW
ABC ABC ABC ABC
END VIE
W
8 mm
4 mm
TOP VIEW
Note: "AB" represents package marking code.
"C" represents date code.
ABC ABC ABC ABC
Outline 143 (SOT-143) Outline SOT-363 (SC-70 6 Lead)
eB
e2
B1
e1
E1
C
EXXX
L
D
A
A1
Notes:
XXX-package marking
Drawings are not to scale
DIMENSIONS (mm)
MIN.
0.79
0.013
0.36
0.76
0.086
2.80
1.20
0.89
1.78
0.45
2.10
0.45
MAX.
1.097
0.10
0.54
0.92
0.152
3.06
1.40
1.02
2.04
0.60
2.65
0.69
SYMBOL
A
A1
B
B1
C
D
E1
e
e1
e2
E
L
E
HE
D
e
A1
b
A
A2
DIMENSIONS (mm)
MIN.
1.15
1.80
1.80
0.80
0.80
0.00
0.15
0.08
0.10
MAX.
1.35
2.25
2.40
1.10
1.00
0.10
0.30
0.25
0.46
SYMBOL
E
D
HE
A
A2
A1
e
b
c
L
0.650 BCS
L
c
9
Tape Dimensions and Product Orientation
For Outline SOT-23
For Outline SOT-143
9° MAX
A
0
P
P
0
D
P
2
E
F
W
D
1
Ko 8° MAX
B
0
13.5° MAX
t1
DESCRIPTION SYMBOL SIZE (mm) SIZE (INCHES)
LENGTH
WIDTH
DEPTH
PITCH
BOTTOM HOLE DIAMETER
A
0
B
0
K
0
P
D
1
3.15 ± 0.10
2.77 ± 0.10
1.22 ± 0.10
4.00 ± 0.10
1.00 + 0.05
0.124 ± 0.004
0.109 ± 0.004
0.048 ± 0.004
0.157 ± 0.004
0.039 ± 0.002
CAVITY
DIAMETER
PITCH
POSITION
D
P
0
E
1.50 + 0.10
4.00 ± 0.10
1.75 ± 0.10
0.059 + 0.004
0.157 ± 0.004
0.069 ± 0.004
PERFORATION
WIDTH
THICKNESS
W
t1
8.00 + 0.30 – 0.10
0.229 ± 0.013
0.315 + 0.012 – 0.004
0.009 ± 0.0005
CARRIER TAPE
CAVITY TO PERFORATION
(WIDTH DIRECTION)
CAVITY TO PERFORATION
(LENGTH DIRECTION)
F
P
2
3.50 ± 0.05
2.00 ± 0.05
0.138 ± 0.002
0.079 ± 0.002
DISTANCE
BETWEEN
CENTERLINE
W
F
E
P
2
P
0
D
P
D
1
DESCRIPTION SYMBOL SIZE (mm) SIZE (INCHES)
LENGTH
WIDTH
DEPTH
PITCH
BOTTOM HOLE DIAMETER
A
0
B
0
K
0
P
D
1
3.19 ± 0.10
2.80 ± 0.10
1.31 ± 0.10
4.00 ± 0.10
1.00 + 0.25
0.126 ± 0.004
0.110 ± 0.004
0.052 ± 0.004
0.157 ± 0.004
0.039 + 0.010
CAVITY
DIAMETER
PITCH
POSITION
D
P
0
E
1.50 + 0.10
4.00 ± 0.10
1.75 ± 0.10
0.059 + 0.004
0.157 ± 0.004
0.069 ± 0.004
PERFORATION
WIDTH
THICKNESS
W
t1
8.00 + 0.30 – 0.10
0.254 ± 0.013
0.315+ 0.012 – 0.004
0.0100 ± 0.0005
CARRIER TAPE
CAVITY TO PERFORATION
(WIDTH DIRECTION)
CAVITY TO PERFORATION
(LENGTH DIRECTION)
F
P
2
3.50 ± 0.05
2.00 ± 0.05
0.138 ± 0.002
0.079 ± 0.002
DISTANCE
A
0
9° 9XAM ° MAX
t
1
B
0
K
0
Tape Dimensions and Product Orientation
For Outlines SOT-323, -363
P
P
0
P
2
F
W
C
D
1
D
E
A
0
An
t
1
(CARRIER TAPE THICKNESS) T
t
(COVER TAPE THICKNESS)
An
B
0
K
0
DESCRIPTION SYMBOL SIZE (mm) SIZE (INCHES)
LENGTH
WIDTH
DEPTH
PITCH
BOTTOM HOLE DIAMETER
A
0
B
0
K
0
P
D
1
2.40 ± 0.10
2.40 ± 0.10
1.20 ± 0.10
4.00 ± 0.10
1.00 + 0.25
0.094 ± 0.004
0.094 ± 0.004
0.047 ± 0.004
0.157 ± 0.004
0.039 + 0.010
CAVITY
DIAMETER
PITCH
POSITION
D
P
0
E
1.55 ± 0.05
4.00 ± 0.10
1.75 ± 0.10
0.061 ± 0.002
0.157 ± 0.004
0.069 ± 0.004
PERFORATION
WIDTH
THICKNESS
W
t
1
8.00 ± 0.30
0.254 ± 0.02
0.315 ± 0.012
0.0100 ± 0.0008
CARRIER TAPE
CAVITY TO PERFORATION
(WIDTH DIRECTION)
CAVITY TO PERFORATION
(LENGTH DIRECTION)
F
P
2
3.50 ± 0.05
2.00 ± 0.05
0.138 ± 0.002
0.079 ± 0.002
DISTANCE
FOR SOT-323 (SC70-3 LEAD) An 8 °C MAX
FOR SOT-363 (SC70-6 LEAD) 10 °C MAX
ANGLE
WIDTH
TAPE THICKNESS
C
T
t
5.4 ± 0.10
0.062 ± 0.001
0.205 ± 0.004
0.0025 ± 0.00004
COVER TAPE
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Data subject to change. Copyright © 2005-2009 Avago Technologies. All rights reserved. Obsoletes 5989-4021EN
AV02-1367EN - May 29, 2009