CY2DL1510
1:10 Differential LVDS Fanout Buffer
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-54863 Rev. *H Revised February 25, 2011
Features
■Low-voltage differential signal (LVDS) input with on-chip 100-Ω
input termi nation resistor
■Ten differential LVDS outputs
■40-ps maximum output-to-output skew
■600-ps maximum propagation delay
■0.11-ps maximum additive RMS phase jitter at 156.25 MHz
(12-kHz to 20-MHz offset)
■Up to 1.5-GHz operation
■Synchronous clock enable function
■32-pin thin quad flat pack (TQFP) package
■2.5-V or 3.3-V operating voltage[1]
■Commercial and industrial operating temperature rang e
Functional Description
The CY2DL1510 is an ultra-low noise, low-skew,
low-propagation delay 1:10 differential LVDS fanout buffer
targeted to meet the requirements of high-speed clock
distribution applications. The on-chip 100-Ω input termination
resistor reduces board component count, while the synchronous
clock enable function ensures glitch-free output transitions
during enable and disable periods. The device has a fully
differential internal architecture that is optimized to achieve
low-additive jitter and low-skew at operating frequencies of up to
1.5 GHz.
Note
1. Input AC-coupling cap acitors are required for voltage-translation applications.
Logic Block Diagram
Q0
Q0#
Q1
Q1#
Q2
Q2#
Q3
Q3#
IN
IN#
VDD
VSS
CLK_EN 100k
VDD
D
Q
100 Q4
Q4#
Q5
Q5#
Q6
Q6#
Q7
Q7#
Q8
Q8#
Q9
Q9#
VBB
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Document Number: 001-54863 Rev. *H Page 2 of 15
Contents
Pinouts .............................................................................. 3
Absolute Maximum Ratings ............................................ 4
Operating Conditi ons......................... .............. ... ............. 4
DC Electrical Specifications............................................ 5
AC Electrical Specifications............................................ 6
Ordering Information...................................................... 10
Ordering Cod e D ef ini tio n. ... .. ... ... .............. ... ... ........... 10
Package Dimension........................................................ 11
Acronyms........................................................................ 12
Document Conventions.............. .............. ... .............. .. .. 12
Document History Page................ ... ... .............. ............. 13
Sales, Solutions, and Legal Information ......................15
Worldwide Sales and Design Support ........ ............. ..15
Products ....................................................................15
PSoC Solutions ............ ... ... ... .. ... .............. ... ... ...........15
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Document Number: 001-54863 Rev. *H Page 3 of 15
Pinouts
Figure 1. Pin Diagram - CY2DL1510
12345678
9
10
11
12
13
14
15
16
1718192021222324
25
26
27
28
29
30
31
32
VDD
NC
NC
VBB
IN
IN#
VSS
Q3
Q3#
Q4
Q4#
Q5
Q5#
Q6
Q6#
VDD
Q2#
Q2
Q1#
Q1
Q0#
Q0
VDD
VDD
Q7
Q7#
Q8
Q8#
Q9
Q9#
VDD
CLK_EN
CY2DL1510
Table 1. Pin Definitions
Pin No. Pin Name Pin Type Description
1, 9, 16, 25, 32 VDD Power Power supply
2 CLK_EN Input Synchronous clock enable. Low-vol tage complementary metal oxide
semiconductor (LVCMOS)/low-voltage transistor-transistor-logic (LVTTL).
When CLK_EN = Low, Q(0:9) outputs are held low and Q(0:9)# outputs are
held high
3, 4 NC No connection
5V
BB Output LVDS reference voltage output
6 IN Input LVDS input clock
7 IN# Input LVDS complementary input clock
8V
SS Power Ground
10,12,14,17,19,21,
23,26,28,30 Q(0:9)# Output LVDS complementary output clocks
11,13,15,18,20,22,
24,27,29,31 Q(0:9) Output LVDS output clocks
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Document Number: 001-54863 Rev. *H Page 4 of 15
Absolute Maximum Ratings
Parameter Description Condition Min Max Unit
VDD Supply voltage Nonfunctional –0.5 4.6 V
VIN[2] Input voltage, relative to VSS Nonfunctional –0.5 lesser of 4.0
or VDD + 0.4 V
VOUT[2] DC output or I/O Voltage, relative to VSS Nonfunctional –0.5 lesser of 4.0
or VDD + 0.4 V
TSStor age temperature Nonfunctional –55 150 °C
ESDHBM Electrostatic discharge (ESD) protection
(Human body model) JEDEC STD 22-A114-B 2000 – V
LULatch up Meets or exceeds JEDEC Spec
JESD78B IC latc h up test
UL–94 Flammability rating At 1/8 in. V–0
MSL Moisture sensitivity level 3
Operating Conditions
Parameter Description Condition Min Max Unit
VDD Supply voltage 2.5-V supply 2.375 2.625 V
3.3-V supply 3.135 3.465 V
TAAmbient operating temperature Commercial 0 70 °C
Industrial –40 85 °C
tPU Power ramp time Power-up time for VDD to reach
minimum specified voltage (power
ramp must be monotonic.)
0.05 500 ms
Note
2. The voltage on any I /O pin cannot exceed the power pin during power-up. Power supply sequencing is not required.
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Document Number: 001-54863 Rev. *H Page 5 of 15
DC Electrical Specifications
(VDD = 3.3 V ± 5% or 2.5 V ± 5%; TA = 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial))
Parameter Description Condition Min Max Unit
IDD Operating supply current All LVDS outputs terminated with 100 Ω
load[3, 4] – 125 mA
VIH1 Input high Voltage, LVDS input clocks,
IN and IN# –V
DD + 0.3 V
VIL1 Input low voltage, LVDS input clocks,
IN and IN# –0.3 – V
VIH2 Input high voltage, CLK_EN VDD = 3.3 V 2.0 VDD + 0.3 V
VIL2 Input low voltage, CLK_EN VDD = 3.3 V –0.3 0.8 V
VIH3 Input high voltage, CLK_EN VDD = 2.5 V 1.7 VDD + 0.3 V
VIL3 Input low voltage, CLK_EN VDD = 2.5 V –0.3 0.7 V
VID[5] Input differential amplitude See Figure 3 on page 7 0.4 0.8 V
VICM Input common mode voltage See Figure 3 on page 7 0.5 VDD – 0.2 V
IIH Input high current, All inputs Input = VDD[6] – 150 μA
IIL Input low current, All inputs Input = VSS[6] –150 – μA
VPP LVDS differential output voltage peak to
peak, single-ended VDD = 3.3 V or 2.5 V,
RTERM = 100 Ω between Q and Q# pairs[3, 7] 250 470 mV
ΔVOCM Change in VOCM between complementary
output states VDD = 3.3 V or 2.5 V,
RTERM = 100 Ω between Q and Q# pairs[3, 7] –50mV
VBB Output reference voltage 0 to 150 μA output current 1.125 1.375 V
RTERM On-chip differential input termination
resistor 80 120 Ω
RPInternal pull-up resistance,
LVCMOS logic input CLK_EN pin 60 140 kΩ
CIN Input capacitance Measured at 10 MHz per pin – 3 pF
Notes
3. Refer to Figure 2 on page 7.
4. IDD includes current that is dissipated externally in the output termination resistors.
5. VID minimum of 400 mV is required to meet all output AC Electrical Specifications. The device is functional with VID minimum of great er than 200 mV.
6. Positive current flows int o the input pin, negative current flows out of the input pin.
7. Refer to Figure 4 on page 7.
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Document Number: 001-54863 Rev. *H Page 6 of 15
AC Electrical Specifications
(VDD = 3.3 V ± 5% or 2.5 V ± 5%; TA = 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial))
Parameter Description Condition Min Typ Max Unit
FIN Input frequency DC – 1.5 G Hz
FOUT Output frequency FOUT = FIN DC – 1.5 GHz
tPD[10] Propagation delay input pair to output
pair Input rise/fall time < 1.5 ns
(20% to 80%) ––600ps
tODC[11] Output duty cycle 50% duty cycle at input
Frequency range up to 1 GHz 48 – 52 %
tSK1[12] Output-to-output skew Any output to any output, with
same load conditions at DUT ––40ps
tSK1 D[12] Device-to-device output skew Any output to any output between
two or more devices. Devices
must have the same input and
have the same output load.
––150ps
PNADD Additive RMS phase noise
156.25-MHz input
Rise/fall time < 150 ps (20% to 80%)
VID > 400 mV
Offset = 1 kHz – – –120 dBc/Hz
Offset = 10 kHz – – –135 dBc/Hz
Offset = 100 kHz – – –135 dBc/Hz
Offset = 1 MHz – – –150 dBc/Hz
Offset = 10 MHz – – –154 dBc/Hz
Offset = 20 MHz – – –155 dBc/Hz
tJIT[13] Additive RMS phase jitter (Random) 156.25 MHz, 12 kHz to 20 MHz
offset; input rise/fall time < 150 ps
(20% to 80%),
VID > 400 mV
––0.11ps
tR,tF[14] Output rise/fall time , single-ended 50% duty cycle at input,
20% to 80% of full swing
(VOL to VOH)
Input rise/fall time < 1.5 ns
(20% to 80%)
Measured at 1 GHz
––300ps
tSOD Time from clock edge to outputs
disabled Synchronous clock enable
(CLK_EN) switched low ––700ps
tSOE Time from clock edge to outputs
enabled Synchronous clock enable
(CLK_EN) switched high ––700ps
Notes
8. Refer to Figure 2 on page 7.
9. Refer to Figure 4 on page 7.
10.Refer to Figure 5 on page 7.
11. Refer to Figure 6 on page 7.
12.Refer to Figure 7 on page 8.
13.Refer to Figure 8 on page 8.
14.Refer to Figure 9 on page 8.
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Document Number: 001-54863 Rev. *H Page 7 of 15
Figure 2. LVDS Output Termination
Figure 3. Input Differentia l an d Common Mode Voltages
Figure 4. Output Differential and Common Mode Voltages
Figure 5. Input to Any Output Pair Propagation Delay
Figure 6. Output Duty Cycle
Q#
Z = 50
100
BUF
Q
Z = 50
IN VA
VB
IN# VICM = (VA + VB)/2
VID
QV
A
V
B
Q#
V
OCM
= (V
A
+ V
B
)/2
V
PP
ΔV
OCM
= | V
OCM1
– V
OCM2
|
IN#
IN
tPD
QX#
QX
tPW
tODC =tPW
tPERIOD
tPERIOD
QX#
QX
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CY2DL1510
Document Number: 001-54863 Rev. *H Page 8 of 15
Figure 7. Output-to-output and Device-to-device Skew
Figure 8. RMS Phase Jitter
Figure 9. Output Rise/Fall Time
QX#
QX
QY#
QY
QZ#
QZtSK1
tSK1 D
Device 1
Device 2
Phas e noise
Phase noise mar k
Offset Freq uency
f1 f2
A
r ea Under the M as k ed Phase Nois e Plot
Noise Powe
r
RMS Jitter ∝
20%
80%
tRtF
20%
80% VPP
QX#
QX
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CY2DL1510
Document Number: 001-54863 Rev. *H Page 10 of 15
Ordering Information
Ordering Code Definition
Part Number Type Production Flow
Pb-free
CY2DL1510AZC 32-Pin TQFP Commercial, 0 °C to 70 °C
CY2DL1510AZCT 32-Pin TQFP tape and reel Commercial, 0 °C to 70 °C
CY2DL1510AZI 32-Pin TQFP Industrial, –40 °C to 85 °C
CY2DL1510AZIT 32-Pin TQFP tape and reel Industrial, –40 °C to 85 °C
CY
Base part number
2DL15 10
Number of differential output pairs
Company ID: CY = Cypress
AZ
Pb-free TQFP package
Temperature range
C = Commercial
I = Industrial
C/I T
Tape and reel
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Document Number: 001-54863 Rev. *H Page 11 of 15
Package Dimension
Figure 11. 32-Pin Thin Plastic Quad Flat Pack 7 x 7 x 1.0 mm
9.00±0.25 SQ
STAND-OFF
0.60±0.15
12°±1°
R. 0.08 MIN.
0.20 MAX.
1.00 REF.
0° MIN.
0-7°
0.20 MAX.
0.20 MIN.
0.25
(8X)
GAUGE PLANE
7.00±0.10 SQ
0.80
0.37±0.05
0.20 MAX.
0.05 MIN.
0.15 MAX.
1.00±0.05
DIMENSIONS ARE IN MILLIMETERS
1
32
B.S.C.
R. 0.08 MIN.
SEATING PLANE
25
24
8
17
169
SEE DETAIL A
DETAIL A
1.20 MAX.
0.08
51-85063 *C
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Document Number: 001-54863 Rev. *H Page 12 of 15
Acronyms Document Conventions
Table 2. Acronyms Used in this Document
Acronym Description
ESD electrostatic discharge
HBM human body model
JEDEC Joint electron devices engine ering council
LVDS low-voltage differential signal
LVCMOS low-voltage complementary metal oxide
semiconductor
LVTTL low-voltage transistor-transistor logic
OE Output enable
RMS root mean square
TQFP thin quad flat pack
Table 3. Units of Measure
Symbol Unit of Measure
°C degree Celsius
dBc decibels relative to the carrier
GHz giga hertz
Hz hertz
kΩkilo ohm
µA microamperes
µF micro Farad
µs micro second
mA milliamperes
ms millisecond
mV millivolt
MHz megahertz
ns nanosecond
Ωohm
pF pico Farad
ps pico second
Vvolts
Wwatts
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Document Number: 001-54863 Rev. *H Page 13 of 15
Document History Page
Document Title: CY2DL1510 1:10 Differential LVDS Fanout Buffer
Document Number: 001-54863
Revision ECN Orig. of Change Submission
Date Description of Change
** 2744225 CXQ/PYRS 08/19/09 New datasheet.
*A 2782891 CXQ 10/09/09 Updated format of Logic Block Diagram on page 1.
Added TSOD and TSOE sp ecs (700 ps max) to AC Spe cs table.
Added TSETUP and THOLD specs (300 ps min) to AC Specs table.
Changed equation for RMS jitter in Figure 8 to proportio nality.
Changed package drawing from 1.4 mm thickness 51-85088 spec to
1.0 mm thickness 51-850063 spec.
Added “Synchronous Clock Enable Function” to Features on page 1.
*B 2838916 CXQ 01/05/2010 Changed status from “ADVANCE” to “PRELIMINARY”.
Changed from 0.34 ps to 0.25 ps maximum additive jitter in “Feat ures”
on page 1 and in tJIT in the AC Electrical Specs table on page 5.
Added tPU spec to the Operating Conditions table on page 3.
Removed VOD and ΔVOD specs from the DC Electrical Specs table on
page 4.
Added VPP and ΔVPP specs to the AC Electrical Specs t able on page 5.
VPP min = 250 mV and max = 470 mV; ΔVPP max = 50 mV.
Added internal pullup resistance spec for CLK_EN in the DC Electrical
Specs table on page 4. Min = 60 kΩ, Max = 140 kΩ.
Added a measurement definition for CIN in the DC Electrical S pecs table
on page 4.
Changed letter case and some names of all the timing parameters in the
AC Electrical Specs table on page 5 to be consistent with EROS.
Lowered all additive phase noise mask specs by 3 dB in the AC Electrical
Specs table on page 5.
Added condition to tR and tF specs in the AC Electrical specs table on
page 5 that input rise/fall t i me must be less than 1.5 ns (20% to 80%).
Changed letter case and some names of all the timing parameters in
Figures 5, 6, 7, and 9, to be consistent with EROS. Updated Figure 4
with definitions for VPP and ΔVPP.
*C 2885033 CXQ 02/26/2010 Updated 32-Pin TQFP package diagram.
*D 3011766 CXQ 08/20/2010 Changed maximum additive jitter from 0.25 ps to 0.11 ps in “Features”
on page 1 and in tJIT in the AC Electrical Specs table on page 5.
Changed max tPD spec from 480 ps to 600 ps.
Added note 5 to describe IIH and IIL specs.
Removed reference to data distribution from “Functional Description”.
Changed RP for differential inputs from 100 kΩ to 150 kΩ in the Logic
Block Diagram and from 60 kΩ min / 140 kΩ max to 90 kΩ min / 210 kΩ
max in the DC Electrical Specs table.
Added VID max spec of 0.8V in the DC Electrical Specs table.
Updated phase noise specs for 1 k/10 k/100 k/1 M/10 M/20 MHz offset
to -120/-130/-135/-150/-150/-150dBc/Hz, respectively, in the AC
Electrical Specs table.
Added “Frequency range up to 1 GHz” condition to tODC spec.
Added Acronyms and Ordering Code Definition.
*E 3017258 CXQ 08/27/2010 Corrected Outpu t Rise/Fall time diagram.
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*F 3100234 CXQ 11/18/2010 Changed V IN and VOUT specs from 4.0V to “lesser of 4.0 or VDD + 0.4”
Removed 200mA min LU spec, replaced with “Meets or exceeds JEDEC
Spec JESD78B IC Latchup Test”
Moved VPP from AC spec table to DC spec table, removed ΔVPP.
Removed RP spec for differential input clock pins INX and INX#.
Changed CIN condition to “Measured at 10 MHz”.
Changed PNADD specs for 10kHz, 10MHz, and 20MHz offsets.
Added “Measured at 1 GHz” to tR, tF spec condition.
Removed tS and tH specs from AC specs table.
Changed to CY2DL1510AZ package code in Ordering Information.
Added to Z package code in Ordering Code Definition.
*G 3135201 CXQ 01/12/2011 Removed “Preliminary” status heading.
Fixed typo and removed resist ors from IN/IN# in Logic Block Diagram .
Added Figure 10 to describe TSOE and TSOD.
*H 3090938 CXQ 02/25/2011 Post to external web.
Document Title: CY2DL1510 1:10 Differential LVDS Fanout Buffer
Document Number: 001-54863
Revision ECN Orig. of Change Submission
Date Description of Change
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Document Number: 001-548 63 Rev. *H Revised February 25, 2011 Page 15 of 15
All products and company names mentioned in this document may be the trademarks of their respective holders.
CY2DL1510
© Cypress Semico nducto r Co rpor ation , 20 09-2 011. The informat ion con ta ined her ein is subje ct to cha nge w ith out no tice. Cypress S emiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypres s pro d ucts a re n ot war ran t ed no r int e nded to be used fo r
medical, life supp or t, l if e savin g, cr it ical control or saf ety ap pl ic at io ns, unless pursuant to an express written agreement wit h C ypress. Furthermore, Cypre ss does not auth or ize i t s pr o ducts for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress p roducts in life -support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protect ion (Unit ed States and fore ign),
United S t ates copyright laws and international treaty provis ions. Cyp ress he reby gr ant s to l icense e a pers onal, no n-excl usive , non-tr ansfer able license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee prod uct to be used only in conjunction with a Cyp ress
integrated circui t as specified in the applicab le agreement. Any r eproduction, mod ification, translati on, compilatio n, or represent ation of this Sour ce Code except a s specified abo ve is prohibit ed without
the express written permission of Cypres s.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cyp ress does not
assume any liabil ity ar ising ou t of the a pplic ation or use o f any pr oduct or circ uit descri bed herein . Cypress d oes not a uthor ize its p roducts fo r use as critical componen ts in life-su pport systems whe re
a malfuncti on or failure may reason ably be expected to res ult in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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