ASAHI KASEI [AK4341]
192kHz 24-Bit Stereo ΔΣ DAC with 2Vrms Output
AK4341
GENERAL DESCRIPTION
The AK4341 is the 24bit DAC with 2Vrms line output for cost and performance based audio systems.
Using AKM's multi bit architecture for its modulator, the AK4341 delivers a wide dynamic range while
preserving linearity for improved THD+N performance. The AK4341 integrates a combination of SCF and
CTF filters increasing performance for systems with excessive clock jitter. The 24 Bit word length and
192kHz sampling rate make this part ideal for a wide range of applications such as digital STB, DVD,
AC-3 receiver system, etc. The AK4341 is offered in a space saving 16pin TSSOP package.
FEATURES
Sampling Rate Ranging from 8kHz to 192kHz
128 times Oversampling (Normal Speed Mode)
64 times Oversampling (Double Speed Mode)
32 times Oversampling (Quad Speed Mode)
24-Bit 8 times FIR Digital Filter
SCF with High Tolerance to Clock Jitter
2nd Order Analog LPF
Single Ended Output Buffer
Digital de-emphasis
Soft mute
I/F format: 24-Bit MSB justified or I2S
Master clock: 256fs, 384fs, 512fs, 768fs or 1152fs (Normal Speed Mode)
256fs or 384fs (Double Speed Mode)
128fs, 192fs (Quad Speed Mode)
THD+N: -86dB
Dynamic Range: 100dB
Power supply: 3.0 ∼ +3.6V (DAC), +8.55 ∼ +12.6V (Output Buffer)
Ta = -20 to 85°C
Very Small Package: 16pin TSSOP (6.4mm x 5.0mm)
LRC
K
BICK
SDTI
Audio
Data
Interface
MCLK
PDN
ΔΣ
Modulator AOUTL
8X
Interpolator
SCF
LPF
AOUTR
V
DD
V
SS
De-emphasis
Control
Control
Interface
Clock
Divider
SMUTE
DIF
ΔΣ
Modulator
8X
Interpolator
HVDD
SCF
LPF
V
COM
GAIN
DEM
ACKS
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ASAHI KASEI [AK4341]
■ Ordering Guide
AK4341ET -20 ∼ +85°C 16pin TSSOP (0.65mm pitch)
AKD4341 Evaluation Board for AK4341
■ Pin Layout
1
MCLK
LRCK
BIC
K
SMUTE
ACKS
DIF
Top
View
2
3
4
5
6
7
8
GAIN
VCOM
VSS
VDD
HVDD
A
OUTL
A
OUTR
DEM
16
15
14
13
12
11
10
9
PDN
SDTI
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ASAHI KASEI [AK4341]
PIN/FUNCTION
No. Pin Name I/O Function
1 MCLK I Master Clock Input Pin
An external TTL clock should be input on this pin.
2 BICK I Audio Serial Data Clock Pin
3 SDTI I Audio Serial Data Input Pin
4 LRCK I L/R Clock Pin
5 PDN I
Power-Down Mode Pin
When at “L”, the AK4341 is in the power-down mode, held in reset and
AOUTL/R are held in VCOM. The AK4341 must be reset once upon
power-up.
6 SMUTE I Soft Mute Pin in parallel control mode
“H”: Enable, “L”: Disable
7 ACKS I Auto Setting Mode Pin
“L”: Manual Setting Mode, “H”: Auto Setting Mode
8 DIF I Audio Data Interface Format Pin
“L”: 24bit MSB Justified, “H”: I2S
9 DEM I De-emphasis Enable Pin
“H”: Enable, “L”: Disable
10 AOUTR O Rch Analog Output Pin
When PDN pin = “L”, outputs VCOM voltage.
11 AOUTL O Lch Analog Output Pin
When PDN pin = “L”, outputs VCOM voltage.
12 HVDD - Output Buffer Power Supply Pin
Normally connected to VSS with a 0.1μF ceramic capacitor in parallel with a
10μF electrolytic cap.
13 VSS - Ground Pin
14 VDD - DAC Power Supply Pin
15 VCOM O DAC Common Voltage Pin
Normally connected to VSS with a 10μF electrolytic cap.
Outputs VCOM VDD voltage either PDN pin = “L” or “H”.
16 GAIN I
Gain Control Pin.
“H”: +6dB, “L”: 0dB, open: +12dB.
When PDN=“H”, the Gain pin is connected to VDD and VSS with 50kΩ
resisters and held to VDD/2 when open. When PDN=“L”, connected to VSS
with 50kΩ resister.
Note: All input pins except for the GAIN pin should not be left floating.
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ASAHI KASEI [AK4341]
ABSOLUTE MAXIMUM RATINGS
(VSS=0V; Note 1)
Parameter Symbol min max Units
Power Supply DAC
Output Buffer VDD
HVDD -0.3
-0.3 +6.0
+14 V
V
Input Current (any pins except for supplies) IIN - ±10 mA
Input Voltage VIND -0.3 VDD+0.3 V
Ambient Operating Temperature Ta -20 85 °C
Storage Temperature Tstg -65 150 °C
Note 1. All voltages with respect to ground.
WARNING: Operation at or beyond these limits may results in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS=0V; Note 1)
Parameter Symbol min typ max Units
Power Supply DAC
Output Buffer VDD
HVDD +3.0
+8.55 +3.3
+9.0 +3.6
+12.6 V
V
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
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ASAHI KASEI [AK4341]
ANALOG CHARACTERISTICS
(Ta = 25°C; VDD = +3.3V, HVDD = +9.0V; fs = 44.1kHz; BICK = 64fs; Signal Frequency = 1kHz;
24bit Input Data; Measurement frequency = 20Hz ∼ 20kHz; RL ≥5kΩ, GAIN =0dB; unless otherwise specified)
Parameter min typ max Units
Resolution 24 Bits
Dynamic Characteristics (Note 2)
fs=44.1kHz, BW=20kHz -86 -80 dB
fs=96kHz, BW=40kHz -86 - dB
THD+N (0dBFS)
fs=192kHz, BW=40kHz -86 - dB
Dynamic Range (-60dBFS with A-weighted. Note 3) 94 100 dB
S/N (A-weighted. Note 4) 94 100 dB
Interchannel Isolation (1kHz) - 90 dB
Interchannel Gain Mismatch 0.3 - dB
DC Accuracy
Gain Drift 100 - ppm/°C
Output Voltage (Note 5) 1.85 2 2.15 Vrms
Load Capacitance (Note 6) 25 pF
Load Resistance 5 kΩ
Power Supplies
Power Supply Current: (Note 7)
Normal Operation (PDN pin = “H”, fs≤96kHz)
VDD
HVDD
Normal Operation (PDN pin = “H”, fs=192kHz)
VDD
HVDD
Power-Down Mode (PDN pin = “L”, Note 8)
VDD
HVDD
10
7
12
7
10
10
-
-
18
11
100
100
mA
mA
mA
mA
μA
μA
Note 2. Measured by Audio Precision (System Two). Refer to the evaluation board manual.
Note 3. 98dB at 16bit data
Note 4. S/N does not depend on input bit length.
Note 5. Full-scale voltage (0dB). Output voltage is proportional to the voltage of VDD,
AOUT (typ.@0dB, GAIN =0dB) = 2Vrms × VDD/3.3.
Note 6. In case of d riving capacitive load , inset the resister between output p in and the capacitive load .
Note 7. The current into VDD pin or HVDD pin
Note 8. All digital inputs including clock pins (MCLK, BICK and LRCK) are fixed to VSS or VDD, and GAIN pin is
fixed to VSS or open.
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ASAHI KASEI [AK4341]
FILTER CHARACTERISTICS
(Ta = 25°C; VDD = +3.0 ∼ +3.6V, HVDD = +8.55 ∼ +12.6V; fs = 44.1kHz; DEM = OFF, GAIN =0dB)
Parameter Symbol min typ max Units
Digital filter (DEM = OFF)
Passband ±0.05dB (Note 9)
–6.0dB PB 0
-
22.05 20.0
- kHz
kHz
Stopband (Note 9) SB 24.1 kHz
Passband Ripple PR ± 0.02 dB
Stopband Attenuation SA 54 dB
Group Delay (Note 10) GD - 19.3 - 1/fs
De-emphasis Filter (DEM = ON)
De-emphasis Error
(Relative to 0Hz)
fs = 32kHz
fs = 44.1kHz
fs = 48kHz
-
-
-
-
-
-
–1.5/0
–0.2/+0.2
0/+0.6
dB
dB
dB
Digital Filter + LPF (DEM = OFF)
Frequency Response
20.0kHz
40.0kHz
80.0kHz
fs=44.1kHz
fs=96kHz
fs=192kHz
FR
FR
FR
-
-
-
± 0.05
± 0.05
± 0.05
-
-
-
dB
dB
dB
Note 9. The passband and stopband frequencies scale with fs(system sampling rate).
For example, PB=0.4535×fs (@±0.05dB), SB=0.546×fs.
Note 10. The calculating delay time which occurred by digital filtering. This time is from setting the 16/24bit data
of both channels to input register to the output of analog signal.
DC CHARACTERISTICS
(Ta = 25°C; VDD = +3.0 ∼ +3.6V, HVDD = +8.55 ∼ +12.6V)
Parameter Symbol min typ max Units
High-Level Input Voltage (except for GAIN pin)
Low-Level Input Voltage (except for GAIN pin) VIH
VIL 70%VDD
- -
- -
30%VDD V
V
High-Level Input Voltage (for GAIN pin)
Low-Level Input Voltage (for GAIN pin)
Open (for GAIN pin. Note 11)
VIH
VIL
open
90%VDD
-
-
-
-
VDD/2
-
10%VDD
-
V
V
V
Input Leakage Current (Note 12) Iin - -
± 10 μA
Note 11. GAIN pin is biased to VDD and VSS via50kΩ (typ) resisters internally.
Note 12. Except for the GAIN pin
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ASAHI KASEI [AK4341]
SWITCHING CHARACTERISTICS
(Ta = 25°C; VDD = +3.0 ∼ +3.6V, HVDD = +8.55 ∼ +12.6V)
Parameter Symbol min typ max Units
Master Clock Frequency
Duty Cycle fCLK
dCLK 2.048
40 11.2896
36.864
60 MHz
%
LRCK Frequency
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Duty Cycle
fsn
fsd
fsq
Duty
8
32
120
45
48
96
192
55
kHz
kHz
kHz
%
Audio Interface Timing
BICK Period
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
BICK Pulse Width Low
Pulse Width High
BICK “↑” to LRCK Edge (Note 13)
LRCK Edge to BICK “↑” (Note 13)
SDTI Hold Time
SDTI Setup Time
tBCK
tBCK
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
1/128fsn
1/64fsd
1/64fsq
30
30
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
Reset Timing
RSTN Pulse Width (Note 14)
tRST
150
ns
Note 13. BICK rising edge must not occur at the same time as LRCK edge.
Note 14. The AK4341 can be reset by bringing PDN pin = “L”.
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ASAHI KASEI [AK4341]
■ Timing Diagram
1/fCLK
tCLKL
VIH
tCLKH
MCLK VIL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
LRCK VIL
tBCK
tBCKL
VIH
tBCKH
BICK VIL
Clock Timing
tLRB
LRCK
VIH
BICK VIL
tSDS
VIH
SDTI VIL
tSDH
VIH
VIL
tBLR
Serial Interface Timing
tPD
VIL
PDN
Power-down Timing
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ASAHI KASEI [AK4341]
OPERATION OVERVIEW
■ System Clock
The external clocks, which are required t o operate the AK4341, are MCLK, LRCK and BICK. The mast er clock (MCLK)
should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation
filter and the delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS pin
= “L”, Normal Speed Mode), the frequency of MCLK is set automatically. In Auto Setting Mode (ACKS pin = “H”),
MCLK frequency is detected automatically and then the internal master clock becomes the appropriate frequency (Table
1).
The AK4341 is automa tically placed in the power save mode when MCLK stops in the norm al operation mode (PDN pin
= “H”), and the analog output becom es the VCOM voltage. After MC LK is input again, the AK4341 is powered up. After
exiting reset at power-up etc., the AK4341 is in the power-down mode until MCLK and LRCK are input.
ACKS pin LRCK MCLK (MHz)
fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs
Sampling
Speed
H 32.0kHz - - - - 16.3840 24.5760 36.8640
44.1kHz - - - - 22.5792 33.8688 -
48.0kHz - - - - 24.5760 36.8640 -
Normal
88.2kHz - - 22.5792 33.8688 - - -
96.0kHz - - 24.5760 36.8640 - - - Double
176.4kHz 22.5792 33.8688 - - - - -
192.0kHz 24.5760 36.8640 - - - - - Quad
L 32.0kHz - - 8.1920 12.2880 16.3840 24.5760 36.8640
44.1kHz
- - 11.2896 16.9344 22.5792 33.8688 -
Normal
48.0kHz
- - 12.2880 18.4320 24.5760 36.8640 -
Table 1. ACKS pin setting and system clock example
■ Audio Serial Interface Format
The Audio data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF pin can selects two serial data
modes as shown in Table 2. In all m odes the serial data is MSB-first, 2’s compliment form at and latched on the rising edge
of BICK.
Mode DIF SDTI Format BICK Figure
0 L 24bit MSB justified ≥48fs Figure 1
1 H 24bit I2S Figure 2
≥48fs
Table 2. Audio Data Formats
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ASAHI KASEI [AK4341]
LRCK
BICK
(
64fs
)
SDTI
0 22 1 2 24 31 0 1 31 0 1
23:MSB, 0:LSB
22 1 0 Don’t care 23
Lch Data Rch Data
23 30 222 24 23 30
22 1 0 Do n’t care 23 2223
Mode 2
Figure 1. Mode 0 Timing
LRCK
BICK
(
64fs
)
SDTI
0 3 1 2 24 31 0 1 31 0 1
23:MSB, 0:LSB
22 1 0 Don’t care
23
Lch Data Rch Data
23 25 3224 23 25
22 1 0 Don’t care 23 23
Mode 3
Figure 2. Mode 1 Timing
■ De-emphasis Filter
A digital de-emphasis filter is built-in (tc = 50/15µs). DEM pin is internal pull-down pin. Setting DEM pin “H” enables
the digital de-emphasis filter. Refer to the section of “FILTER CHARACTERISTICS” regarding the gain error when the
de-emphasis filter is enabled. De-emphasis filter is off when double/quad speed mode.
DEM pin De-emphasis Filter
H ON
L OFF
Table 3. De-emphasis Filter Control (Normal Speed Mode)
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ASAHI KASEI [AK4341]
■ Output Gain Setting
Outputs level of AOUTL/AOUTR pin can be selected by GAIN pin.
GAIN pin GAIN Input Level Output Level (VDD=3.3V)
L 0dB 0dBFS 2Vrms (typ)
H +6.0dB -6dBFS 2Vrms (typ) (Note 15)
open +12dB -12dBFS 2Vrms (typ) (Note 15)
Note 15. Output level of AOUTL/AOUTR pin clips if it exceeds 2Vrms.
The input data should be 2Vrms or less as the output level.
Table 4. Output Level Setting
■ Soft Mute Operation
Soft mute operat ion is perform ed at digital domain. When the SMUTE pin goes t o “H”, the output signal is attenuated by
-∞ during 1024 LR C K cy cl es. When the SM UTE pi n i s returned t o “L”, the mute is cancelled and the output attenuati on
gradually changes to 0dB during 1024 LRCK cycles. If the soft mute is cancelled within the 1024 LRCK cycles after
starting the operation, t he attenuation is discontinued and returned to 0dB by the same cycle. The soft m ute is effective for
changing the signal source without stopping the signal transmission.
SMUTE pin
ttenuation
1024/fs
0dB
-
∞
A
OUT
1024/fs
GD GD
(1)
(2)
(3)
Notes:
(1) 1020LRCK cycles (1020/fs) at input data is attenuated to -∞.
(2) The analog output corresponding to the digital input has a group delay, GD.
(3) If the soft mute is cancelled before attenuating to -∞ after starting the operation, the att enuation is discontinued and
returned to ATT level by the same cycle.
Figure 3. Soft Mute
■ System Reset
The AK4341 must be reset once by bringing PDN pin = “L” upon power-up. The AK4341 is powered up and the internal
timing starts clocking by LRCK “↑” after exiting reset and power down state by MCLK. The AK4341 is in the
power-down mode until LRCK are input.
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ASAHI KASEI [AK4341]
■ Power-down
The AK4341 is placed in the power-down mode by bringing PDN pin “L” and the analog outputs are VCOM voltage
(VDD). Figure 4 shows an example of the system timing at the power-down and power-up.
Normal Operation
Internal
State
PDN
Power- down Normal Operation
GD GD
“0” data
D/A Out
(Analog)
D/A In
(Digital)
Clock In
M CLK, LRCK, BICK
(1) (3)
External
MUTE (5)
(3) (1)
Mute ON
(2)
(4)
Don’t care
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs are VCOM level (VDD) at the power-down mode.
(3) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN = “L”).
(5) Please mute the analog output externally if the click noise (3) influences system application.
The timing example is shown in this figure.
Figure 4. Power-down/up Sequence Example
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ASAHI KASEI [AK4341]
■ Reset Function
When the MCLK or LRCK stops during the normal operation (PDN pin =”H”), the AK4341 is placed in the reset mode
and its anal og outputs are set to VCOM volt age (VDD). When the MCLK and LRCK are restarted, the AK4341 ret urn to
the normal operat i on mode. The BICK can be stopped when MCLK or LRCK is stopped but shouldn’t be stopped when
MCLK and LRCK are supplied.
Normal Operation
Internal
State Reset Normal Operation
GD GD
D/A Out
(Analog)
D/A In
(Digital)
Clock In
MCLK, BICK, LRCK
(2)
(3)
External
MUTE (6)
VCOM
(2)
MCLK Stop
PDN pin
Power-down
Power-down
(4) (4)
(4)
Hi-Z
(6) (6)
(5)
(1)
Clock In
MCLK, BICK, LRCK
External
MUTE (6)
LRCK Stop
(5)
<Case1:MCLK Stop>
<Case2:LRCK Stop>
(7)
(6) (6)
Notes:
(1) PDN pin should be “L” for 150ns or more after power-on.
(2) The analog output corresponding to digital input has the group delay (GD).
(3) Digital data can be stopped. The click noise after the MCLK and LRCK are input again can be reduced by
inputting the “0” data during this period.
(4) Click noise occurs within 20usec and 20usec +(3∼4LRCK) after the edges(“↑ ↓”) of the PDN pin and MCLK
starting. The noises also occur when MCLK or LRCK is stopped and within 20usec after stopping.
(5) Clocks (MCLK, BICK, LRCK) can be stopped in the reset mode (MCLK or LRCK is stopped).
(6) Mute externally if the click noises (4) cau se problem.
(7) The AK4341 detects the stop of LRCK by the ratio MCLK/LRCK > 2048. If the LRCK is input, when LRCK is
stopping, then the AK4341 exits the reset mode.
Figure 5. Reset Timing Example
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ASAHI KASEI [AK4341]
SYSTEM DESIGN
Figure 6 shows the system connection diagram. An evaluation board (AKD4341) is available in order to allow an easy
study on the layout of a surrounding circuit.
MCLK
1
BICK
2
SDTI
3
LRCK
4
PDN
5
SMUTE
6
A
CKS
7
DIF 8
GAIN 16
VCOM 15
VDD 14
VSS 13
HVDD 12
AOUTL 11
AOUTR 10
DEM 9
Master Clock
Mode-
Setting
AK4341
fs
24bit Audio Data
Reset & Power down
64fs
10u
0.1u +
Rch Out
Lch Out
Analog Ground Digital Ground
A
nalog
Supply 3.3V
+
10u
0.1u
+10u
A
nalog
Supply 9.0V
Figure 6. Typical Connection Diagram (GAIN = 0dB)
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ASAHI KASEI [AK4341]
1. Grounding and Power Supply Decoupling
VDD, HVDD and VSS are supplied from anal og supply and should be separated from system digit al supply . Decoupling
capacitor, especially 0.1μF ceramic capacitor for high frequency should be placed as near to VDD and HVDD as possible.
The differential voltage between VDD and VSS pins set the analog output range. The power-up sequence between
VDD and HVDD is not critical.
2. Analog Outputs
The analog outputs are single-ended and centered around the VDD voltage. The output signal range is typically 2Vrms
(typ @VDD=3.3V). The internal switched-capacitor filter and continuous-time filter attenuate the noise generated by the
delta-sigma m odulator beyond the audio passband. The output voltage is a positive full scale for 7FFFFFH (@24bit) and
a negative full scale for 800000H (@24bit). The ideal output is VDD voltage for 000000H (@24bit).
DC offsets on analog outputs are eliminated by AC coupling since analog outputs have DC offsets of VDD + a few mV.
Figure 7 shows an example of the external LPF with 2Vrms (typ) output.
AOUT
10u 470
2.2nF
AK4341
22k 2V r ms (typ)
Analog
Out
(fc = 154kHz, gain = -0.28dB @ 40kHz, gain = -1.04dB @ 80kHz)
Figure 7. External 1st order LPF Circuit Example
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ASAHI KASEI [AK4341]
PACKAGE
0-10°
Detail A
Seat in g Pl ane 0.10
0.17
±
0.05
0.22±0.1 0.65
*5.0±0.1 1.05±0.05
A
18
916
16
p
in TSSOP
(
Unit: mm
)
*4.4±0.1
6.4±0.2
0.5±0.2
0.1±0.1
NOTE: Dimension "*" does not include mold flash.
0.13 M
■ Package & Lead frame material
Package molding compound: Epoxy
Lead frame material: Cu
Lead frame surface treatment: Solder (Pb free) plate
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ASAHI KASEI [AK4341]
MARKING
AKM
4341ET
XXYYY
1) Pin #1 indication
2) Date Code : XXYYY (5 digits)
XX: Lot#
YYY: Date Code
3) Marketing Code : 4341ET
4) Asahi Kasei Logo
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ASAHI KASEI [AK4341]
Revision History
Date (YY/MM/DD) Revision Reason Page Contents
06/10/30 00 First Edition
07/03/26 01 Error correction 1
3
9
FEATURE
I/F format: 24bit MSB justified, 24/16 bit LSB
justified or I2S
Æ 24bit MSB justified or I2S
PIN/FUNCTION
No.8 “L”: Left Justified Æ 24 bit MSB Justified
AUDIO SERIAL INTERFACE
The DIF pin can select four serial data modes as
shown in Table 2
Æ The DIF pin can select two serial data modes as
shown in Table 2
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering
any use or application, consult the Asahi Kasei Microsys tems Co., Ltd. (AKM) sales office or
authorized distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to customs
and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to
any such use, except with the express written consent of the Representative Director of AKM. As
used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content
and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability
for and hold AKM harmless from any and all claims arising from the use of said product in the
absence of such notification.
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