Industrial Current/Voltage Output Driver
with Programmable Ranges
AD5748
Rev. A
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FEATURES
Current output ranges: 4 mA to 21 mA, 0 mA to 21 mA
±0.15% FSR total unadjusted error (TUE)
±5 ppm/°C FSR typical output drift
Voltage output ranges: 0 V to 5 V, 0 V to 10.5 V, ±10.5 V
±0.05% FSR total unadjusted error (TUE)
±3 ppm/°C FSR output drift
Flexible serial digital interface
On-chip output fault detection
PEC error checking
Asynchronous CLEAR function
Flexible power-up condition to 0 V or tristate
Power supply range
AVDD: +12 V (± 10%) to +24 V (± 10%)
AVSS: −12 V (± 10%) to −24 V (± 10%)
Output loop compliance to AVDD − 2.75 V
Temperature range: −40°C to +105°C
32-lead, 5 mm × 5 mm LFCSP package
APPLICATIONS
Process control
Actuator control
PLCs
GENERAL DESCRIPTION
The AD5748 is a single-channel, low cost, precision, voltage/
current output driver with hardware or software programmable
output ranges. The software ranges are configured via an SPI-/
MICROWIRE™-compatible serial interface. The AD5748 targets
applications in PLC and industrial process control. The analog
input to the AD5748 is provided from a low voltage, single-supply,
digital-to-analog converter (DAC) and is internally conditioned
to provide the desired output current/voltage range. The analog
input range is 0 V to 4.096 V.
The output current range is programmable across two current
ranges: 4 mA to 21 mA and 0 mA to 21 mA.
Voltage output is provided from a separate pin that can be
configured to provide 0 V to 5 V, 0 V to 10.5 V, or ±10.5 V
output range.
Analog outputs are short-circuit and open-circuit protected and
can drive capacitive loads of 2 µF and inductive loads of 0.1 H.
The device is specified to operate with a power supply range from
±12 V to ±24 V. Output loop compliance is 0 V to AVDD − 2.75 V.
The flexible serial interface is SPI- and MICROWIRE-compatible
and can be operated in 3-wire mode to minimize the digital
isolation required in isolated applications. The interface also
features an optional PEC error checking feature using CRC-8
error checking, useful in industrial environments where data
communication corruption can occur.
The device also includes a power-on-reset function, ensuring
that the device powers up in a known state (0 V or tristate),
and a asynchronous CLEAR pin that sets the outputs to zero
scale/midscale voltage output or the low end of the selected
current range.
An HW SELECT pin is used to configure the part for hardware
or software mode on power-up.
Note that the plots in the Typical Performance Characteristics
section of this data sheet contain information on the standard
ranges, as released in the AD5750/AD5750-1 data sheet. Although
the overranges have been tested, new plots were not generated
and substitution data was used for plotting purposes.
Table 1. Related Device
Part Number Description
AD5422 Single-channel, 16-bit, serial input current
source and voltage output DAC
AD5748
Rev. A | Page 2 of 32
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications ..................................................................................... 4
Timing Characteristics ................................................................ 7
Absolute Maximum Ratings ............................................................ 9
ESD Caution .................................................................................. 9
Pin Configuration and Function Descriptions ........................... 10
Typical Performance Characteristics ........................................... 12
Voltage Output ............................................................................ 12
Current Output ........................................................................... 16
Terminology .................................................................................... 21
Theory of Operation ...................................................................... 22
Software Mode ............................................................................ 22
Current Output Architecture .................................................... 24
Driving Inductive Loads ............................................................ 24
Power-On State of the AD5748 ................................................ 24
Default Registers at Power-On ................................................. 25
Reset Function ............................................................................ 25
OUTEN ........................................................................................ 25
Software Control ........................................................................ 25
Hardware Control ...................................................................... 27
Transfer Function ....................................................................... 27
Detailed Description of Features .................................................. 28
Output Fault Alert—Software Mode ....................................... 28
Output Fault Alert—Hardware Mode ..................................... 28
Voltage Output Short-Circuit Protection ................................ 28
Asynchronous Clear (CLEAR) ................................................. 28
Current Setting Resistor ............................................................ 29
Packet Error Checking ............................................................... 29
Applications Information .............................................................. 30
Transient Voltage Protection .................................................... 30
Thermal Considerations ............................................................ 30
Layout Guidelines....................................................................... 30
Galvanically Isolated Interface ................................................. 31
Microprocessor Interfacing ....................................................... 31
Outline Dimensions ....................................................................... 32
Ordering Guide .......................................................................... 32
REVISION HISTORY
5/10—Rev. 0 to Rev. A
Changes to Table 2, Power Requirements ..................................... 6
3/10—Revision 0: Initial Version
AD5748
Rev. A | Page 3 of 32
FUNCTIONAL BLOCK DIAGRAM
CLEAR
VSENSE+
VOUT
VSENSE–
REXT1
IOUT
DVCC GND
A
VDD GND COMP1 COMP2
AD2/R1*AD1/R2*AD0/R3*AVSS
CLRSEL
HW SE LECT
VIN
VREF
SCLK/OUTEN*
SDIN/R0*
SYNC/RSET*
SDO/VFAULT*
INPUT SHIFT
REGISTER
AND
CONTROL
LOGIC
STATUS
REGISTER
VOUT RANGE
SCALING
IOUT RANGE
SCALING
VOUT
SHORT FAULT
POWER-
ON RESET
FAULT/TEMP*
NC/IFAULT*
OVERTEMP
VOUT SHORT F AULT
IOUT OPEN FAULT
PEC ERROR
RESET
AVDD
R2
R
SET
R3
REXT2
IOUT
OPEN FAULT
AD5748
*DENOT E S S HARED P IN. S OFTW ARE MODE DE NOTE D BY REGUL AR TEX T , HARDW ARE M ODE
DENOTED BY ITALIC TEXT. FOR EXAMPLE, FOR FAULT/TEMP PIN, IN SOFTWARE MODE, THIS
PIN TAKES ON FAUL T F UNCT IO N. IN HARDW ARE M ODE, T HIS P IN TAKES ONTEMP FUNCTION.
08922-001
Figure 1.
AD5748
Rev. A | Page 4 of 32
SPECIFICATIONS
AVDD/AVSS = ±12 V (± 10%) to ±24 V (± 10%), DVCC = 2.7 V to 5.5 V, GND = 0 V. IOUT: RLOAD = 300 Ω. All specifications TMIN to TMAX,
unless otherwise noted.
Table 2.
Parameter 1Min Typ Max Unit Test Conditions/Comments
INPUT VOLTAGE RANGE Output unloaded
VIN 0 to 4.096 V
Input Leakage Current −1 +1 μA
REFERENCE INPUT
Reference Input Voltage 4.096 V External reference needs to be exactly as
stated; otherwise, accuracy errors show
up as error in output
Input Leakage Current −1 +1 μA
VOLTAGE OUTPUT, VOUT
Output Voltage Ranges 0 5 V
0 10.5 V AVDD must have minimum 1.3 V
headroom
−10.5 +10.5 V AVDD/AVSS must have minimum 1.3 V
headroom
Accuracy
Total Unadjusted Error (TUE)2−0.3 +0.3 % FSR
−0.1 ±0.05 +0.1 % FSR TA = 25°C
Relative Accuracy (INL) −0.02 ±0.005 +0.02 % FSR
Bipolar Zero Error (Offset at
Midscale)
−10 +10 mV ±10.5 V range
−8 ±0.5 +8 mV TA = 25°C, ±10.5 V range
Bipolar Zero Error TC 3 ±1.5 ppm FSR/°C ±10.5 V range
Zero-Scale Error −10 +10 mV ±10.5 V range
−8 ±0.5 +8 mV TA = 25°C, ±10.5 V range
Zero-Scale Error TC3
±1 ppm FSR/°C ±10.5 V range
Zero-Scale/Offset Error −5 +5 mV 0 V to 10.5 V range
−4 ±0.5 +4 mV TA = 25°C, 0 V to 10.5 V range
−3 +3 mV 0 V to 5 V range
−2.2 ±0.3 +2.2 mV TA = 25°C, 0 V to 5 V range
Offset Error TC3
±2 ppm FSR/°C
Gain Error −0.05 +0.05 % FSR All ranges
−0.04 ±0.015 +0.04 % FSR TA = 25°C
Gain Error TC3
±0.5 ppm FSR/°C
Full-Scale Error −0.05 +0.05 % FSR All ranges
−0.04 ±0.015 +0.04 % FSR TA = 25°C
Full-Scale Error TC3
±1.5 ppm FSR/°C
VOLTAGE OUTPUT CHARACTERISTICS3
Headroom 1.3 V Output unloaded
Short-Circuit Current 15 mA
Load 1 kΩ
Capacitive Load Stability TA = 25°C
RLOAD = ∞ 1 nF
RLOAD = 2 kΩ 1 nF
RLOAD = ∞ 2 μF External compensation capacitor required;
see the Driving Inductive Loads section
DC Output Impedance 0.12 Ω
0 V to 5 V range, ¼ to ¾ Step 7 μs Specified with 2 kΩ || 220 pF, ±0.05%
0 V to 5 V range, 40 mV Input Step 4.5 μs Specified with 2 kΩ || 220 pF, ±0.05%
Slew Rate 2 V/μs Specified with 2 kΩ || 220 pF
Output Noise 2.5 μV rms 0.1 Hz to 10 Hz bandwidth
45.5 μV rms 100 kHz bandwidth
AD5748
Rev. A | Page 5 of 32
Parameter 1Min Typ Max Unit Test Conditions/Comments
Output Noise Spectral Density 165 nV/√Hz Measured at 10 kHz; specified with
2 kΩ || 220 pF
AC PSRR −65 dB 200 mV, 50 Hz/60 Hz sine wave
superimposed on power supply voltage
DC PSRR 10 μV/V Outputs unloaded
CURRENT OUTPUT, IOUT
Output Current Ranges 0 21 mA
4 21 mA
Accuracy, Internal RSET 4
Total Unadjusted Error (TUE)2
−0.5 +0.5 % FSR
−0.3 ±0.15 +0.3 % FSR TA = 25°C
Relative Accuracy (INL) −0.02 ±0.01 +0.02 % FSR 4 mA to 21 mA, 0 mA to 21 mA
Offset Error −16 +16 μA 4 mA to 21 mA, 0 mA to 21 mA
−10 +5 +10 μA TA = 25°C
Offset Error TC3
±3 ppm FSR/°C 4 mA to 21 mA, 0 mA to 21 mA
Gain Error −0.2 +0.2 % FSR 4 mA to 21 mA, 0 mA to 21 mA
−0.03 ±0.006 +0.03 % FSR TA = 25°C
Gain TC3
±8 ppm FSR/°C 4 mA to 21 mA, 0 mA to 21 mA
Full-Scale Error −0.2 +0.2 % FSR 4 mA to 21 mA, 0 mA to 21 mA
−0.125 ±0.02 +0.125 % FSR TA = 25°C
Full-Scale TC3
±4 ppm FSR/°C 4 mA to 21 mA, 0 mA to 21 mA
Accuracy, External RSET4
Total Unadjusted Error (TUE)2
−0.3 +0.3 % FSR
−0.1 ±0.02 +0.1 % FSR TA = 25°C
Relative Accuracy (INL) −0.02 ±0.01 +0.02 % FSR 4 mA to 21 mA, 0 mA to 21 mA
Offset Error −14 +14 μA 4 mA to 21 mA, 0 mA to 21 mA
−11 +5 +11 μA TA = 25°C
Offset Error TC3
±2 ppm FSR/°C 4 mA to 21 mA, 0 mA to 21 mA
Gain Error −0.08 +0.08 % FSR 4 mA to 21 mA, 0 mA to 21 mA
−0.07 ±0.02 +0.07 % FSR TA = 25°C
Gain TC ±1 ppm FSR/°C 4 mA to 21 mA, 0 mA to 21 mA
Full-Scale Error −0.1 +0.1 % FSR 4 mA to 21 mA, 0 mA to 21 mA
−0.07 ±0.02 +0.07 % FSR TA = 25°C
Full-Scale TC3
±2 ppm FSR/°C 4 mA to 21 mA, 0 mA to 21 mA
CURRENT OUTPUT CHARACTERISTICS3
Current Loop Compliance Voltage 0 AVDD − 2.75 V
Resistive Load See comments Chosen so that compliance is not
exceeded
Inductive Load See comments Needs appropriate capacitor at higher
inductance values; see the Driving
Inductive Loads section
Settling Time
4 mA to 21 mA, Full-Scale Step 8.5 μs 250 Ω load
120 μA Step, 4 mA to 21 mA Range 1.2 μs 250 Ω load
DC PSRR 1 μA/V
Output Impedance 130 MΩ
DIGITAL INPUT JEDEC compliant
Input High Voltage, VIH 2 V
Input Low Voltage, VIL 0.8 V
Input Current −1 +1 μA Per pin
Pin Capacitance 5 pF Per pin
DIGITAL OUTPUTS3
FAULT, IFAULT, TEMP, VFAULT
Output Low Voltage, VOL 0.4 V 10 kΩ pull-up resistor to DVCC
Output Low Voltage, VOL 0.6 V At 2.5 mA
Output High Voltage, VOH 3.6 V 10 kΩ pull-up resistor to DVCC
AD5748
Rev. A | Page 6 of 32
Parameter 1Min Typ Max Unit Test Conditions/Comments
SDO
Output Low Voltage, VOL 0.5 0.5 V Sinking 200 μA
Output High Voltage, VOH DVCC − 0.5 DVCC − 0.5 V Sourcing 200 μA
High Impedance Output
Capacitance
3 pF
High Impedance Leakage Current −1 +1 μA
POWER REQUIREMENTS
Positive Analog Supply, AVDD 12 24 V ±10%
Negative Analog Supply, AVSS −12 −24 V ±10%
Digital Power Supply, DVCC
Input Voltage 2.7 5.5 V
AIDD 4.4 5.6 mA Output unloaded, output disabled,
R3, R2, R1, R0 = 0, 1, 0, 1
5.2 6.2 mA Current output enabled
5.2 6.2 mA Voltage output enabled
AISS 2.0 2.5 mA Output unloaded, output disabled,
R3, R2, R1, R0 = 0, 1, 0, 1
2.5 3 mA Current output enabled
2.5 3 mA Voltage output enabled
DICC 0.3 1 mA VIH = DVCC, VIL = GND
Power Dissipation 108 mW AVDD/AVSS = ±24 V, outputs unloaded
1 Temperature range: −40°C to +105°C; typical at +25°C.
2 Specification includes gain and offset errors over temperature, and drift after 1000 hours, TA = 125°C.
3 Guaranteed by characterization, but not production tested.
4 See the Current Setting Resistor section.
AD5748
Rev. A | Page 7 of 32
TIMING CHARACTERISTICS
AVDD/AVSS = ±12 V (± 10%) to ±24 V (± 10%), DVCC = 2.7 V to 5.5 V, GND = 0 V. VOUT: RLOAD = 2 kΩ, CL = 200 pF, IOUT: RLOAD =
300 Ω. All specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter 1, 2Limit at TMIN, TMAX Unit Description
t1 20 ns min SCLK cycle time
t2 8 ns min SCLK high time
t3 8 ns min SCLK low time
t4 5 ns min SYNC falling edge to SCLK falling edge setup time
t5 10 ns min
16th SCLK falling edge to SYNC rising edge (on 24th SCLK falling edge if using PEC)
t6 5 ns min Minimum SYNC high time (write mode)
t7 5 ns min Data setup time
t8 5 ns min Data hold time
t9, t10 1.5 μs max CLEAR pulse low/high activation time
t11 5 ns min Minimum SYNC high time (read mode)
t12 40 ns max SCLK rising edge to SDO valid (SDO CL = 15 pF)
t13 10 ns min
RESET pulse low time
1 Guaranteed by characterization, but not production tested.
2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
AD5748
Rev. A | Page 8 of 32
Timing Diagrams
D15
12 16
D0
t
1
t
2
t
5
t
8
t
7
t
3
SCLK
SYNC
SDIN
CLEA
R
VOUT
t
10
t
9
t
13
RESET
t
4
t
6
08922-002
Figure 2. Write Mode Timing Diagram
SCLK
SDIN
SDO
SYNC
A2 A1 A0 R = 1 0XXXXXXXXXXX
XXXXXR3 R2 R1 R0
CLRSEL OUTEN RSET PEC
ERROR OVER
TEMP IOUT
FAULT VOUT
FAULT
12 16
t11
t12
0
8922-003
Figure 3. Readback Mode Timing Diagram
AD5748
Rev. A | Page 9 of 32
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise noted.
Transient currents of up to 100 mA do not cause SCR latch-up.
Table 4. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter Rating
AVDD to GND −0.3 V to +30 V
AVSS to GND +0.3 V to −28 V
AVDD to AVSS −0.3 V to +58 V
DVCC to GND −0.3 V to +7 V
VSENSE+ to GND AVSS to AVDD
VSENSE− to GND ±5.0 V
Digital Inputs to GND −0.3 V to DVCC + 0.3 V or 7 V
(whichever is less)
Digital Outputs to GND −0.3 V to DVCC + 0.3 V or 7 V
(whichever is less)
VREF to GND −0.3 V to +7 V
VIN to GND −0.3 V to +7 V
VOUT, IOUT to GND AVSS to AVDD
Operating Temperature Range, −40°C to +105°C
Industrial
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ max) 125°C
32-Lead LFCSP Package
θJA Thermal Impedance 28°C/W
Lead Temperature JEDEC industry standard
Soldering J-STD-020
ESD (Human Body Model) 3 kV
ESD CAUTION
AD5748
Rev. A | Page 10 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
TOP VIEW
(Not to Scal e)
AD5748
1SDO/VFAULT 2CLRSEL 3CLEAR 4DVCC 5GND 6SYNC/RSET 7
S
CLK/OUTEN 8SDIN/R0
24 VSENSE+
23 VOUT
22 VSENSE–
21 AVSS
20 COMP1
19 COMP2
18 IOUT
17 AVDD
9
AD2/R1 10
AD1/R2 11
AD0/R3 12
REXT2 13
REXT1 14
VREF 15
VIN 16
GND
32 NC/IFAULT
31 FAULT/TEMP
30 RESET
29 HW SELECT
28 NC
27 NC
26 NC
25 NC
NOTES
1. NC = NO CONNE CT.
2
. THE EXPOSED PADDLE IS TIED TO AVSS.
08922-004
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 SDO/VFAULT
Serial Data Output (SDO). In software mode, this pin is used to clock data from the input shift register in
readback mode. Data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK.
This pin is a CMOS output.
Short-Circuit Fault Alert (VFAULT). In hardware mode, this pin acts as a short-circuit fault alert pin and is
asserted low when a short-circuit error is detected. This pin is an open-drain output and must be connected
to a pull-up resistor.
2 CLRSEL
In hardware or software mode, this pin selects the clear value, either zero-scale or midscale code. In software
mode, this pin is implemented as a logic OR with the internal CLRSEL bit.
3 CLEAR
Active High Input. Asserting this pin sets the output current/voltage to zero-scale code or midscale code of the
range selected (user-selectable). CLEAR is a logic OR with the internal clear bit.
In software mode, during power-up, the CLEAR pin level determines the power-on condition of the voltage
channel, which can be active 0 V or tristate. See the Asynchronous Clear (CLEAR) section for more details.
4 DVCC Digital Power Supply.
5 GND Ground Connection.
6 SYNC/RSET Positive Edge-Sensitive Latch (SYNC). In software mode, a rising edge parallel loads the input shift register data
into the AD5748, also updating the output.
Resistor Select (RSET). In hardware mode, this pin chooses whether the internal or the external current sense
resistor is used.
If RSET = 0, the external sense resistor is chosen.
If RSET = 1, the internal sense resistor is chosen.
7 SCLK/OUTEN
Serial Clock Input (SCLK). In software mode, data is clocked into the input shift register on the falling edge of
SCLK. This pin operates at clock speeds of up to 50 MHz.
Output Enable (OUTEN). In hardware mode, this pin acts as an output enable pin.
8 SDIN/R0 Serial Data Input (SDIN). In software mode, data must be valid on the falling edge of SCLK.
Range Decode Bit (R0). In hardware mode, this pin, in conjunction with R1, R2, and R3, selects the output
current/voltage range setting on the part.
9 AD2/R1
Device Addressing Bit (AD2). In software mode, this pin, in conjunction with AD1 and AD0, allows up to eight
devices to be addressed on one bus.
Range Decode Bit (R1). In hardware mode, this pin, in conjunction with R0, R2, and R3, selects the output
current/voltage range setting on the part.
10 AD1/R2
Device Addressing Bit (AD1). In software mode, this pin, in conjunction with AD2 and AD0 allows up to eight
devices to be addressed on one bus.
Range Decode Bit (R2). In hardware mode, this pin, in conjunction with R0, R1, and R3, selects the output
current/voltage range setting on the part.
AD5748
Rev. A | Page 11 of 32
Pin No. Mnemonic Description
11 AD0/R3
Device Addressing Bit (AD0). In software mode, this pin, in conjunction with AD1 and AD2, allows up to eight
devices to be addressed on one bus.
Range Decode Bit (R3). In hardware mode, this pin, in conjunction with, R0, R1, and R2, selects the output
current/voltage range setting on the part.
12, 13 REXT2, REXT1 A 15 kΩ external current setting resistor can be connected between the REXT1 and REXT2 pins to improve the
IOUT temperature drift performance.
14 VREF Buffered Reference Input.
15 VIN Buffered Analog Input (0 V to 4.096 V).
16 GND Ground Connection.
17 AVDD Positive Analog Supply Pin.
18 IOUT Current Output Pin.
19, 20 COMP2,
COMP1
Optional Compensation Capacitor Connections for the Voltage Output Buffer. These are used to drive higher
capacitive loads on the output. These pins also reduce overshoot on the output. Care should be taken when
choosing the value of the capacitor connected between the COMP1 and COMP2 pins because it has a direct
influence on the settling time of the output. See the Driving Large Capacitive Loads section for further details.
21 AVSS Negative Analog Supply Pin.
22 VSENSE−
Sense Connection for the Negative Voltage Output Load Connection. This pin must stay within ±3.0 V of
ground for correct operation.
23 VOUT Buffered Analog Output Voltage.
24 VSENSE+ Sense Connection for the Positive Voltage Output Load Connection.
25, 26,
27, 28
NC No Connect. Can be tied to GND.
29 HW SELECT This pin is used to configure the part to hardware or software mode.
HW SELECT = 0 selects software control.
HW SELECT = 1 selects hardware control.
30 RESET Resets the part to its power-on state.
31 FAULT/TEMP
Fault Alert (FAULT). In software mode, this pin acts as a general fault alert pin. It is asserted low when an open
circuit, short circuit, overtemperature error, or PEC interface error is detected. This pin is an open-drain output
and must be connected to a pull-up resistor.
Overtemperature Fault (TEMP). In hardware mode, this pin acts as an overtemperature fault pin. It is asserted
low when an overtemperature error is detected. This pin is an open-drain output and must be connected to a
pull-up resistor.
32 NC/IFAULT No Connect (NC). In software mode, this pin is a no connect. Instead, tie this pin to GND.
Open-Circuit Fault Alert (IFAULT). In hardware mode, this pin acts as an open-circuit fault alert pin. It is asserted
low when an open-circuit error is detected. This pin is an open-drain output and must be connected to a pull-
up resistor.
33 (EPAD) Exposed
paddle
The exposed paddle is tied to AVSS.
AD5748
Rev. A | Page 12 of 32
TYPICAL PERFORMANCE CHARACTERISTICS
VOLTAGE OUTPUT
0.0020
–0.0030
–0.0025
–0.0020
–0.0015
–0.0010
–0.0005
0
0.0005
0.0010
0.0015
04.0963.5112.9262.3411.7551.1700.585
INL (%FSR)
V
IN
(V)
+5V
+10V
±10V
AV
DD
= +24V
AV
SS
= –24V
08922-005
Figure 5. Integral Nonlinearity Error vs. VIN
0.005
–0.005
–0.004
–0.003
–0.002
–0.001
0
0.001
0.002
0.003
0.004
10525–40
INL (%F SR)
TEMPERATURE (°C)
AV
DD
= +24V
AV
SS
= –24V +5V L INEARI TY, NO LOAD
+10V LINE ARITY, NO LOAD
±10V L I NE ARITY , NO L OAD
08922-006
Figure 6. Integral Nonlinearity Error vs. Temperature
0.006
–0.010
–0.008
–0.006
–0.004
–0.002
0.004
0.002
0
0 4.0963.5112.9262.3411.7551.1700.585
TUE (%FSR)
V
IN
(V)
+5V
+10V
±10V
AV
DD
= +24V
AV
SS
= –24V
0
8922-007
Figure 7. Total Unadjusted Error vs. VIN
0.10
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
10525–40
TUE (%FSR)
TEMPERATURE (°C)
+5V POSITIVE TUE, NO LOAD
+10V POSITIVE TUE, NO LOAD
±10V POSITI VE TUE, NO LO AD
+5V NEGATIVE TUE, NO L OAD
+10V NEGATI VE T UE , NO LOAD
±10V NEGATIVE T UE, NO L OAD
08922-008
Figure 8. Total Unadjusted Error vs. Temperature
0.03
–0.04
–0.03
–0.02
–0.01
0
0.01
0.02
10525–40
FUL L - SCAL E ERRO R (%F S R)
TEMPERATURE (°C)
+5V RANG E, F UL L-S CALE ERRO R
+10V RANG E , FU LL- S CALE E RRO R
±10V RANGE , F ULL- S CALE ERROR
08922-009
Figure 9. Full-Scale Error vs. Temperature
2.5
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
10525–40
BIPOLAR ZERO E RROR (mV)
TEMPERATURE (°C)
±10V Z E RO ERRO R
AV
DD
= +24V
AV
SS
= –24V
08922-010
Figure 10. Bipolar Zero Error vs. Temperature
AD5748
Rev. A | Page 13 of 32
0.020
–0.025
–0.020
–0.015
–0.010
–0.005
0
0.005
0.010
0.015
10525–40
GA IN E R ROR ( % FS R)
TEM P E RATURE (°C)
AV
DD
= +24V
AV
SS
= –24V
+5V GAIN, NO LOAD
+10V GAIN, NO LOAD
±10V GAIN, NO LOAD
08922-011
Figure 11. Gain Error vs. Temperature
2.5
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.5
2.0
1.0
10525–40
ZERO-SCALE ERRO R (mV)
TEM P E RATURE (°C)
AV
DD
= +24V
AV
SS
= –24V
OUTPUT UNL OADED
+5V RANG E
+10V RANGE
±10V RANGE
08922-012
Figure 12. Zero-Scale Error (Offset Error) vs. Temperature
0.003
–0.003
–0.002
–0.001
0
0.001
0.002
INL (%FSR)
SUPPLY VOLTAGES (AV
DD
/AV
SS
)
+11.2/–10.8 ±15.0 ±24.0 ±26.4
+5V LINEARITY , NO LOAD
+10V LINEARITY, NO L OAD
±10V LINEARITY , NO LO AD
08922-013
Figure 13. Integral Nonlinearity Error vs. Supply Voltage
0.10
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
TUE (%FSR)
SUPPLY VOLTAGES (AV
DD
/AV
SS
)
+11.2/–10.8 ±15.0 ±24.0 ±26.4
+5V POSITIVE TUE, NO LOAD
+10V POSIT I VE TUE, NO LO AD
±10V POSITI VE TUE, NO LO AD
+5V NEGATIVE TUE, NO L OAD
+10V NEGATIVE TUE, NO L OAD
±10V NEGATIVE T UE, NO L OAD
08922-014
Figure 14. Total Unadjusted Error vs. Supply Voltages
1.2
1.0
0.8
0.6
0.4
0.2
010525–40
HEADROOM ( V)
TEMPERATURE (°C)
±10V AV
DD
HEADROOM, LO AD OFF
08922-015
Figure 15. AVDD Headroom, ±10 V Range, Output Set to 10 V, Load Off
0.05
–0.05
–0.04
–0.03
–0.02
–0.01
0
0.01
0.02
0.03
0.04
15–15–13–11–9–7–5–3–1 1 3 5 7 9 1113
OUT P UT VO LTAGE DE LTA ( V )
SOURCE /SI NK CURRENT (mA)
+5V RANGE
±10V RANG E
08922-016
Figure 16. Source and Sink Capability of Output Amplifier
AD5748
Rev. A | Page 14 of 32
12
10
8
6
4
2
02722171272–3–8
VOLTAGE (V)
TIME (µs)
08922-017
Figure 17. Full-Scale Positive Step
12
10
8
6
4
2
02722171272–3–8
VOLTAGE (V)
TIME (µs)
08922-018
Figure 18. Full-Scale Negative Step
40
35
30
25
20
15
10
5
0
–5 2.52.01.51.00.50–0.5–1.0
VOUT (mV)
TIME (ms)
08922-019
Figure 19. VOUT vs. Time on Power-Up, Load = 2 kΩ || 200 pF
CH1 5. 00V CH2 20.0m V
BW
M1.0µs A CH1 3.00V
1
2
0
8922-020
Figure 20. VOUT Enable Glitch, Load = 2 kΩ || 1 nF
5µV/DIV 1s/DIV
08922-021
Figure 21. Peak-to-Peak Noise (0.1 Hz to 10 Hz Bandwidth)
100µV/DIV 1s/DIV
08922-022
Figure 22. Peak-to-Peak Noise (100 kHz Bandwidth)
AD5748
Rev. A | Page 15 of 32
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1.0
0.8
0.6
0.4
0.2
0
–0.2
2.01.5
AV
DD
V
OUT
1.00.50–0.5–1.0–1.5
AVDD (V)
VOUT (V)
TIME (ms)
08922-023
Figure 23. AVDD and VOUT vs. Time on Power-Up
AD5748
Rev. A | Page 16 of 32
CURRENT OUTPUT
0.004
–0.010
–0.008
–0.006
–0.004
–0.002
0.002
0
0 4.0963.5112.9262.3411.7551.1700.585
INL (%FSR)
V
IN
(V)
AV
DD
= +24V
AV
SS
= –24V
+4mA TO +20mA
0mA TO +20m A
0
8922-024
Figure 24. Integral Nonlinearity Error vs. VIN, External RSET Resistor
0.004
–0.012
–0.010
–0.008
–0.006
–0.004
–0.002
0.002
0
0 4.0963.5112.9262.3411.7551.1700.585
INL (%FSR)
V
IN
(V)
AV
DD
= +24V
AV
SS
= –24V
+4mA TO +20mA
0mA TO +20mA
0
8922-025
Figure 25. Integral Nonlinearity Error vs. VIN, Internal RSET Resistor
0.010
–0.010
–0.008
–0.006
–0.004
–0.002
0
0.002
0.004
0.006
0.008
INL (%FSR)
SUPPLY VOLTAGES (AV
DD
/AV
SS
)
+11.2/–10.8 ±15.0 ±24.0 ±26.4
+4mA TO +20mA E XTERNAL R
SET
LINEARITY
0mA TO +20mA EXTE RNAL R
SET
LINEARITY
08922-026
Figure 26. Integral Nonlinearity Error, Current Mode,
External RSET Sense Resistor
0.010
–0.010
–0.008
–0.006
–0.004
–0.002
0
0.002
0.004
0.006
0.008
INL (%FSR)
SUPPLY VOLTAGES (AV
DD
/AV
SS
)
+11.2/–10.8 ±15.0 ±24.0 ±26.4
+4mA TO +20mA INTE RNAL R
SET
LINEARITY
0mA TO +20mA INTE RNAL R
SET
LINEARITY
08922-027
Figure 27. Integral Nonlinearity Error Current Mode,
Internal RSET Sense Resistor
0.010
–0.008
–0.006
–0.004
–0.002
0
0.002
0.004
0.006
0.008
0 4.0963.5112.9262.3411.7551.1700.585
TUE (%FSR)
V
IN
(V)
AV
DD
= +24V
AV
SS
= –24V
+4mA T O +20mA
0mA TO +20mA
0
8922-028
Figure 28. Total Unadjusted Error vs. VIN, External RSET Resistor
0.015
–0.015
–0.010
–0.005
0
0.005
0.010
0 4.0963.5112.9262.3411.7551.1700.585
TUE (%FSR)
V
IN
(V)
AV
DD
= +24V
AV
SS
= –24V
+4mA TO +20mA
0mA TO + 20mA
0
8922-029
Figure 29. Total Unadjusted Error vs. VIN, Internal RSET Resistor
AD5748
Rev. A | Page 17 of 32
0.10
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
TUE (%FSR)
SUPPLY VOLTAGES (AV
DD
/AV
SS
)
+11.2/–10.8 ±15.0 ±24.0 ±26.4
+4mA T O +20mA EXTERNAL R
SET
POSI T I VE T UE
0mA TO + 2 0mA E XTERNAL R
SET
POSITIVE TUE
+4mA T O +20mA EXTERNAL R
SET
NEG A T IV E T UE
0mA TO + 2 0mA E XTERNAL R
SET
NEGATIVE TUE
08922-030
Figure 30. Total Unadjusted Error Current Mode, External RSET Sense Resistor
0.10
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
TUE (%FSR)
SUPPLY VOLTAGES (AV
DD
/AV
SS
)
+11.2/–10.8 ±15.0 ±24.0 ±26.4
+4mA TO +20mA INTERNAL R
SET
POSITIVE TUE
0mA TO + 2 0mA I NTERNAL R
SET
POSI TIV E TUE
+4mA TO +20mA INTERNAL R
SET
NEGATIVE TUE
0mA TO + 2 0mA I NTERNAL R
SET
NEGATIVE TUE
08922-031
Figure 31. Total Unadjusted Error Current Mode, Internal RSET Sense Resistor
10525–40 TEMP ERATURE ( °C)
0.010
–0.010
–0.008
–0.006
–0.004
–0.002
0
0.002
0.004
0.006
0.008
INL (%F SR)
+4mA TO +20mA INTERNAL R
SET
LINEARITY
0mA TO + 2 0mA I NTERNAL R
SET
LI NE ARITY
AV
DD
= +24V
AV
SS
= –24V
08922-032
Figure 32. INL vs. Temperature, Internal RSET Sense Resistor
10525–40 TEMP ERATURE ( °C)
0.010
–0.010
–0.008
–0.006
–0.004
–0.002
0
0.002
0.004
0.006
0.008
INL (%F SR)
+4mA T O +20mA EXTERNAL R
SET
LINEARITY
0mA TO + 2 0mA E XTE RNAL R
SET
LINEARITY
AV
DD
= +24V
AV
SS
= –24V
08922-033
Figure 33. INL vs. Temperature, External RSET Sense Resistor
10525–40 TEM PERATURE (°C)
0.10
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
TUE (%FSR)
+4mA TO +20mA I NTERNAL R
SET
POSITIVE TUE
0mA TO + 20mA INTE RNAL R
SET
POSITIVE TUE
+4mA TO +20mA I NTERNAL R
SET
NEGATIVE TUE
0mA TO + 20mA INTE RNAL R
SET
NEGATIVE TUE
08922-034
Figure 34. Total Unadjusted Error vs. Temperature, Internal RSET Sense Resistor
0.10
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
TUE (%FSR)
+4mA TO + 20mA EX TERNAL R
SET
POSI TIV E TUE
0mA TO +20mA EXTERNAL R
SET
POSITI VE TUE
+4mA TO + 20mA EX TERNAL R
SET
NEGATIVE TUE
0mA TO +20mA EXTERNAL R
SET
NEGATIVE TUE
10525–40 TEMP E RATURE (°C)
08922-035
Figure 35. Total Unadjusted Error vs. Temperature, External RSET Sense Resistor
AD5748
Rev. A | Page 18 of 32
6
–6
–4
–2
0
2
4
ZERO-SCALE ERROR (µA)
10525–40 TEMPERATURE (°C)
AV
DD
= +24V
AV
SS
= –24V
+4mA T O +20mA EXTERNAL R
SET
0mA TO +20mA EXTERNAL R
SET
08922-036
Figure 36. Zero-Scale Error vs. Temperature, External RSET Sense Resistor
25
–20
–15
–10
–5
0
5
10
15
20
ZERO-SCALE ERROR (µA)
10525–40 TEMPERATURE (°C)
AV
DD
= +24V
AV
SS
= –24V
+4mA T O +20mA I NTERNAL R
SET
0mA TO +20mA I NT ERNAL R
SET
±20mA INTERNAL R
SET
±24mA INTERNAL R
SET
08922-037
Figure 37. Zero-Scale Error vs. Temperature, Internal RSET Sense Resistor
0.04
–0.04
–0.03
–0.02
–0.01
0
0.01
0.02
0.03
FUL L - SCAL E ERRO R (%F S R)
10525–40 TEMPERATURE (°C)
AV
DD
= +24V
AV
SS
= –24V
+4mA TO +20mA EXTERNAL R
SET
0mA TO + 20mA E X TERNAL R
SET
08922-040
Figure 38. Full-Scale Error vs. Temperature, External RSET Sense Resistor
0.04
–0.06
–0.04
–0.05
–0.03
–0.02
–0.01
0
0.01
0.02
0.03
FUL L - SCAL E ERRO R (%F S R)
10525–40 TEMP E RATURE (°C)
AV
DD
= +24V
AV
SS
= –24V
+4mA T O +20mA I NTERNAL R
SET
0mA TO +20mA I NT ERNAL R
SET
08922-041
Figure 39. Full-Scale Error vs. Temperature, Internal RSET Sense Resistor
0.020
0.015
–0.015
–0.010
–0.005
0
0.005
0.010
GA IN E R ROR ( % FS R)
10525–40 TEMP E RATURE (°C)
AV
DD
= +24V
AV
SS
= –24V
+4mA TO +20mA EXTERNAL R
SET
0mA TO +20mA EXTERNAL R
SET
08922-042
Figure 40. Gain Error vs. Temperature, External RSET Sense Resistor
0.08
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.04
0.02
0.06
GA IN E R ROR ( % FS R)
10525–40 TEMP E RATURE (°C)
AV
DD
= +24V
AV
SS
= –24V
+4mA TO +20mA I NTERNAL R
SET
0mA TO + 20mA INTE RNAL R
SET
08922-043
Figure 41. Gain Error vs. Temperature, Internal RSET Sense Resistor
AD5748
Rev. A | Page 19 of 32
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
COM PLI ANCE (V)
10525–40 TEMPERATURE (°C)
AV
DD
COMP LIANCE
08922-044
Figure 42. Output Compliance vs. Temperature
Tested When IOUT = 10.8 mA
12
10
8
6
4
2
0
–2
0.000010
–0.000010
–0.000008
–0.000006
–0.000004
–0.000002
0
0.000002
0.000004
0.000006
0.000008
10
V
DD
I
OUT
–10–8–6–4–202468
V
DD
(V)
I
OUT
(A)
TIME (ms)
08922-045
Figure 43. Output Current vs. Time on Power-Up
0
–18
–16
–14
–12
–10
–8
–6
–4
–2
8–2–101234567
I
OUT
(V)
TIME (µs)
08922-046
Figure 44. Output Current vs. Time on Output Enable
0.025
0.020
0.015
0.010
0.005
068615448413428211481–12 –6
CURRENT ( A)
TIME (µs)
08922-047
Figure 45. 4 mA to 20 mA Output Current Step
3000
2500
2000
1500
1000
500
00 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
DI
CC
(µA)
LOGIC LEVEL (V)
DV
CC
= 5V
DV
CC
= 3V
08922-048
Figure 46. DICC vs. Logic Input Voltage
AD5748
Rev. A | Page 20 of 32
6
5
4
3
2
1
0
–1
–2
–3
AIDD/AISS (mA)
AVDD/AVSS (V)
±10.8 ±15.0 ±24.0 ±26.4
AIDD
AISS
08922-049
Figure 47. AIDD/AISS vs. AVDD/AVSS, VOUT = 0 V
6
5
4
3
2
1
0
–1
–2
–3
AIDD/AISS (mA)
AVDD/AVSS (V)
±10.8 ±15.0 ±24.0 ±26.4
AIDD
AISS
08922-050
Figure 48. AIDD/AISS vs. AVDD/AVSS, IOUT = 0 mA
AD5748
Rev. A | Page 21 of 32
TERMINOLOGY
Total Unadjus te d Error (TUE)
TUE is a measure of the output error taking all the various
errors into account: INL error, offset error, gain error, and
output drift over supplies, temperature, and time. TUE is
expressed as a percentage of full-scale range (% FSR).
Relative Accuracy or Integral Nonlinearity (INL)
INL is a measure of the maximum deviation, in % FSR, from a
straight line passing through the endpoints of the output driver
transfer function. A typical INL vs. input voltage plot can be
seen in Figure 5.
Bipolar Zero Error
Bipolar zero error is the deviation of the actual vs. ideal half-
scale output of 0 V/0 mA with a bipolar range selected. A plot
of bipolar zero error vs. temperature can be seen in Figure 10.
Bipolar Zero TC
Bipolar zero TC is a measure of the change in the bipolar
zero error with a change in temperature. It is expressed in
ppm FSR/°C.
Full-Scale Error
Full-scale error is the deviation of the actual full-scale analog
output from the ideal full-scale output. Full-scale error is
expressed as a percentage of full-scale range (% FSR).
Full-Scale TC
Full-scale TC is a measure of the change in the full-scale error
with a change in temperature. It is expressed in ppm FSR/°C.
Gain Error
Gain error is a measure of the span error of the output. It is the
deviation in slope of the output transfer characteristic from the
ideal expressed in % FSR. A plot of gain error vs. temperature
can be seen in Figure 11.
Gain Error TC
Gain error TC is a measure of the change in gain error
with changes in temperature. Gain error TC is expressed
in ppm FSR/°C.
Zero-Scale Error
Zero-scale error is the deviation of the actual zero-scale analog
output from the ideal zero-scale output. Zero-scale error is
expressed in millivolts (mV).
Zero-Scale TC
Zero-scale TC is a measure of the change in zero-scale error
with a change in temperature. Zero-scale error TC is expressed
in ppm FSR/°C.
Offset Error
Offset error is a measurement of the difference between VOUT
(actual) and VOUT (ideal) expressed in millivolts (mV) in the
linear region of the transfer function. It can be negative or
positive.
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for
the output to settle to a specified level for a half-scale input change.
Slew Rate
The slew rate of a device is a limitation in the rate of change
of the output voltage. The output slewing speed is usually
limited by the slew rate of the amplifier used at its output.
Slew rate is measured from 10% to 90% of the output signal
and is expressed in V/s.
Current Loop Voltage Compliance
Current loop voltage compliance is the maximum voltage at
the IOUT pin for which the output current is equal to the
programmed value.
Power-On Glitch Energy
Power-on glitch energy is the impulse injected into the analog
output when the AD5748 is powered on. It is specified as the
area of the glitch in nV-sec.
Power Supply Rejection Ratio (PSRR)
PSRR indicates how the output is affected by changes in the
power supply voltage.
AD5748
Rev. A | Page 22 of 32
THEORY OF OPERATION
The AD5748 is a single-channel, precision, voltage/current
output driver with hardware or software programmable
output ranges. The software ranges are configured via an SPI-/
MICROWIRE-compatible serial interface. The analog input
to the AD5748 is provided from a low voltage, single-supply,
digital-to-analog converter and is internally conditioned to
provide the desired output current/voltage range. The analog
input range is 0 V to 4.096 V.
The output current range is programmable across two current
ranges: 4 mA to 21 mA and 0 mA to 21 mA.
The voltage output is provided from a separate pin that can
be configured to provide 0 V to 5 V, 0 V to 10.5 V, or ±10.5 V
output ranges. The current and voltage outputs are available on
separate pins. Only one output can be enabled at one time. The
output range is selected by programming the R3 to R0 bits in
the control register (see Table 6 and Table 7).
Figure 49 and Figure 50 show a typical configuration of the
AD5748 in software mode and in hardware mode, respectively,
in an output module system. The HW SELECT pin selects
whether the part is configured in software or hardware mode.
The analog input to the AD5748 is provided from a low voltage,
single-supply, digital-to-analog converter (DAC) such as the
AD506x or AD566x, which provides an output range of 0 V
to 4.096 V. The supply and reference for the DAC, as well as
the reference for the AD5748, can be supplied from a reference
such as the ADR392. The AD5748 can operate from supplies
up to ±26.4 V.
SOFTWARE MODE
In current mode, software-selectable output ranges include 0 mA
to 21 mA, and 4 mA to 21 mA.
In voltage mode, software-selectable output ranges include 0 V
to 5 V, 0 V to 10.5 V, and ±10.5 V.
VSENSE+
VSENSE–
VIN
SCLK VDD REFIN
SDI/DIN
SDO
SYNC1
SYNC
SDO
SDIN
SCLK
AD506x
AD566x
MCU
VOUT
0V TO + 5V,
0V TO +10.5V,
±10.5V
IOUT
4mA TO 21mA,
0mA TO 21mA
VOUT
RANGE
SCALE
IOUT
RANGE
SCALE
VOUT SHORT FAULT
IO UT O PE N FAUL T
OVERTEMP FAULT
PEC ERROR
STATUS REGIS TER
SERIAL
INTERFACE
VREF
HW S ELECT
FAULT
ADP1720
ADR392
V
DD
A
GND
V
SS
AVDD GND AVSS
AD5748
08922-051
Figure 49. Typical System Configuration in Software Mode (Pull-Up Resistors Not Shown for Open-Drain Outputs)
AD5748
Rev. A | Page 23 of 32
VSENSE+
VSENSE–
R3
R2
R1
R0
OUTPUT RANG E
SELECT PINS
VIN
SCLK VDD REFIN
SDI/DIN
SDO
SYNC1
AD506x
AD566x
MCU
VOUT
0V TO + 5V ,
0V TO + 10 .5V,
±10.5V
IOUT
4mA TO +21mA,
0mA TO +21mA
VOUT
RANGE
SCALE
IOUT
RANGE
SCALE
VREF
TEMP VFAULT IFAULT
ADP1720
ADR3192
V
DD
A
GND
V
SS
AD5748
OUTEN
HW SELECT
DVCC
AVDD GND AVSS
08922-052
Figure 50. Typical System Configuration in Hardware Mode Using Internal DAC Reference (Pull-Up Resistors Not Shown for Open-Drain Outputs)
Table 5. Suggested Parts for Use with AD5748
DAC Reference Power Accuracy Description
AD5660 Internal ADP1720112-bit INL Mid end system, single channel, internal reference
AD5664R Internal N/A N/A Mid end system, quad channel, internal reference
AD5668 Internal N/A N/A Mid end system, octal channel, internal reference
AD5060 ADR434 ADP1720 16-bit INL High end system, single channel, external reference
AD5064 ADR434 N/A N/A High end system, quad channel, external reference
AD5662 ADR3922ADR392212-bit INL Mid end system, single channel, external reference
AD5664 ADR3922N/A N/A Mid end system, quad channel, external reference
1 ADP1720 input range up to 28 V.
2 ADR392 input range up to 15 V.
AD5748
Rev. A | Page 24 of 32
CURRENT OUTPUT ARCHITECTURE
The voltage input from the analog input VIN pin (0 V to 4.096 V)
is either converted to a current (see Figure 51), which is then
mirrored to the supply rail so that the application simply sees
a current source output with respect to an internal reference
voltage, or buffered and scaled to output a software-selectable
unipolar or bipolar voltage range (see Figure 52). The reference
is used to provide internal offsets for range and gain scaling.
The selectable output range is programmable through the
digital interface.
RSET
R2 R3
IOUT
AVDD
T1
IOUT
RANGE
SCALING
RANGEDECODE
FRO M I NT E RF ACE
VIN
T2
VREF
A2
A1
0
8922-059
Figure 51. Current Output Configuration
VOUT RANG E
SCALING
VSENSE+
VOUT
VSENSE–
VOUT
SHORT FAULT
RANGE DECODE
FROM INTERFACE
VIN
(0V TO 4. 096V)
VREF
08922-054
Figure 52. Voltage Output
DRIVING INDUCTIVE LOADS
When driving inductive or poorly defined loads, connect a 0.01 µF
capacitor between IOUT and GND. This ensures stability with
loads beyond 50 mH. There is no maximum capacitance limit.
The capacitive component of the load may cause slower settling.
Voltage Output Amplifier
The voltage output amplifier is capable of generating both
unipolar and bipolar output voltages. It is capable of driving a
load of 1 kΩ in parallel with 1.2 µF (with an external compensa-
tion capacitor on the COMP1 and COMP2 pins). The source
and sink capabilities of the output amplifier can be seen in
Figure 16. The slew rate is 2 V/µs.
Internal to the device, there is a 2.5 MΩ resistor connected
between the VOUT and VSENSE+ pins and similarly between
the VSENSE− pin and the internal device ground. Should a
fault condition occur, these resistors act to protect the AD5748
by ensuring that the amplifier loop is closed so that the part
does not enter into an open-loop condition.
The VSENSE− pin can work in a common-mode range of ±3 V
with respect to the remote load ground point.
The current and voltage are output on separate pins and cannot
be output simultaneously. This allows the user to tie both the
current and voltage output pins together and configure the end
system as a single-channel output.
Driving Large Capacitive Loads
The voltage output amplifier is capable of driving capacitive loads
of up to 1 µF with the addition of a nonpolarized compensation
capacitor between the COMP1 and COMP2 pins.
Without the compensation capacitor, up to 20 nF capacitive loads
can be driven. Care should be taken to choose an appropriate
value for the CCOMP capacitor. This capacitor, while allowing the
AD5748 to drive higher capacitive loads and reduce overshoot,
increases the settling time of the part and, therefore, affects the
bandwidth of the system. Considered values of this capacitor
should be in the range 100 pF to 4 nF depending on the trade-
off required between settling time, overshoot, and bandwidth.
POWER-ON STATE OF THE AD5748
On power-up, the AD5748 senses whether hardware or
software mode is loaded and sets the power-up conditions
accordingly.
In software SPI mode, the power-up state of the output is depen-
dent on the state of the CLEAR pin. If the CLEAR pin is pulled
high, then the part powers up, driving an active 0 V on the
output. If the CLEAR pin is pulled low, then the part powers up
with the voltage output channel in tristate mode. In both cases, the
current output channel powers up in a tristate condition (0 mA).
This allows the voltage and current outputs to be connected
together if desired.
To put the part into normal operation, the user must set the
OUTEN bit in the control register to enable the output and, in
the same write, set the output range configuration using the R3
to R0 range bits. If the CLEAR pin is still high (active) during
this write, the part automatically clears to its normal clear state
as defined by the programmed range and by the CLRSEL pin or
CLRSEL bit (see the Asynchronous Clear (CLEAR) section for
more details). The CLEAR pin must be taken low to operate the
part in normal mode.
The CLEAR pin is typically driven directly from a microcontroller.
In cases where the power supply for the AD5748 supply may be
independent of the microcontroller power supply, the user can
connect a weak pull-up resistor to DVCC or a pull-down resistor
to ground to ensure that the correct power-up condition is
achieved independent of the microcontroller. A 10 kΩ pull-
up/pull-down resistor on the CLEAR pin should be sufficient
for most applications.
If hardware mode is selected, the part powers up to the condi-
tions defined by the R3 to R0 range bits and the status of the
OUTEN or CLEAR pin. It is recommended to keep the output
disabled when powering up the part in hardware mode.
AD5748
Rev. A | Page 25 of 32
DEFAULT REGISTERS AT POWER-ON
The AD5748 power-on reset circuit ensures that all registers are
loaded with zero code.
In software SPI mode, the part powers up with all outputs dis-
abled (OUTEN bit = 0). The user must set the OUTEN bit in
the control register to enable the output and, in the same write,
set the output range configuration using the R3 to R0 bits.
If hardware mode is selected, the part powers up to the
conditions defined by the R3 to R0 bits and the status of the
OUTEN pin. It is recommended to keep the output disabled
when powering up the part in hardware mode.
RESET FUNCTION
In software mode, the part can be reset using the RESET pin
(active low) or the reset bit (reset = 1). A reset disables both the
current and voltage outputs to their power-on condition. The
user must write to the OUTEN bit to enable the output and, in
the same write, set the output range configuration. The RESET
pin is a level-sensitive input; the part stays in reset mode as long
as the RESET pin is low. The reset bit clears to 0 following a
reset command to the control register.
In hardware mode, there is no reset. If using the part in hardware
mode, the RESET pin should be tied high.
OUTEN
In software mode, the output can be enabled or disabled using
the OUTEN bit in the control register. When the output is
disabled, both the current and voltage channels go into tristate.
The user must set the OUTEN bit to enable the output and
simultaneously set the output range configuration.
In hardware mode, the output can be enabled or disabled using
the OUTEN pin. When the output is disabled, both the current
and voltage channels both go into tristate. The user must write
to the OUTEN pin to enable the output. It is recommended
that the output be disabled when changing the ranges.
SOFTWARE CONTROL
Software control is enabled by connecting the HW SELECT pin
to ground. In software mode, the AD5748 is controlled over a
versatile 3-wire serial interface that operates at clock rates of up
to 50 MHz. It is compatible with SPI, QSPI™, MICROWIRE,
and DSP standards.
Input Shift Register
The input shift register is 16 bits wide. Data is loaded into the
device MSB first as a 16-bit word under the control of a serial
clock input, SCLK. Data is clocked in on the falling edge of
SCLK. The input shift register consists of 16 control bits, as
shown in Table 6. The timing diagram for this write operation
is shown in Figure 2. The first three bits of the input shift register
are used to set the hardware address of the AD5748 device on
the printed circuit board (PCB). Up to eight devices can be
addressed per board.
Bit D11, Bit D1, and Bit D0 must always be set to 0 during any
write sequence.
Table 6. Input Shift Register Contents for a Write Operation—Control Register
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
A2 A1 A0
R/W 0 R3 R2 R1 R0 CLRSEL OUTEN Clear RSET Reset 0 0
Table 7. Input Shift Register Descriptions
Bit Description
A2, A1, A0 Used in association with the AD2, AD1, and AD0 external pins to determine which part is being addressed by the system
controller
A2 A1 A0 Function
0 0 0 Addresses part with Pin AD2 = 0, Pin AD1 = 0, Pin AD0 = 0
0 0 1 Addresses part with Pin AD2 = 0, Pin AD1 = 0, Pin AD0 = 1
0 1 0 Addresses part with Pin AD2 = 0, Pin AD1 = 1, Pin AD0 = 0
0 1 1 Addresses part with Pin AD2 = 0, Pin AD1 = 1, Pin AD0 = 1
1 0 0 Addresses part with Pin AD2 = 1, Pin AD1 = 0, Pin AD0 = 0
1 0 1 Addresses part with Pin AD2 = 1, Pin AD1 = 0, Pin AD0 = 1
1 1 0 Addresses part with Pin AD2 = 1, Pin AD1 = 1, Pin AD0 = 0
1 1 1 Addresses part with Pin AD2 = 1, Pin AD1 = 1, Pin AD0 = 1
R/W Indicates a read from or a write to the addressed register
AD5748
Rev. A | Page 26 of 32
Bit Description
R3, R2, R1, R0 Selects output configuration in conjunction with RSET
RSET R3 R2 R1 R0 Output Configuration
0 0 0 0 0 4 mA to 21 mA (external 15 kΩ current sense resistor)
0 0 0 0 1 0 mA to 21 mA (external 15 kΩ current sense resistor)
0 0 0 1 0 N/A
0 0 0 1 1 N/A
0 0 1 0 0 N/A
0 0 1 0 1 0 V to 5 V
0 0 1 1 0 N/A
0 0 1 1 1 N/A
0 1 0 0 0 N/A
0 1 0 0 1 N/A
0 1 0 1 0 0 V to 10.5 V
0 1 0 1 1 N/A
0 1 1 0 0 ±10.5 V
0 1 1 0 1 N/A
0 1 1 1 0 N/A
0 1 1 1 1 N/A
1 0 0 0 0 4 mA to 21 mA (internal current sense resistor)
1 0 0 0 1 0 mA to 21 mA (internal current sense resistor)
1 0 0 1 0 N/A
1 0 0 1 1 N/A
1 0 1 0 0 N/A
1 0 1 0 1 0 V to 5 V
1 0 1 1 0 N/A
1 0 1 1 1 N/A
1 1 0 0 0 N/A
1 1 0 0 1 N/A
1 1 0 1 0 0 V to 10.5 V
1 1 0 1 1 N/A
1 1 1 0 0 ±10.5 V
1 1 1 0 1 N/A
1 1 1 1 0 N/A
1 1 1 1 1 N/A
CLRSEL Sets clear mode to zero scale or midscale. See the Asynchronous Clear (CLEAR) section
CLRSEL Function
0 Clear to 0 V
1 Clear to midscale in unipolar mode; clear to zero scale in bipolar mode
OUTEN Output enable bit. This bit must be set to 1 to enable the outputs
Clear Software clear bit, active high
RSET Select internal/external current sense resistor
RSET Function
1 Select internal current sense resistor; used with the R3 to R0 bits to select range
0 Select external current sense resistor; used with the R3 to R0 bits to select range
Reset Resets the part to its power-on state
AD5748
Rev. A | Page 27 of 32
Readback Operation
Readback mode is activated by selecting the correct device address
(A2, A1, A0) and then setting the R/W bit to 1. By default, the
SDO pin is disabled. After having addressed the AD5748 for a
read operation, setting R/W to 1 enables the SDO pin and SDO
data is clocked out on the 5th rising edge of SCLK. After the data
has been clocked out on SDO, a rising edge on SYNC disables
(tristate) the SDO pin again. Status register data (see )
and control register data are both available during the same
read cycle.
Table 8
The status bits comprise four read-only bits. They are used to
notify the user of specific fault conditions that occur, such as
an open circuit or short circuit on the output, overtemperature
error, or an interface error. If any of these fault conditions occurs,
a hardware FAULT is also asserted low, which can be used as a
hardware interrupt to the controller.
See the Detailed Description of Features section for a full
explanation of fault conditions.
HARDWARE CONTROL
Hardware control is enabled by connecting the HW SELECT
pin to DVCC. In this mode, the R3, R2, R1, and R0 pins in
conjunction with the RSET pin are used to configure the
output range, as per Table 7.
In hardware mode, there is no status register. The fault condi-
tions (open circuit, short circuit, and overtemperature) are
available on Pin IFAULT, Pin VFAULT, and Pin TEMP. If any
one of these fault conditions is set, then a low is asserted on the
specific fault pin. IFAULT, VFAULT, and TEMP are open-drain
outputs and, therefore, can be connected together to allow the
user to generate one interrupt to the system controller to commu-
nicate a fault. If hardwired in this way, it is not possible to
isolate which fault occurred in the system.
TRANSFER FUNCTION
The AD5748 consists of an internal signal conditioning block
that maps the analog input voltage to a programmed output
range. The available analog input range is 0 V to 4.096 V.
For all ranges, both current and voltage, the AD5748 imple-
ments a straight linear mapping function. 0 V maps to the
lower end of the selected range; 4.096 V maps to the upper
end of the selected range.
Table 8. Input Shift Register Contents for a Read Operation—Status Register
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
A2 A1 A0 1 0 R3 R2 R1 R0 CLRSEL OUTEN RSET PEC error OVER TEMP IOUT fault VOUT fault
Table 9. Status Bit Options
Bit Description
PEC Error This bit is set if there is an interface error detected by CRC-8 error checking. See the Detailed Description of Features section.
VOUT Fault This bit is set if there is a short circuit on the VOUT pin.
IOUT Fault This bit is set is there is an open circuit on the IOUT pin.
OVER TEMP This bit is set if the AD5748 core temperature exceeds approximately 150°C.
AD5748
Rev. A | Page 28 of 32
DETAILED DESCRIPTION OF FEATURES
OUTPUT FAULT ALERT—SOFTWARE MODE
In software mode, the AD5748 is equipped with one FAULT
pin; this is an open-drain output allowing several AD5748
devices to be connected together to one pull-up resistor for
global fault detection. In software mode, the FAULT pin is
forced active low by any one of the following fault scenarios:
• The voltage at IOUT attempts to rise above the compliance
range, due to an open-loop circuit or insufficient power
supply voltage. The internal circuitry that develops the
fault output avoids using a comparator with window limits
because this requires an actual output error before the fault
output becomes active. Instead, the signal is generated when
the internal amplifier in the output stage has less than
approximately 1 V of remaining drive capability. Thus,
the fault output activates slightly before the compliance
limit is reached. Because the comparison is made within
the feedback loop of the output amplifier, the output
accuracy is maintained by its open-loop gain, and an output
error does not occur before the fault output becomes active.
• A short is detected on the voltage output pin (VOUT). The
short-circuit current is limited to 15 mA.
• An interface error is detected due to a packet error
checking (PEC) failure. See the Packet Error Checking
section.
• If the core temperature of the AD5748 exceeds
approximately 150°C.
OUTPUT FAULT ALERT—HARDWARE MODE
In hardware mode, the AD5748 is equipped with three fault
pins: VFAULT, IFAULT, and TEMP. These are open-drain
outputs allowing several AD5748 devices to be connected
together to one pull-up resistor for global fault detection. In
hardware control mode, these fault pins are forced active by
any one of the following fault scenarios:
• Open-circuit detect. The voltage at IOUT attempts to rise
above the compliance range, due to an open-loop circuit
or insufficient power supply voltage. The internal circuitry
that develops the fault output avoids using a comparator
with window limits because this requires an actual output
error before the fault output becomes active. Instead, the
signal is generated when the internal amplifier in the
output stage has less than approximately 1 V of remaining
drive capability. Thus, the fault output activates slightly
before the compliance limit is reached. Because the compari-
son is made within the feedback loop of the output amplifier,
the output accuracy is maintained by its open-loop gain,
and an output error does not occur before the fault output
becomes active. If this fault is detected, the IFAULT pin is
forced low.
• A short is detected on the voltage output pin (VOUT).
The short-circuit current is limited to 15 mA. If this fault
is detected, the VFAULT pin is forced low.
• If the core temperature of the AD5748 exceeds approx-
imately 150°C. If this fault is detected, the TEMP pin is
forced low.
VOLTAGE OUTPUT SHORT-CIRCUIT PROTECTION
Under normal operation, the voltage output sinks and sources
up to 12 mA and maintains the specified operation. The maxi-
mum current that the voltage output delivers is 15 mA; this is
the short-circuit current.
ASYNCHRONOUS CLEAR (CLEAR)
CLEAR is an active high clear that allows the voltage output
to be cleared to either zero-scale code or midscale code and is
user-selectable via the CLRSEL pin or the CLRSEL bit of the
input shift register, as described in Table 7. (The clear select
feature is a logical OR function of the CLRSEL pin and the
CLRSEL bit.) The current loop output clears to the bottom of
its programmed range. When the CLEAR signal is returned
low, the output returns to its programmed value or a new value
if programmed. A clear operation can also be performed via the
clear command in the control register.
Table 10. CLRSEL Options
CLRSEL
Output Clear Value
Unipolar Output
Voltage Range Unipolar Current Output Range
0 0 V Zero scale; for example:
4 mA on the 4 mA to 21 mA range
0 mA on the 0 mA to 21 mA range
1 Midscale Midscale; for example:
12.5 mA on the 4 mA to 21 mA range
10.5 mA on the 0 mA to 21 mA range
AD5748
Rev. A | Page 29 of 32
CURRENT SETTING RESISTOR
Referring to Figure 1, RSET is an internal sense resistor as part of
the voltage-to-current conversion circuitry. The nominal value
of the internal current sense resistor is 15 kΩ. To allow for over-
range capability in current mode, the user can also select the
internal current sense resistor to be 14.7 kΩ, giving a nominal
2% overrange capability. This feature is available in the 0 mA
to 21 mA and 4 mA to 21 mA current ranges.
The stability of the output current value over temperature is
dependent on the stability of the value of RSET. As a method of
improving the stability of the output current over temperature,
an external low drift resistor can be connected to the REXT1
and REXT2 pins of the AD5748, which can be used instead of
the internal resistor. The external resistor is selected via the
input shift register. If the external resistor option is not used,
the REXT1 and REXT2 pins should be left floating.
PACKET ERROR CHECKING
To verify that data has been received correctly in noisy environ-
ments, the AD5748 offers the option of error checking based on
an 8-bit (CRC-8) cyclic redundancy check. The device controlling
the AD5748 should generate an 8-bit frame check sequence
using the following polynomial:
C(x) = x8 + x2 + x1 + 1
This is added to the end of the data-word, and 24 data bits are
sent to the AD5748 before taking SYNC high. If the AD5748
receives a 24-bit data frame, it performs the error check when
SYNC goes high. If the check is valid, then the data is written
to the selected register. If the error check fails, the FAULT pin
goes low and Bit D3 of the status register is set. After reading
this register, this error flag is cleared automatically and the
FAULT pin goes high again.
SCLK
SDIN
SYNC UPDATE ON SYNC HIGH
D15
(MSB) D0
(LSB)
16-BIT DATA
16-BIT DAT A T RANS ER— NO ERRO R CHECKI NG
SCLK
SDIN
SYNC
FAULT
UPDATE AF T E R SYNC HI G H
ONL Y I F ERROR CHECK PASS ED
FAULT GOES LOW IF
ERROR CHECK F A ILS
D23
(MSB) D8
(LSB) D7 D0
16-BIT DAT A 8-BIT F CS
16-BIT DAT A T RANS ER WIT H ERRO R CHECKI NG
08922-055
Figure 53. PEC Error Checking Timing
AD5748
Rev. A | Page 30 of 32
APPLICATIONS INFORMATION
TRANSIENT VOLTAGE PROTECTION
The AD5748 contains ESD protection diodes that prevent damage
from normal handling. The industrial control environment can,
however, subject I/O circuits to much higher transients. To protect
the AD5748 from excessively high voltage transients, external
power diodes and a surge current limiting resistor may be
required, as shown in Figure 54. The constraint on the resistor
value is that, during normal operation, the output level at IOUT
must remain within its voltage compliance limit of AVDD − 2.75 V,
and the two protection diodes and resistor must have appropri-
ate power ratings. Further protection can be added with transient
voltage suppressors if needed.
IOUT
AVDD
AVDD
AVSS
AD5748
R
P
R
LOAD
0
8922-056
Figure 54. Output Transient Voltage Protection
THERMAL CONSIDERATIONS
It is important to understand the effects of power dissipation
on the package and on junction temperature. The internal junction
temperature should not exceed 125°C. The AD5748 is packaged
in a 32-lead LFCSP 5, 5 mm × 5 mm package. The thermal
impedance, θJA, is 28°C/W. It is important that the devices are
not operated under conditions that cause the junction tempera-
ture to exceed its junction temperature.
Worst-case conditions occur when the AD5748 is operated from
the maximum AVDD (26.4 V) while driving the maximum
current (24 mA) directly to ground. The quiescent current of the
AD5748 should also be taken into account, nominally ~4 mA.
The following calculations estimate maximum power dissipation
under these worst-case conditions, and determine maximum
ambient temperature based on the power dissipation:
Power Dissipation = 26.4 V × 28 mA = 0.7392 W
Temp Increase = 28°C × 0.7392 W = 20.7°C
Maximum Ambient Temp = 125°C − 20.7°C = 104.3°C
These figures assume that proper layout and grounding
techniques are followed to minimize power dissipation,
as outlined in the Layout Guidelines section.
LAYOUT GUIDELINES
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The PCB on which the AD5748 is
mounted should be designed so that the AD5748 lies on the
analog plane.
The AD5748 should have ample supply bypassing of 10 µF
in parallel with 0.1 µF on each supply located as close to the
package as possible, ideally right up against the device. The
10 µF capacitors are the tantalum bead type. The 0.1 µF capaci-
tor should have low effective series resistance (ESR) and low
effective series inductance (ESI) such as the common ceramic
types, which provide a low impedance path to ground at high
frequencies to handle transient currents due to internal logic
switching.
In systems where there are many devices on one board, it is often
useful to provide some heat sinking capability to allow the power
to dissipate easily.
A
D5748
AVSS
PLANE
BOARD
08922-057
Figure 55. Paddle Connection to Board
The AD5748 has an exposed paddle beneath the device. This
paddle is connected to the AVSS supply for the part. For opti-
mum performance, special considerations should be used to
design the motherboard and to mount the package. For enhanced
thermal, electrical, and board level performance, the exposed
paddle on the bottom of the package is soldered to the correspond-
ing thermal land paddle on the PCB. Thermal vias are designed
into the PCB land paddle area to further improve heat dissipation.
The AVSS plane on the device can be increased (as shown in
Figure 55) to provide a natural heat sinking effect.
AD5748
Rev. A | Page 31 of 32
GALVANICALLY ISOLATED INTERFACE
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled to protect and isolate the controlling circuitry from
any hazardous common-mode voltages that may occur. The
iCoupler® family of products from Analog Devices, Inc., provides
voltage isolation in excess of 5.0 kV. The serial loading structure
of the AD5748 makes it ideal for isolated interfaces because the
number of interface lines is kept to a minimum. Figure 56 shows
a 4-channel isolated interface using an ADuM1400. For further
information, visit www.analog.com/icouplers.
DECODE
ENCODE
V
IA
V
OA
TO
SCLK
V
IB
V
OB
TO
SDIN
V
IC
V
OC
TO
SYNC
V
ID
V
OD
TO
CLEAR
SERIAL
CLOCK OUT
SERIAL
DATA OUT
SYNC OUT
CONTROL OUT
CONTROLLER ADuM14001
1
ADDI TIONAL PINS OMIT TED FOR CL ARIT Y.
DECODE
ENCODE
DECODE
ENCODE
DECODE
ENCODE
08922-058
Figure 56. Isolated Interface
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5748 is via a serial bus
that uses a protocol compatible with microcontrollers and DSP
processors. The communications channel is a 3-wire (minimum)
interface consisting of a clock signal, a data signal, and a SYNC
signal. The AD5748 requires a 16-bit data-word with data valid
on the falling edge of SCLK.
AD5748
Rev. A | Page 32 of 32
COMP LIANT TO J EDEC STANDARDS MO-220- V HHD-2
011708-A
0.23
0.18
OUTLINE DIMENSIONS
0.30 0. 20 RE F
0.80 M A X
0.65 TYP
0.05 M A X
0.02 NOM
12° MAX
1.00
0.85
0.80 SEATING
PLANE
COPLANARITY
0.08
1
32
8
9
25
24
16
17
0.50
0.40
0.30
3.50 RE F
0.50
BSC
PIN 1
INDI
C
ATOR TOP
VIEW
5.00
BSC SQ
4.75
BSC SQ 3.25
3.10 SQ
2.95
PIN 1
INDICATOR
0.60 M AX
0.60 M A X
0.25 MIN
EXPOSED
PAD
(BOTTOM VIEW)
FOR PRO PE R CONNECT IO N O F
THE EXPOSED PAD, REFER TO
THE P IN CONFI GURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 57. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1TUE Accuracy
Analog Input
Range
External
Reference
Temperature
Range Package Description
Package
Option
AD5748ACPZ ±0.3% VOUT, ±0.5% IOUT 0 V to 4.096 V 4.096 V −40°C to +105°C 32-Lead LFCSP_VQ CP-32-2
AD5748ACPZ-RL7 ±0.3% VOUT, ±0.5% IOUT 0 V to 4.096 V 4.096 V −40°C to +105°C 32-Lead LFCSP_VQ CP-32-2
1 Z = RoHS Compliant Part.
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08922-0-5/10(A)
