Data Sheet 1 Rev. 1.01
www.infineon.com/industrial-profet 2018-06-14
Industrial PROFET™
ITS4075Q-EP-D
75 mΩ Quad Channel Smart High-Side Power Switch
1 Overview
Features
• Quad channel Smart High-Side Power Switch with integrated protection
and diagnosis
•Maximum
R
DS(ON) 75 mΩ per channel at
T
j= 25°C
• High output current capability: nominal current up to 2.6 A
• Low and accurate current limitation: 4.1 A (± 20 %)
• Extended supply voltage range up to 45 V
• All control inputs 24 V capable and support direct interface to optocouplers
• All control inputs 3.3 V and 5 V logic level compatible
• 4 kV electrostatic discharge protection (ESD)
• Optimized electromagnetic compatibility
• Very small, thermally enhanced TSDSO-14 package
• Device robustness validated by extended qualification according to JEDEC standard “JESD47J”
• Green product (RoHS compliant)
Potential applications
• Digital output modules (PLC applications, factory automation)
• Industrial peripheral switches and power distribution
• Switching resistive, inductive and capacitive loads in harsh industrial environments
• Replacement for electromechanical relays, fuses and discrete circuits
• Most suitable for loads that require a precise current limit
Product validation
Qualified for industrial applications according to the relevant tests of JEDEC JESD47J.
Data Sheet 2 Rev. 1.01
2018-06-14
ITS4075Q-EP-D
75 mΩ Quad Channel Smart High-Side Power Switch
Overview
Description
The ITS4075Q-EP-D is a 75 mΩ Quad Channel Smart High-Side Power Switch providing integrated protection
functions and a diagnosis feedback. With four channels capable of currents of more than 2 A each, very low
typical
R
DS(ON) values of 120 mΩ at
T
j= 125°C and the small PG-TSDSO-14 exposed pad package it combines
high current capability with minimum space requirements. The exposed pad of the thermally enhanced PG-
TSDSO-14 package allows a very efficient heat transfer from the device to inner layers of the PCB by means of
thermal vias. The power transistors are built by N-channel vertical power MOSFETs (DMOS) with charge pump.
The ITS4075Q-EP-D is specifically designed to switch resistive, inductive or capacitive loads in harsh industrial
environments. The ITS4075Q-EP-D is equipped with essential protection features that make it extremely
robust. Diagnostic information can be read out via the STATUS output (ST). The four channel device can be
controlled with four separate input pins. Due to their high voltage capability the input pins can be directly
interfaced to optocouplers without additional external components.
Diagnostic Functions
• Short circuit to ground (overload) indication
• Overtemperature switch off indication
• Stable diagnostic signal during short circuit and overtemperature shutdown
• Intelligent channel fault detection system
Protection Functions
• Stable behavior during undervoltage
• Overtemperature protection with restart after cooling down phase
• Overload- and short circuit protection
• Reverse polarity / inverse current protection with external components
• Overvoltage protection with external components
• Loss of ground protection
The qualification of this product is based on JEDEC JESD47J and may reference existing qualification results
of similar products. Such referring is justified by the structural similarity of the products. The product is not
qualified and manufactured according to the requirements of Infineon Technologies with regard to
automotive and/or transportation applications. Infineon Technologies administrates a comprehensive
quality management system according to the latest version of the ISO9001 and IATF 16949.
The most updated certificates of the ISO9001 and IATF 16949 are available at
www.infineon.com/cms/en/product/technology/quality/
Type Package Marking
ITS4075Q-EP-D PG-TSDSO-14 ITS4075Q
Data Sheet 3 Rev. 1.01
2018-06-14
ITS4075Q-EP-D
75 mΩ Quad Channel Smart High-Side Power Switch
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Potential applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Product validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Pin Assignment PG-TSDSO-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2 Pin Definitions and Functions PG-TSDSO-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3 Voltage and Current Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2 Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3 Typical Performance Characteristics Operating Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1 Output ON-state Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2 Turn ON/OFF Characteristics with Resistive Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.3 Inductive Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3.1 Output Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3.2 Maximum Load Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4 Inverse Current Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.5 Electrical Characteristics: Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.6 Typical Performance Characteristics Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6 Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1 Loss of Ground Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.2 Undervoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.2.1 Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.3 Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.4 Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.4.1 Current Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.4.2 Temperature Limitation in the Power DMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.5 Electrical Characteristics: Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.6 Typical Performance Characteristics Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7 Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.1 Electrical Characteristics: Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.2 Channel Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.3 Typical Performance Characteristics Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8 Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.1 Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.2 Input Pin Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table of Contents
Data Sheet 4 Rev. 1.01
2018-06-14
ITS4075Q-EP-D
75 mΩ Quad Channel Smart High-Side Power Switch
8.3 Electrical Characteristics: Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.4 Typical Performance Characteristics Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
9 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.1 Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
9.2 Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
10 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
11 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Data Sheet 5 Rev. 1.01
2018-06-14
ITS4075Q-EP-D
75 mΩ Quad Channel Smart High-Side Power Switch
Block Diagram
2 Block Diagram
Figure 1 Block Diagram: ITS4075Q-EP-D
IN1
ST
IN2
IN3
IN4
PG-TSDSO-14
ITS4075Q-EP-D
3
14
2
OUT1
5
Bias
ESD
Protection
Driver
Logic
Over
Temperature
Voltage Sensor
Clamp for
Inductive Loads
Gate control
&
Charge Pump
Over Current
Switch Limit
V
S
12
OUT2
4Control and Protection Circuitry
Equivalent to Channel 1
Channel 1
Channel 2
10
OUT3
6Control and Protection Circuitry
Equivalent to Channel 1
Channel 3
8
OUT4
7Control and Protection Circuitry
Equivalent to Channel 1
Channel 4
V
S
V
S
V
S
GND
Data Sheet 6 Rev. 1.01
2018-06-14
ITS4075Q-EP-D
75 mΩ Quad Channel Smart High-Side Power Switch
Pin Configuration
3 Pin Configuration
3.1 Pin Assignment PG-TSDSO-14
Figure 2 Pin Configuration PG-TSDSO-14
3.2 Pin Definitions and Functions PG-TSDSO-14
Pin Symbol Function
1TMTest Mode Entry; must be connected to device GND (pin 2) via resistor 1)
1) To ensure proper functionality of the device the TM pin must be connected to device ground. In order to protect the
pin furthermore in case of reverse polarity conditions or ground shifts the TM pin needs to be connected with a serial
resistor to device ground. The recommended value for this resistor is 2.2 kΩ.
2GNDGround pin
3IN1INput channel 1; Input signal for channel 1 activation, Active “High”
4IN2INput channel 2; Input signal for channel 2 activation, Active “High”
5STSTatus Feedback; Active “Low”, connect with external pull-up resistor to
“High”
6IN3INput channel 3; Input signal for channel 3 activation, Active “High”
7IN4INput channel 4; Input signal for channel 4 activation, Active “High”
8OUT4OUTput 4; Protected high side power output channel 4
10 OUT3 OUTput 3; Protected high side power output channel 3
12 OUT2 OUTput 2; Protected high side power output channel 2
14 OUT1 OUTput 1; Protected high side power output channel 1
9,11,13 N.C. Not Connected
Exposed Pad VS Voltage Supply
OUT1
OUT4
N.C.
OUT3
N.C.
OUT2
N.C.
TM
IN4
ST
IN1
IN2
GND
1
2
3
4
5
6
7
14
9
10
11
12
13
8
IN3
Data Sheet 7 Rev. 1.01
2018-06-14
ITS4075Q-EP-D
75 mΩ Quad Channel Smart High-Side Power Switch
Pin Configuration
3.3 Voltage and Current Definitions
Figure 3 shows all terms used in this data sheet, with associated convention for positive values.
Figure 3 Voltage and Current Definitions
IN1
IN2
IN3
IN4
ST
VS
GND
OUT1
OUT2
OUT 3
OUT 4
ITS4075Q-EP-D
V
S
V
IN1
V
IN2
V
IN3
V
IN4
V
ST
I
IN1
I
IN2
I
IN3
I
IN4
I
ST
I
S
I
OUT1
I
OUT2
I
OUT3
I
OUT4
V
DS1
V
DS2
V
DS3
V
DS4
V
OUT1
V
OUT2
V
OUT3
V
OUT4
I
GND
Data Sheet 8 Rev. 1.01
2018-06-14
ITS4075Q-EP-D
75 mΩ Quad Channel Smart High-Side Power Switch
General Product Characteristics
4 General Product Characteristics
4.1 Absolute Maximum Ratings
Table 1 Absolute Maximum Ratings 1)
T
j = -40°C to 150°C, positive current flowing into pin; (unless otherwise specified)
Parameter Symbol Values Unit Note or Test Condition Number
Min. Typ. Max.
Supply Voltages
Supply voltage
V
S-0.3 – 45 V – P_4.1.1
Reverse polarity voltage -
V
S(REV) 0–28V2)
t
<2min
T
A= 25°C
R
L≥25 Ω
Z
GND = 150 Ω Power Resistor
P_4.1.3
Supply voltage for short
circuit protection
V
S(SC) 0–36V– P_4.1.4
Input Pins
Voltage at INPUT pins
V
IN -0.3 – 45 V
V
S>
V
IN P_4.1.5
Current through INPUT pins
I
IN -2 – 2 mA – P_4.1.6
STATUS Pin
Voltage at ST pin
V
ST -0.3 – 45 V
V
S>
V
ST P_4.1.7
Current through ST pin
I
ST -2 – 2 mA – P_4.1.8
Power Stage
Power dissipation (DC)
P
TOT – – 1.9 W 3)
T
A= 85°C
T
j< 150°C
P_4.1.10
Maximum energy dissipation
Single pulse (one channel)
E
AS ––60mJ
I
L=2A
T
j= 150°C
V
S=28V
P_4.1.11
Voltage at power transistor
V
DS ––65V– P_4.1.12
Currents
Current through ground pin
I
GND -20 – 20 mA – P_4.1.13
Temporary reverse current
through ground pin to
V
S
I
GND -200 – – mA
t
<2min P_4.1.21
Temperatures
Junction temperature
T
j-40 – 150 °C – P_4.1.14
Storage temperature
T
STG -55 – 150 °C – P_4.1.15
ESD Susceptibility
ESD susceptibility (all pins)
V
ESD_HBM -2 – 2 kV HBM4) P_4.1.16
ESD susceptibility OUT Pin vs.
GND and
V
S connected
V
ESD_HBM -4 – 4 kV HBM4) P_4.1.17
Data Sheet 9 Rev. 1.01
2018-06-14
ITS4075Q-EP-D
75 mΩ Quad Channel Smart High-Side Power Switch
General Product Characteristics
Notes
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in
the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions
are not designed for continuous repetitive operation.
ESD susceptibility
V
ESD_CDM -500 – 500 V CDM5) P_4.1.18
ESD susceptibility pin
(corner pins)
V
ESD_CDM -750 – 750 V CDM5) P_4.1.19
1) Not subject to production test; specified by design.
2) Reverse polarity protection can only be achieved in combination with external components: to limit the current
through the GND-path a 150 Ω power resistor needs to be placed between GND-pin and ground. An alternative
solution is to use a reverse current diode in the GND-path to realize reverse polarity protection. In this case placing a
resistor in the range of ≥27 Ω in series to the diode is recommended to improve at the same time the overvoltage
capability in case of overvoltage pulses on
V
S.
3) This parameter serves as reference for the thermal budget: it illustrates the power dissipation that can be handled
by the device in an application under the given boundary conditions before exceeding the maximum rating of
T
j
when assuming a
R
thJA value for a thermally well dimensioned PCB connection like given in the JEDEC case P_4.3.3
in Chapter 4.4. As
R
thJA depends strongly on the applied PCB and layout of any individual application the actual
achievable values of
P
TOT can either be lower or higher depending on the given application.
4) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS-001(1.5 kΩ, 100 pF).
5) ESD susceptibility, Charged Device Model “CDM” JEDEC JESD22-C101.
Table 1 Absolute Maximum Ratings 1) (cont’d)
T
j = -40°C to 150°C, positive current flowing into pin; (unless otherwise specified)
Parameter Symbol Values Unit Note or Test Condition Number
Min. Typ. Max.
Data Sheet 10 Rev. 1.01
2018-06-14
ITS4075Q-EP-D
75 mΩ Quad Channel Smart High-Side Power Switch
General Product Characteristics
4.2 Functional Range
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics
table.
Table 2 Functional Range
T
j = -40°C to 150°C; (unless otherwise specified)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Nominal operating voltage
V
S(NOM) 82436V
V
S>
V
IN P_4.2.1
Extended operating voltage
V
S(EOP) 5–45V1)
V
S>
V
IN
I
OUT =2A
V
DS <0.5V
P_4.2.2
Minimum functional supply voltage
during power-up
V
S(OP)_MIN –4.35 V
V
S>
V
IN
I
OUT =0A to
V
DS <0.5V
(
V
S rising;
powering up)
P_4.2.3
Undervoltage shutdown
V
S(UV) 33.54.1V
V
S>
V
IN
from
V
DS <0.5V
to
I
OUT =0A
(
V
S dropping
from functional
range)
P_4.2.4
Undervoltage shutdown hysteresis
V
S(UV)_HYS – 850 – mV 1) –
1) Not subject to production test; specified by design.
P_4.2.5
Operating current
One channel active
I
GND_1 –2 3 mA
V
S =
V
IN =24V
Device in
R
DS(ON)
P_4.2.6
Operating current
All channels active
I
GND_4 –5.27 mA
V
S=
V
IN =24V
Device in
R
DS(ON)
P_4.2.9
Junction Temperature
T
j-40 – 150 °C – P_4.2.8
Data Sheet 11 Rev. 1.01
2018-06-14
ITS4075Q-EP-D
75 mΩ Quad Channel Smart High-Side Power Switch
General Product Characteristics
4.3 Typical Performance Characteristics Operating Current
Typical Performance Characteristics
Operating Current
I
GND versus
Junction Temperature
T
j
Operating Current
I
GND versus
Supply Voltage
V
S
−50 0 50 100 150
0
1
2
3
4
5
6
7
T
j
[°C]
I
GND
[mA]
V
S
= 24 V 1 channel active
2 channels active
3 channels active
4 channels active
0 10 20 30 40
0
1
2
3
4
5
6
7
V
S
[V]
I
GND
[mA]
T
j
= 25 °C 1 channel active
2 channels active
3 channels active
4 channels active
Data Sheet 12 Rev. 1.01
2018-06-14
ITS4075Q-EP-D
75 mΩ Quad Channel Smart High-Side Power Switch
General Product Characteristics
4.4 Thermal Resistance
Figure 4 Thermal Impedance (short time scale; one channel active)
Table 3 Thermal Resistance 1)
1) Not subject to production test; specified by design.
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Junction to exposed pad soldering point
R
thJC –1– K/W– P_4.3.1
Junction to ambient
All channels active
R
thJA_2s2pvia –33– K/W
2) –
2) Specified
R
thJA value is according to JEDEC JESD51-2,-5,-7 at natural convection on FR4 2s2p board; the product (chip
+ package) was simulated on a 76.2×114.3×1.5mm board with 2 inner copper layers (2×70µmCu, 2×35µmCu).
Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
P_4.3.3
Junction to ambient
All channels active
R
thJA_1s0p – 102 – K/W 3) –
3) Specified
R
thJA value is according to JEDEC JESD51-3 at natural convection on FR4 1s0p board, footprint;
The product (chip + package) was simulated on a 76.2×114.3×1.5mm board with 1×70µm Cu.
P_4.3.4
Junction to ambient
All channels active
R
thJA_1s0p_300mm –48– K/W
4) –
4) Specified
R
thJA value is according to JEDEC JESD51-3 at natural convection on FR4 1s0p board, 300 mm;
The product (chip + package) was simulated on a 76.2×114.3×1.5mm board with 1×70µm Cu.
P_4.3.5
Junction to ambient
All channels active
R
thJA_1s0p_600mm –40– K/W
5) –
5) Specified
R
thJA value is according to JEDEC JESD51-3 at natural convection on FR4 1s0p board, 600 mm;
The product (chip + package) was simulated on a 76.2×114.3×1.5mm board with 1×70µm Cu.
P_4.3.6
0,00001
0,0001
0,001
0,01
0,1
1
10
100
1000
1,00E-09 1,00E-07 1,00E-05 1,00E-03 1,00E-01
ZtH-JA [K/W]
time [s]
Thermal Impedance (one channel active; PDISSIPATION = 0.81W)
Rth-JA (footprint only)
Rth-JA (1s0p_300mm)
Rth-JA (1s0p_600mm)
Rth-JA (2s2p-via)
Data Sheet 13 Rev. 1.01
2018-06-14
ITS4075Q-EP-D
75 mΩ Quad Channel Smart High-Side Power Switch
General Product Characteristics
Figure 5 Thermal Impedance (long time scale; one channel active)
0
20
40
60
80
100
120
140
1,00E-05 1,00E-03 1,00E-01 1,00E+01 1,00E+03
ZtH-JA [K/W]
time [s]
Thermal Impedance (one channel active; PDISSIPATION = 0.81W)
Rth-JA (footprint only)
Rth-JA (1s0p_300mm)
Rth-JA (1s0p_600mm)
Rth-JA (2s2p-via)
Data Sheet 14 Rev. 1.01
2018-06-14
ITS4075Q-EP-D
75 mΩ Quad Channel Smart High-Side Power Switch
Power Stage
5 Power Stage
The power stages are built using an N-channel vertical power MOSFET (DMOS) with charge pump.
5.1 Output ON-state Resistance
The ON-state resistance
R
DS(ON) of the power stage depends on supply voltage as well as on junction
temperature
T
j. Figure 6 shows the influence of temperature on the typical ON-state resistance. The behavior
of the power stage in reverse polarity condition is described in Chapter 6.3.
Figure 6 Typical ON-state Resistance
5.2 Turn ON/OFF Characteristics with Resistive Load
A “High” signal at the input pin (see Chapter 8) causes the power DMOS to switch ON with a dedicated slope,
which is optimized in terms of EMC emission.
Figure 7 shows the typical timing when switching a resistive load.
Figure 7 Switching a Resistive Load Timing
−50 0 50 100 150
0
20
40
60
80
100
120
140
160
Tj [°C]
RDSON [mΩ]
IN
t
VOUT
tON
tON_delay tOFF
90% VS
10% VS
VIN_H
VIN_L
t
Switching times.vsd
tOFF_delay
30% VS
70% VS
dV/dt ON dV/dt OFF
Data Sheet 15 Rev. 1.01
2018-06-14
ITS4075Q-EP-D
75 mΩ Quad Channel Smart High-Side Power Switch
Power Stage
5.3 Inductive Load
5.3.1 Output Clamping
When switching OFF inductive loads with high-side switches, the voltage
V
OUT drops below ground potential,
because the inductance intends to continue driving the current. To prevent the destruction of the device by
avalanche due to high voltage drop over the power stage a voltage clamp mechanism
Z
DS(AZ) is implemented
that limits negative output voltage to a certain level (
V
S-
V
DS(AZ)). The clamping mechanism allows in addition
a fast demagnetization of inductive loads because during the phase of active clamping the power is dissipated
to a great extent rapidly inside the switch. On the other hand the power dissipated inside the switch while
switching off inductive loads can cause considerable stress to the device. Therefore the maximum allowed
energy at a given current (and by this also the inductance) is limited. In Figure 8 and Figure 9 the basic
principle of active clamping as well as simplified waveforms when switching off inductive loads are illustrated.
Figure 8 Output Clamp
Figure 9 Switching an Inductive Load Timing
ITS4075Q-EP-D
OUT
x
IN
x
V
S
Driver
Logic
GND
Bias Z
DS(AZ)
V
S
V
ÎN
I
L
L, R
L
Z
GND
V
DS
V
OUT
IN
VOUT
IL
VS
VS-VDS(AZ)
t
t
t
Switching an inductance.vsd
Data Sheet 16 Rev. 1.01
2018-06-14
ITS4075Q-EP-D
75 mΩ Quad Channel Smart High-Side Power Switch
Power Stage
5.3.2 Maximum Load Inductance
During demagnetization of inductive loads, the following energy must be dissipated by the ITS4075Q-EP-D.
This energy can be calculated by help of the following equation:
(5.1)
Following equation gets simplified under the assumption of
R
L=0Ω:
(5.2)
The energy, which may be converted into heat, is limited by the thermal design of the component. See
Figure 10 for the maximum allowed energy dissipation as a function of the load current for a singular pulse
event on one channel.
Figure 10 Maximum Energy Dissipation Single Pulse for a Single Channel;
V
S = 28 V
5.4 Inverse Current Capability
In case of inverse current, meaning a voltage
V
INV at the OUTput higher than the supply voltage
V
S, a current
I
INV will flow from output to
V
S pin via the body diode of the power transistor (please refer to Figure 11).
Channels that are active (ON-state) by the time when the inverse current condition appears will remain active
and their output stage will follow the state of the corresponding IN pin, which means that the channel can be
switched off during inverse current condition. Channels that are inactive (OFF-state) by the time when the
inverse current condition appears will remain inactive regardless of the state of the corresponding IN pin. If
during an inverse current condition the IN-pin of a channel is set from “Low” to “High” in order to activate the
channel, the output stage of the channel is kept OFF until the inverse current disappears. For all cases the
current
I
INV should not be higher than
I
L(INV). Please note that during inverse current condition the protection
functions of concerned channels are not available.
EV
DS AZ() L
RL
------
×VSVDS AZ()
–
RL
-------------------------------- 1RLIL
×
VSVDS AZ()
–
--------------------------------
–
⎝⎠
⎛⎞
ln IL
+××=
E1
2
---LI
21VS
VSVDS AZ()
–
--------------------------------
–
⎝⎠
⎛⎞
×××=
0.5 1 1.5 2 2.5 3 3.5 4
0
100
200
300
400
500
600
I
Load
[A]
EAS [mJ]
Single Channel Pulse @ 150°C
Single Channel Pulse @ 125°C
Data Sheet 17 Rev. 1.01
2018-06-14
ITS4075Q-EP-D
75 mΩ Quad Channel Smart High-Side Power Switch
Power Stage
Figure 11 Inverse Current Circuitry
Figure 12 Inverse Current event: channel in OFF-state (channel remains off for duration of inverse
current event)
ITS4075Q-EP-D
OUT
x
IN
x
Device
Logic
Gate
Driver
GND
Bias
Z
GND
Inv.
Comp
V
S
I
L(INV)
V
INV
I
L(INV)
V
IN
t
t
t
Channel
State
„ON“
„OFF“
„OFF“ „ON“
Inverse Current Event
Data Sheet 18 Rev. 1.01
2018-06-14
ITS4075Q-EP-D
75 mΩ Quad Channel Smart High-Side Power Switch
Power Stage
Figure 13 Inverse Current event: channel in ON-state (output not influenced but can be switched off)
5.5 Electrical Characteristics: Power Stage
Table 4 Electrical Characteristics: Power Stage
V
S = 8 V to 36 V,
T
j = -40°C to 150°C (unless otherwise specified).
Typical values are given at
V
S=24V,
T
j= 25°C
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
ON-state resistance per
channel (
T
j= 25°C)
R
DS(ON) ––75mΩ
I
Lx =2A
V
IN =4.5V
T
j= 25°C
P_5.5.18
ON-state resistance per
channel (
T
j= 125°C)
R
DS(ON)_125 – 120 – mΩ2)
I
Lx =2A
V
IN =4.5V
T
j= 125°C
P_5.5.19
ON-state resistance per
channel (
T
j= 150°C)
R
DS(ON)_150 – – 150 mΩ
I
Lx=2A
V
IN =4.5V
T
j= 150°C
P_5.5.1
Nominal load current
per channel
I
L(NOM)1 ––2.6A
1) 2)
T
j< 150°C P_5.5.2
Drain to source clamping
voltage
V
DS(AZ) = [
V
S-
V
OUT]
V
DS(AZ) 65 70 75 V
I
DS =5mA P_5.5.5
Output leakage current per
channel
I
L(OFF) –0.10.5µA
2)
V
IN floating
V
OUT =0V
T
j≤85°C
P_5.5.6
Output leakage current per
channel
I
L(OFF)_150 –15 µA
V
IN floating
V
OUT =0V
T
j= 150°C
P_5.5.4
Inverse current capability
I
L(INV) –2.2–A
2) 3)
V
S<
V
OUTX
t
<2min
P_5.5.7
„ON“
„OFF“
I
L(INV)
V
IN
Channel
State
t
t
t
„OFF“ „ON“ „OFF“
Inverse Current Event
Data Sheet 19 Rev. 1.01
2018-06-14
ITS4075Q-EP-D
75 mΩ Quad Channel Smart High-Side Power Switch
Power Stage
Slew rate (switch on)
30% to 70% of
V
S
Δ
V
/Δ
t
ON 0.3 0.75 1.9 V/µs
R
L=12Ω
V
S=24V
P_5.5.8
Slew rate (switch off)
70% to 30% of
V
S
-Δ
V
/Δ
t
OFF 0.3 0.75 1.9 V/µs
R
L=12Ω
V
S=24V
P_5.5.9
Turn-ON time to
V
OUT = 90%
V
S
t
ON 20 55 100 µs
R
L=12Ω
V
S=24V
P_5.5.11
Turn-OFF time to
V
OUT = 10%
V
S
t
OFF 20 55 100 µs
R
L=12Ω
V
S=24V
P_5.5.12
Turn-ON / OFF matching
t
OFF -
t
ON
Δ
t
SW -50 0 50 µs
R
L=12Ω
V
S=24V
P_5.5.13
Turn-ON time to
V
OUT = 10%
V
S
t
ON_delay –2550µs
R
L=12Ω
V
S=24V
P_5.5.14
Turn-OFF time to
V
OUT = 90%
V
S
t
OFF_delay –2550µs
R
L=12Ω
V
S=24V
P_5.5.15
1) This parameter describes the nominal load capability per channel from an electrical point of view respecting a
maximum
T
j≤150°C. Please note that depending on the individual thermal design of a real application (and a
potentially insufficient thermal budget resulting hereof) additional restrictions for
I
L(NOM) may occur for pure thermal
reasons in order not to exceed the maximum allowed junction temperature
T
j= 150°C. The latter needs to be
considered especially for cases where all four channels are operating simultaneously under high load conditions and
at high ambient temperature
T
AMB. For further details about potential derating of the nominal load current due to
thermal restrictions please refer to “Thermal Considerations” on Page 38.
2) Not subject to production test; specified by design.
3) Please note that during inverse current condition the protection features are not operational.
Table 4 Electrical Characteristics: Power Stage (cont’d)
V
S = 8 V to 36 V,
T
j = -40°C to 150°C (unless otherwise specified).
Typical values are given at
V
S=24V,
T
j= 25°C
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Data Sheet 20 Rev. 1.01
2018-06-14
ITS4075Q-EP-D
75 mΩ Quad Channel Smart High-Side Power Switch
Power Stage
5.6 Typical Performance Characteristics Power Stage
Typical Performance Characteristics
ON-State Resistance
R
DSON versus
Junction Temperature
T
j
Leakage Current per channel
I
L(OFF) versus
Junction Temperature
T
j
Output Clamp Voltage
V
DS(AZ) versus
Junction Temperature
T
j
−50 0 50 100 150
0
20
40
60
80
100
120
140
160
T
j
[°C]
R
DSON
[mΩ]
V
S
= 24 V; I
Load
= 2A
−50 0 50 100 150
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Tj [°C]
IL(OFF) [uA]
VS = 24 V
−50 0 50 100 150
65
66
67
68
69
70
71
72
73
74
75
T
j
[°C]
V
DS(AZ)
[V]
CH 1
CH 2
CH 3
CH 4
Data Sheet 21 Rev. 1.01
2018-06-14
ITS4075Q-EP-D
75 mΩ Quad Channel Smart High-Side Power Switch
Power Stage
Turn-ON time
t
ON to
V
OUT =90% versus
Junction Temperature
T
j
Turn-OFF time
t
OFF to
V
OUT =90% versus
Junction Temperature
T
j
Turn-ON delay time
t
ON_delay to
V
OUT =10% versus
Junction Temperature
T
j
Turn-OFF delay time
t
OFF_delay to
V
OUT = 10% versus
Junction Temperature
T
j
−50 0 50 100 150
0
10
20
30
40
50
60
70
80
90
100
T
j
[°C]
t
ON
[us]
V
S
= 24V
I
Load
= 0.5A
I
Load
= 1.0A
I
Load
= 2.0A
I
Load
= 2.5A
−50 0 50 100 150
0
10
20
30
40
50
60
70
80
90
100
T
j
[°C]
t
OFF
[us]
V
S
= 24V
I
Load
= 0.5A
I
Load
= 1.0A
I
Load
= 2.0A
I
Load
= 2.5A
−50 0 50 100 150
0
5
10
15
20
25
30
35
40
45
50
T
j
[°C]
t
ON_delay
[us]
V
S
= 24V
I
Load
= 0.5A
I
Load
= 1.0A
I
Load
= 2.0A
I
Load
= 2.5A
−50 0 50 100 150
0
5
10
15
20
25
30
35
40
45
50
T
j
[°C]
t
OFF_delay
[us]
V
S
= 24V
I
Load
= 0.5A
I
Load
= 1.0A
I
Load
= 2.0A
I
Load
= 2.5A
Data Sheet 22 Rev. 1.01
2018-06-14
ITS4075Q-EP-D
75 mΩ Quad Channel Smart High-Side Power Switch
Power Stage
Turn-ON time
t
ON to
V
OUT =90% versus
Load Current
I
Load
Turn-OFF time
t
OFF to
V
OUT =90% versus
Load Current
I
Load
Turn-ON delay time
t
ON_delay to
V
OUT =10% versus
Load Current
I
Load
Turn-OFF delay time
t
OFF_delay to
V
OUT = 10% versus
Load Current
I
Load
0 0.5 1 1.5 2 2.5 3
0
10
20
30
40
50
60
70
80
90
100
I
Load
[A]
t
ON
[us]
V
S
= 24 V
T
j
= −40 °C
T
j
= 25 °C
T
j
= 150 °C
0 0.5 1 1.5 2 2.5 3
0
10
20
30
40
50
60
70
80
90
100
I
Load
[A]
t
OFF
[us]
V
S
= 24 V
T
j
= −40 °C
T
j
= 25 °C
T
j
= 150 °C
0 0.5 1 1.5 2 2.5 3
0
5
10
15
20
25
30
35
40
45
50
I
Load
[A]
t
ON_delay
[us]
V
S
= 24 V
T
j
= −40 °C
T
j
= 25 °C
T
j
= 150 °C
0 0.5 1 1.5 2 2.5 3
0
5
10
15
20
25
30
35
40
45
50
I
Load
[A]
t
OFF_delay
[us]
V
S
= 24 V
T
j
= −40 °C
T
j
= 25 °C
T
j
= 150 °C
Data Sheet 23 Rev. 1.01
2018-06-14
ITS4075Q-EP-D
75 mΩ Quad Channel Smart High-Side Power Switch
Protection Functions
6 Protection Functions
The device provides integrated protection functions. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Protection functions are designed to prevent the destruction of
the ITS4075Q-EP-D due to fault conditions described in the data sheet. Please note that fault conditions are
not considered as normal operation conditions and the protection functions are neither designed for
continuous operation nor for repetitive operation.
6.1 Loss of Ground Protection
In case of loss of module ground when the load remains connected to ground, the device protects itself by
automatically turning OFF (when it was previously ON) or remains OFF, regardless of the voltage applied at the
input pins.
In an application where the inputs are directly controlled by logic levels <
V
S (e.g. by a microcontroller without
galvanic isolation), it is recommended to use input resistors 1) between the external control circuit
(microcontroller) and the ITS4075Q-EP-D to protect also the external control circuit in case of loss of device
ground.
In case of loss of module or device ground, a current (
I
OUT(GND)) can flow out of the DMOS. Figure 14 sketches
the situation.
Z
GND is recommended to be a resistor in series to a diode.
Figure 14 Loss of Ground Protection with External Components
1) Recommended value is 10 kΩ
ITS4075Q-EP-D
OUTx
INx
VS
Logic
GND
ZDS(AZ)
IOUT(GND)
ZGND
ZD(AZ)
ST
RIN
RST
+
-
Data Sheet 24 Rev. 1.01
2018-06-14
ITS4075Q-EP-D
75 mΩ Quad Channel Smart High-Side Power Switch
Protection Functions
6.2 Undervoltage Protection
If the supply voltage falls below
V
S(UV) the undervoltage protection of the device is triggered.
V
S(UV) represents
hence the minimum voltage for which the switch still can hold ON. Once the device is off
V
S(OP)_MIN represents
the lowest voltage where the device is turning on again (and thus the channels can be switched again). If the
supply voltage is below the undervoltage threshold
V
S(UV), the channels of the device are OFF (or turning OFF).
As soon as the supply voltage is recovering and exceeding the threshold of the functional supply voltage
V
S(OP)_MIN, the device is re-powering and its channels can be switched again. In addition the protection
functions as well as diagnosis become operational once
V
SOP_MIN is reached. Figure 15 sketches the
undervoltage mechanism.
Figure 15 Undervoltage Behavior
6.2.1 Overvoltage Protection
There is an integrated clamping mechanism for overvoltage protection (
Z
D(AZ)). To ensure this mechanism
operates properly in the application, the current in the Zener diode
Z
D(AZ) must be limited by a ground resistor.
Figure 16 shows a typical application to withstand overvoltage issues. In case of supply voltage higher than
V
S(AZ), the voltage across supply to ground path is clamped. As a result, the internal ground potential rises to
V
S-
V
S(AZ). Due to the ESD Zener diodes, the potential at pin INx rises almost to that potential, depending on
the impedance of the connected circuitry 1). In the case the device was ON, prior to overvoltage, the ITS4075Q-
EP-D remains ON. In case the ITS4075Q-EP-D was OFF, prior to overvoltage, the power transistor can be
activated. In case the supply voltage is above
V
S(SC) and below
V
DS(AZ), the output transistor is still operational
and follows the input. If at least one channel is in ON-state, parameters are no longer within specified range
and lifetime is reduced compared to the nominal supply voltage range. This especially impacts the short
circuit robustness, as well as the maximum energy
E
AS capability.
Z
GND is recommended to be either a resistor
(27 Ω) in series to a diode or alternatively a 150 Ω power resistor.
1) Hence, the usage of external input resistors needs to be considered
V
OUT
V
S
V
S(UV)
V
S(OP)_MIN
Data Sheet 25 Rev. 1.01
2018-06-14
ITS4075Q-EP-D
75 mΩ Quad Channel Smart High-Side Power Switch
Protection Functions
Figure 16 Overvoltage Protection with External Components
ITS4075Q-EP-D
OUT
x
IN
x
V
S
Logic
GND
Z
DS(AZ)
I
OUT
Z
GND
Z
D(AZ)
ST
RIN
RST
+
-
I
SOV
Data Sheet 26 Rev. 1.01
2018-06-14
ITS4075Q-EP-D
75 mΩ Quad Channel Smart High-Side Power Switch
Protection Functions
6.3 Reverse Polarity Protection
In case of reverse polarity, the intrinsic body diodes of the affected power DMOS channels will dissipate power.
The current flowing through the intrinsic body diode is limited externally by the load itself. But in addition the
current into the ground path and the logic pins must be limited by an external resistor to the maximum
allowed current described in Chapter 4.1. Figure 17 shows a typical application.
Z
GND resistor is used to limit
the current through the Zener protection of the device.
Z
GND is recommended to be either a resistor (~ 27 Ω) in
series to a diode or alternatively a power resistor (~ 150 Ω).
During reverse polarity no protection functions are available.
Figure 17 Reverse Polarity Protection with External Components
ITS4075Q-EP-D
OUT
x
IN
x
V
S
Logic
GND
Z
DS(AZ)
Z
GND
Z
D(AZ)
ST
R
IN
R
ST
V
DS(REV)
+
-
Microcontroller
Protection
diodes
-V
S(REV)
Data Sheet 27 Rev. 1.01
2018-06-14
ITS4075Q-EP-D
75 mΩ Quad Channel Smart High-Side Power Switch
Protection Functions
6.4 Overload Protection
In case of overload, such as high inrush current of a cold lamp filament, or short circuit to ground, the
ITS4075Q-EP-D offers a set of protection mechanisms which is illustrated in Figure 18.
6.4.1 Current Limitation
As a first step, the instantaneous power in the switch is contained within a safe range by limiting the current
to the maximum current allowed in the switch
I
L(LIM). During this time, where the current is limited to
I
L(LM), the
DMOS temperature is increasing caused by the voltage drop
V
DS over the DMOS.
Figure 18 Protection behavior of the ITS4075Q-EP-D
Overtemperature concept: Overtemperature behavior:
OvertemperatureTogglingNormal
Waveforms turn on into a short circuit: Waveforms short circuit during on state:
tt
OFF
OFF
Overloaded OUT shorted to GND
OFF
Normal
operation
ON
T
j(SC)
∆T
j(SC)
V
OUT
t
t
0
I
L(LIM)
0
Shut down by overtemperature and restart after
cooling down (thermal toggling) once the device
exceeds thermal threshold after being heated up
during current limitation state
Shut down by overtemperature and restart after
cooling down (thermal toggling) once the device
exceeds thermal threshold after being heated up
during current limitation state
V
OUT
t
V
IN
Lt
0
I
L(LIM)
0
t
OFF
OFF
ON ON
V
OUT
t
t
0
T
j
t
Tj(SC) ∆Tj(SC)
OFF
T
j
OFF cooling
down
heating
up
Device
Status
L
H
V
ST
t
H
V
IN
L
H
L
H
V
ST
t
tST(FAULT)_SC1
V
IN
L
H
L
H
V
ST
t
tST(FAULT)
tON tOFF
tON tOFF
tON tOFF
OFF
Data Sheet 28 Rev. 1.01
2018-06-14
ITS4075Q-EP-D
75 mΩ Quad Channel Smart High-Side Power Switch
Protection Functions
6.4.2 Temperature Limitation in the Power DMOS
Each channel incorporates one temperature sensor. Activation of this temperature sensor will cause an
overheated channel to switch OFF to prevent destruction. Any protective overtemperature shutdown event
triggered within a channel is switching OFF the output of the corresponding channel until the temperature
reaches an acceptable value again.
A restart functionality is implemented that is switching the channel ON again after the DMOS temperature has
sufficiently cooled down.
6.5 Electrical Characteristics: Protection Functions
Table 5 Electrical Characteristics: Protection Functions 1)
V
S = 8 V to 36 V,
T
j = -40°C to 150°C (unless otherwise specified).
Typical values are given at
V
S=24V,
T
j= 25°C
1) Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Integrated
protection functions are designed to prevent IC from destruction under fault conditions described in the data sheet.
Fault conditions are considered as “outside” normal operating range. Protection functions are designed neither for
continuous nor repetitive operation.
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Loss of Ground
Output leakage current
while GND disconnected
I
OUT(GND) –0.1–mA
2) 3)
V
S=24V
2) All pins are disconnected except
V
S and OUT.
3) Not subject to production test; specified by design.
P_6.5.1
Reverse Polarity
Drain source diode voltage
during reverse polarity
V
DS(REV) – 650 700 mV
I
L=-2A
T
j= 150°C
P_6.5.2
Overvoltage
Overvoltage protection
V
S(AZ) 65 70 75 V 4)
I
SOV =5mA
4) For practical cases it is recommended to place a resistor in the range of ≥27 Ω into the GND path to limit the GND
current associated with overvoltage events.
P_6.5.3
Overload Condition
Load current limitation
I
L(LIM) 3.3 4.1 4.9 A – P_6.5.4
Thermal shutdown
temperature
T
j(SC) 150 175 200 °C 3) –P_6.5.6
Thermal shutdown
hysteresis
Δ
T
j(SC) – 30 – K 3) –P_6.5.7
Data Sheet 29 Rev. 1.01
2018-06-14
ITS4075Q-EP-D
75 mΩ Quad Channel Smart High-Side Power Switch
Protection Functions
6.6 Typical Performance Characteristics Protection Functions
Typical Performance Characteristics
Current Limit
I
L(LIM) versus
Junction Temperature
T
j
Clamping Voltage
V
S(AZ) versus
Voltage
T
j
−50 0 50 100 150
0
1
2
3
4
5
6
T
j
[°C]
I
L(LIM)
[A]
V
DS
= 12V
−50 0 50 100 150
65
66
67
68
69
70
71
72
73
74
75
T
j
[°C]
V
S(AZ)
[V]
Data Sheet 30 Rev. 1.01
2018-06-14
ITS4075Q-EP-D
75 mΩ Quad Channel Smart High-Side Power Switch
Diagnostic Functions
7 Diagnostic Functions
For diagnosis purpose, the ITS4075Q-EP-D provides a digital signal at pin ST. This signal is called STATUS. The
STATUS pin is realized as open drain output and must be connected to an external pull-up resistor. During
normal operation the STATUS signal is logic “High” (H). During short circuit to ground or overtemperature
condition the STATUS signal is logic “Low” (L). Table 6 shows the corresponding truth table.
7.1 Electrical Characteristics: Diagnostic Functions
Table 6 Diagnostic Truth Table 1) 2)
1) Please refer to Table 7 for more details.
2) Not subject to production test; specified by design.
Device Operation INXall INi except INXOUTXall OUTi except OUTXST Comment
Normal Operation L L OFF OFF H 3) External pull
up at ST pin
3) “X” denotes status of
OUT
i according to the status of the corresponding input signals
IN
i.
H H ON ON H
H don’t care ON X H
L don’t care OFF X H
Short Circuit to GND H don’t care ON X L 3) 4)
4) Device not in specified
R
DS(ON).
Overtemperature H don’t care OFF 5)
5) Channel remains off during cooling-down phase of power stage; then channel tries to re-start.
XL
3)
Table 7 Electrical Characteristics: Diagnostic Functions
V
S = 8 V to 36 V,
T
j = -40°C to 150°C (unless otherwise specified).
Typical values are given at
V
S = 24 V,
T
j = 25°C
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Diagnostic Timing in Overload Condition
STATUS settling time for overload
detection
t
ST(FAULT) –25–µs
1)
V
S=24V;
load jump of
R
L:
12Ω-> 3.3 Ω;
Please refer to
Figure 18 for
more details
P_7.1.1
STATUS settling time for channel
start-up into existing overload 2)
t
ST(FAULT)_SC1 – 45 90 µs
V
DS ≥ 8V;
Please refer to
Figure 18 for
more details
P_7.1.9
“Low” level STATUS voltage
V
ST(L) ––0.5V
I
ST =1.6mA3) P_7.1.3
“High” level STATUS voltage
V
ST(H) 2––
4) V
V
S>
V
ST P_7.1.4
Current through STATUS pin
(Operating Range)
I
ST ––1.6mA
V
ST <0.5V P_7.1.5
Data Sheet 31 Rev. 1.01
2018-06-14
ITS4075Q-EP-D
75 mΩ Quad Channel Smart High-Side Power Switch
Diagnostic Functions
7.2 Channel Fault Detection
The ITS4075Q-EP-D is equipped with an intelligent channel fault detection system, which allows with the aid
of a microcontroller to identify and communicate the channel on which the fault occurs.
During normal operation the STATUS pin is kept “High” by the external pull-up resistor as shown in Table 6.
If - in case of a fault - the application requires the information on which of the channels the fault occurs when
a “Low” STATUS is flagged, then the microcontroller can be programmed according to the sequence depicted
as an example in Figure 19. The figure shows a case where three channels are active (these are channels 1, 2
and 4). Channel 3 in this example is not switched ON. During normal operation of channels 1, 2 and 4 the
STATUS signal is “High”. If a fault occurs, e.g. at channel 4, the STATUS signal goes “Low” to flag an error to the
microcontroller. The microcontroller, in order to identify on which channel the fault occurs, must send a
“Low” pulse sequentially to the input of each active channel, that is channels 1, 2 and 4 in this case. These
pulses are shown in Figure 19 and their width is denominated
T
x. The pulse width
T
x should be between 3 µs
up to 6 µs in order to make sure that the output does not react to this short inversion input level. The STATUS
signal will go to “High” for a short period of time
T
monly after the channel on which the fault occurs gets a
“Low” pulse from the microcontroller, which in this case is after channel 4 receives a “Low” pulse for a time
T
x.
In this way, by reading back whether an inversion of the STATUS flag within
T
m occurs, the microcontroller is
able to detect on which channel the fault occurs. Once the microcontroller receives this information it can
start to switch OFF the channel on which the fault occurs (channel 4 in this case) via the corresponding input
pin. For the delay time
T
D between
T
x going “Low” and
T
m going “High” a value of 8 µs needs to be taken into
account.
Channel fault detection
interrogation time
(Sequential Pulse Width)
T
x3–6µs
V
ST <0.5V5) P_7.1.2
STATUS signal “High” valid
window after
T
x on fault affected
channel
T
m40 80 150 µs 5) –P_7.1.6
Minimum delay between
subsequent
T
x interrogation
windows.
T
X-2-X 200 – – µs 1) –P_7.1.8
Maximum delay time between
T
x
(“High” to “Low”) on fault
affected channel and STATUS
“High” signal
T
m
T
D–8–µs
1) –P_7.1.7
1) Not subject to production test; specified by design.
2) This parameter describes the status settling time when a channel is switched on into an already existing overload
condition. This parameter is referenced to the edge of the input pin IN that switches the channel into overload.
3) Levels referenced to device ground.
4) Depends on pull-up circuit that is used within application; maximum ratings of STATUS pin need to be respected.
5) Please refer to “Channel Fault Detection” on Page 31 for more details.
Table 7 Electrical Characteristics: Diagnostic Functions (cont’d)
V
S = 8 V to 36 V,
T
j = -40°C to 150°C (unless otherwise specified).
Typical values are given at
V
S = 24 V,
T
j = 25°C
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Data Sheet 32 Rev. 1.01
2018-06-14
ITS4075Q-EP-D
75 mΩ Quad Channel Smart High-Side Power Switch
Diagnostic Functions
Figure 19 Channel Fault Detection Timing Diagram
IN1
IN2
IN3
IN4
STATUS
Fault at channel 4
TX
TX
TX
t
Normal Operation Normal Operation
TD
TDTD
??
TX-2-X TX-2-X
TmTmTm
Fault
Channel
An inverted ST-pin signal following a T
X
interrogation pulse within a time window T
m
on a given channel confirms a fault channel.
A non-inverted ST-pin signal after a T
X
pulse (dashed lines) indicate that corresponding channel is not in fault condition.
Data Sheet 33 Rev. 1.01
2018-06-14
ITS4075Q-EP-D
75 mΩ Quad Channel Smart High-Side Power Switch
Diagnostic Functions
7.3 Typical Performance Characteristics Diagnostic Functions
Typical Performance Characteristics
Status Settling Time
t
ST(FAULT) versus
Junction Temperature
T
j (overload during ON)
Status Settling Time
t
ST(Fault)_SC1 versus
Junction Temperature
T
j (switch on into overload)
Maximum Delay Time
T
D (
T
X ‘H->L’ to ST ‘L->H’) vs.
Junction Temperature
T
j
ST “High” Valid window (after
T
X)
T
M versus
Junction Temperature
T
j
−50 0 50 100 150
0
5
10
15
20
25
30
35
40
45
50
T
j
[°C]
t
ST(Fault)
[us]
V
S
= 24V
typ. t
ST(Fault)
for R
L
: 12 Ω −> 3.3 Ω
typ. t
ST(Fault)
for R
L
: 12 Ω −> 0 Ω
−50 0 50 100 150
0
10
20
30
40
50
60
70
80
T
j
[°C]
t
ST(Fault)_SC1
[us]
V
S
= 24V
V
DS
= 8V
t
ST(Fault)_SC1
−50 0 50 100 150
0
1
2
3
4
5
6
7
8
9
10
T
j
[°C]
T
D
[us]
V
S
= 24V
T
D
−50 0 50 100 150
0
10
20
30
40
50
60
70
80
90
100
T
j
[°C]
T
M
[us]
V
S
= 24V
T
M
Data Sheet 34 Rev. 1.01
2018-06-14
ITS4075Q-EP-D
75 mΩ Quad Channel Smart High-Side Power Switch
Input Pins
8 Input Pins
8.1 Input Circuitry
The input circuitry is compatible with 3.3V and 5V microcontrollers as well as input levels up to
V
S1). The
concept of the input pin is to react to voltage thresholds which are referenced to device ground. An
implemented Schmitt trigger avoids any undefined state if the voltage on the input pin is slowly increasing or
decreasing. The output is either OFF or ON but cannot be in a linear or undefined state. Figure 20 shows the
electrical equivalent input circuitry. In case a channel is permanently not needed, the corresponding input pin
shall not be left floating but tied with a serial resistor to device ground (not module ground). The
recommended value for the serial resistor is 2.2 kΩ.
Figure 20 Input Pin Circuitry
8.2 Input Pin Voltage
The input pin IN uses a comparator with hysteresis. Switching “ON / OFF” of the channels takes place in a
defined region, set by the thresholds
V
IN(L),max and
V
IN(H),min. The exact values where the “ON” and “OFF” take
place depend on the process, as well as on the temperature. To avoid cross talk and parasitic turn-ON or turn-
OFF, a hysteresis is implemented. This ensures an improved immunity to noise.
1)
V
IN must not exceed
V
S. The relation
V
IN ≤
V
S must always be fulfilled.
ITS4075Q-EP-D
OUT
x
IN
x
Device
Logic
Gate
Driver
GND
Bias
Z
GND
Inv.
Comp
V
S
V
IH
Data Sheet 35 Rev. 1.01
2018-06-14
ITS4075Q-EP-D
75 mΩ Quad Channel Smart High-Side Power Switch
Input Pins
8.3 Electrical Characteristics: Input Pins
Table 8 Electrical Characteristics: Input Pins
V
S = 8 V to 36 V,
T
j = -40°C to 150°C (unless otherwise specified).
Typical values are given at
V
S = 24 V,
T
j = 25°C
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Input Pins Characteristics
“Low” level input voltage
range
V
IN(L) -0.3 – 0.8 V – 1)
1) Levels referenced to device ground.
P_8.3.1
“High” level input voltage
range
V
IN(H) 2 – 36 V
V
S>
V
IN 1) P_8.3.2
Input voltage hysteresis
V
IN(HYS) – 250 – mV – 2)
2) Not subject to production test; specified by design.
P_8.3.3
“Low” level input current
I
IN(L) –3570µA
V
IN =0.8V P_8.3.4
“High” level input current
I
IN(H) –4370µA
V
IN =24V P_8.3.5
Data Sheet 36 Rev. 1.01
2018-06-14
ITS4075Q-EP-D
75 mΩ Quad Channel Smart High-Side Power Switch
Input Pins
8.4 Typical Performance Characteristics Input Pins
Typical Performance Characteristics
Input Voltage thresholds
V
IN(L)
V
IN(H) versus
Junction Temperature
T
j
Input Voltage hysteresis
V
IN(HYS) versus
Junction Temperature
T
j
Input Pin Current
I
IN(H) versus
Supply Voltage
V
S
Input Pin Current
I
IN(H) versus
Junction Temperature
T
j
0 50 100 150
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
T
j
[°C]
V
IN
[V]
V
S
= 24V
V
IN(H)
V
IN(L)
0 50 100 150
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
T
j
[°C]
V
IN
[V]
V
S
= 24V
V
IN(HYS)
0 5 10 15 20 25
0
10
20
30
40
50
60
70
V
IN
[V]
I
IN
[uA]
V
S
= 28.8V
T
j
−40°C
T
j
25°C
T
j
150°C
0 50 100 150
0
10
20
30
40
50
60
70
T
j
[°C]
I
IN
[uA]
V
IN
= 24V
Data Sheet 37 Rev. 1.01
2018-06-14
ITS4075Q-EP-D
75 mΩ Quad Channel Smart High-Side Power Switch
Application Information
9 Application Information
9.1 Application Diagram
Note: This is a very simplified example of an application circuit. The function must be verified in the real
application.
Figure 21 Application Diagram with ITS4075Q-EP-D
In Figure 21 above a simplified application diagram is shown where the inputs are galvanically isolated from
V
S with optocouplers. Thanks to the fact that the input pins are 24 V capable they can be directly connected to
the optocouplers. Reverse polarity protection can be achieved with external components. In this context it
should be noted that input pins of channels which are permanently unused have to be tied with 2.2 kΩ
resistance to device ground. In addition the TM-pin must be always be tied with a serial resistor to device
ground in order to protect the pin in case of reverse polarity. The recommended value for this serial resistor is
also 2.2 kΩ. For applications where no galvanic isolation is present between the external control circuitry (e.g
microcontroller) and the input pins of the ITS4075Q-EP-D serial input resistors need to be placed in order to
ITS4075Q-EP-D
IN1
VS
GND
ST
Microcontroller
e.g. XMC4xxx
IN2
IN3
IN4
OUT1
OUT2
OUT3
OUT4
I/O
I/O
I/O
I/O
I/O
GND
LOAD 1
LOAD 2
V
DD
Linear
Voltage Regulator
e.g. IFX1763
VOUT VIN
C
OUT
LOAD 3
LOAD 4
V
DD
External
components for
Surge Immunity
V
S
Z
GND
External components for reverse polarity protection and overvoltage
pulses. Recommended setup for ZGND is a diode for reverse polarity in
series with a resistor of ~27Ω to limit GND current during overvoltage
spikes.
TM
2.2 kΩ
30 kΩ
Data Sheet 38 Rev. 1.01
2018-06-14
ITS4075Q-EP-D
75 mΩ Quad Channel Smart High-Side Power Switch
Application Information
protect the external control circuitry and the input structures of the ITS4075Q-EP-D under fault conditions
(like e.g. reverse polarity, loss of ground or overvoltage). For further details please also refer to the
corresponding sections in Chapter 6. The recommended value for such serial input resistors is 10 kΩ however
application specific optimized values may also depend on the individual application conditions as well as the
applied external control circuitry / microcontroller.
9.2 Thermal Considerations
If the cooling possibilities within the application are not sufficient to sink the heat of the dissipated power the
junction temperature
T
j of the device may exceed its maximum specified rating of 150°C and eventually trigger
a thermal shutdown of the overheated channels to protect the device from destruction. Such thermal
shutdown events may occur e.g. if one or more channels are operated in overload conditions that are causing
the current limitation functionality to become active. If the current limitation of a channel becomes active the
power dissipation will rise rapidly and in many cases lead to thermal shutdown events of the corresponding
channels within short periods of time.
But also under nominal load conditions the power dissipation can become too high inside an application if it
is applied at high environmental temperature
T
AMB and if at the same time the cooling capability of the PCB is
not sufficient. In general the cooling capability of an IC on a PCB within an application can be described for
static cases by its thermal resistance from junction-to-ambient
R
thJA. The thermal resistance
R
thJA can be
improved by adding cooling area on top- or bottom layer of the PCB or by adding inner layers that are
connected to the
V
S layer with thermal vias. Thermal vias show the best efficiency for heat distribution if
directly placed underneath the exposed pad of the ITS4075Q-EP-D. The achievable values for
R
thJA will differ
from application to application. As reference simulation values of
R
thJA for a set of standardized JEDEC cases
are provided in Chapter 4.4 “Thermal Resistance” on Page 12. Actual values in real applications naturally
can be lower or higher.
For cases where the achievable thermal resistance
R
thJA and the hereof resulting thermal budget within an
application is not sufficient for a given ambient temperature
T
AMB there is no other choice than to lower the
load current to smaller numbers than the allowed maximum nominal current of 2.6 A. Figure 22 illustrates
how the derating of the nominal current due to excessive power dissipation can look like as a function of
achievable
R
thJA and given
T
AMB. The graphs show how the thermal budget with its limiting condition
T
j= 150°C
can be shared between the influencing parameters
T
AMB,
R
thJA,
I
Load depending on the number of active
channels
n
CH. Next to the standardized JEDEC cases mentioned above also an arbitrarily chosen value of
R
thJA = 25 K/W as additional reference for a highly optimized PCB solution is included in the graphs.
The calculation of the thermal budget displayed in the graphs follows simple rules as given in the equations
below. It should be noted that the calculation is restricted to static cases where the resulting
T
AMB and
T
j have
reached a stable equilibrium.
(9.1)
(9.2)
T
j
= T
AMB
+ R
thJA
× P
DISS
P
DISS
= I
Load
2 × R
DS(ON)
× n
CH
+ V
S
× I
GND
Data Sheet 39 Rev. 1.01
2018-06-14
ITS4075Q-EP-D
75 mΩ Quad Channel Smart High-Side Power Switch
Application Information
Figure 22 Possible thermal derating of nominal current due to insufficient cooling capability of PCB
20 30 40 50 60 70 80 90 100
0
0.5
1
1.5
2
2.5
TAMB [°C]
Inom,max [A]
1 channel active
(VS = 28V)
RthJA = 25 K/W
RthJA = 33 K/W
RthJA = 40 K/W
RthJA = 48 K/W
RthJA =102 K/W
20 30 40 50 60 70 80 90 100
0
0.5
1
1.5
2
2.5
TAMB [°C]
Inom,max [A]
2 channels active
(VS = 28V)
RthJA = 25 K/W
RthJA = 33 K/W
RthJA = 40 K/W
RthJA = 48 K/W
RthJA =102 K/W
20 30 40 50 60 70 80 90 100
0
0.5
1
1.5
2
2.5
TAMB [°C]
Inom,max [A]
3 channels active
(VS = 28V)
RthJA = 25 K/W
RthJA = 33 K/W
RthJA = 40 K/W
RthJA = 48 K/W
RthJA =102 K/W
20 30 40 50 60 70 80 90 100
0
0.5
1
1.5
2
2.5
TAMB [°C]
Inom,max [A]
4 channels active
(VS = 28V)
RthJA = 25 K/W
RthJA = 33 K/W
RthJA = 40 K/W
RthJA = 48 K/W
RthJA =102 K/W
Data Sheet 40 Rev. 1.01
2018-06-14
ITS4075Q-EP-D
75 mΩ Quad Channel Smart High-Side Power Switch
Package Outlines
10 Package Outlines
Figure 23 PG-TSDSO-14 (Plastic Dual Small Outline Package) (RoHS-Compliant)
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant
with government regulations the device is available as a green product. Green products are RoHS-Compliant
(i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
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For further information on alternative packages, please visit our website:
http://www.infineon.com/packages.Dimensions in mm
Data Sheet 41 Rev. 1.01
2018-06-14
ITS4075Q-EP-D
75 mΩ Quad Channel Smart High-Side Power Switch
Revision History
11 Revision History
Revision Date Changes
1.01 2018-06-14 Data Sheet Rev. 1.01
Editorial changes
1.0 2018-05-22 Data Sheet (Initial Release)
IMPORTANT NOTICE
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics ("Beschaffenheitsgarantie").
With respect to any examples, hints or any typical
values stated herein and/or any information regarding
the application of the product, Infineon Technologies
hereby disclaims any and all warranties and liabilities
of any kind, including without limitation warranties of
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In addition, any information given in this document is
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The data contained in this document is exclusively
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information given in this document with respect to
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For further information on technology, delivery terms
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Edition 2018-06-14
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2018 Infineon Technologies AG.
All Rights Reserved.
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