Industrial PROFETTM ITS4075Q-EP-D 75 m Quad Channel Smart Hig h-Side Power Swi tc h 1 Overview Features * Quad channel Smart High-Side Power Switch with integrated protection and diagnosis * Maximum RDS(ON) 75 m per channel at Tj = 25C * High output current capability: nominal current up to 2.6 A * Low and accurate current limitation: 4.1 A ( 20 %) * Extended supply voltage range up to 45 V * All control inputs 24 V capable and support direct interface to optocouplers * All control inputs 3.3 V and 5 V logic level compatible * 4 kV electrostatic discharge protection (ESD) * Optimized electromagnetic compatibility * Very small, thermally enhanced TSDSO-14 package * Device robustness validated by extended qualification according to JEDEC standard "JESD47J" * Green product (RoHS compliant) Potential applications * Digital output modules (PLC applications, factory automation) * Industrial peripheral switches and power distribution * Switching resistive, inductive and capacitive loads in harsh industrial environments * Replacement for electromechanical relays, fuses and discrete circuits * Most suitable for loads that require a precise current limit Product validation Qualified for industrial applications according to the relevant tests of JEDEC JESD47J. Data Sheet www.infineon.com/industrial-profet 1 Rev. 1.01 2018-06-14 ITS4075Q-EP-D 75 m Quad Channel Smart High-Side Power Switch Overview Description The ITS4075Q-EP-D is a 75 m Quad Channel Smart High-Side Power Switch providing integrated protection functions and a diagnosis feedback. With four channels capable of currents of more than 2 A each, very low typical RDS(ON) values of 120 m at Tj = 125C and the small PG-TSDSO-14 exposed pad package it combines high current capability with minimum space requirements. The exposed pad of the thermally enhanced PGTSDSO-14 package allows a very efficient heat transfer from the device to inner layers of the PCB by means of thermal vias. The power transistors are built by N-channel vertical power MOSFETs (DMOS) with charge pump. The ITS4075Q-EP-D is specifically designed to switch resistive, inductive or capacitive loads in harsh industrial environments. The ITS4075Q-EP-D is equipped with essential protection features that make it extremely robust. Diagnostic information can be read out via the STATUS output (ST). The four channel device can be controlled with four separate input pins. Due to their high voltage capability the input pins can be directly interfaced to optocouplers without additional external components. Diagnostic Functions * Short circuit to ground (overload) indication * Overtemperature switch off indication * Stable diagnostic signal during short circuit and overtemperature shutdown * Intelligent channel fault detection system Protection Functions * Stable behavior during undervoltage * Overtemperature protection with restart after cooling down phase * Overload- and short circuit protection * Reverse polarity / inverse current protection with external components * Overvoltage protection with external components * Loss of ground protection The qualification of this product is based on JEDEC JESD47J and may reference existing qualification results of similar products. Such referring is justified by the structural similarity of the products. The product is not qualified and manufactured according to the requirements of Infineon Technologies with regard to automotive and/or transportation applications. Infineon Technologies administrates a comprehensive quality management system according to the latest version of the ISO9001 and IATF 16949. The most updated certificates of the ISO9001 www.infineon.com/cms/en/product/technology/quality/ and IATF 16949 Type Package Marking ITS4075Q-EP-D PG-TSDSO-14 ITS4075Q Data Sheet 2 are available at Rev. 1.01 2018-06-14 ITS4075Q-EP-D 75 m Quad Channel Smart High-Side Power Switch Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Potential applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Product validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 3.1 3.2 3.3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignment PG-TSDSO-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Definitions and Functions PG-TSDSO-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage and Current Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4.1 4.2 4.3 4.4 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Typical Performance Characteristics Operating Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 5.1 5.2 5.3 5.3.1 5.3.2 5.4 5.5 5.6 Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output ON-state Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Turn ON/OFF Characteristics with Resistive Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inductive Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum Load Inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Inverse Current Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics: Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Performance Characteristics Power Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 14 15 15 16 16 18 20 6 6.1 6.2 6.2.1 6.3 6.4 6.4.1 6.4.2 6.5 6.6 Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loss of Ground Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Undervoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reverse Polarity Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Limitation in the Power DMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics: Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Performance Characteristics Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 23 24 24 26 27 27 28 28 29 7 7.1 7.2 7.3 Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics: Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Channel Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Performance Characteristics Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 30 31 33 8 8.1 8.2 Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Input Pin Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Data Sheet 3 6 6 6 7 Rev. 1.01 2018-06-14 ITS4075Q-EP-D 75 m Quad Channel Smart High-Side Power Switch 8.3 8.4 Electrical Characteristics: Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Typical Performance Characteristics Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9 9.1 9.2 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 10 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 11 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Data Sheet 4 Rev. 1.01 2018-06-14 ITS4075Q-EP-D 75 m Quad Channel Smart High-Side Power Switch Block Diagram 2 Block Diagram ITS4075Q-EP-D VS Voltage Sensor Bias IN1 3 Over Temperature Gate control & Charge Pump Driver Logic ESD Protection Over Current Switch Limit Clamp for Inductive Loads 14 OUT1 12 OUT2 10 OUT3 8 OUT4 Channel 1 VS IN2 4 ST 5 IN3 6 Control and Protection Circuitry Equivalent to Channel 1 Channel 2 VS Control and Protection Circuitry Equivalent to Channel 1 Channel 3 VS IN4 7 Control and Protection Circuitry Equivalent to Channel 1 Channel 4 PG-TSDSO-14 2 GND Figure 1 Data Sheet Block Diagram: ITS4075Q-EP-D 5 Rev. 1.01 2018-06-14 ITS4075Q-EP-D 75 m Quad Channel Smart High-Side Power Switch Pin Configuration 3 Pin Configuration 3.1 Pin Assignment PG-TSDSO-14 TM 1 14 OUT1 GND 2 13 N.C. IN1 3 12 OUT2 IN2 4 11 N.C. ST 5 10 OUT3 IN3 6 9 N.C. IN4 7 8 OUT4 Figure 2 Pin Configuration PG-TSDSO-14 3.2 Pin Definitions and Functions PG-TSDSO-14 Pin Symbol Function 1 TM Test Mode Entry; must be connected to device GND (pin 2) via resistor 1) 2 GND Ground pin 3 IN1 INput channel 1; Input signal for channel 1 activation, Active "High" 4 IN2 INput channel 2; Input signal for channel 2 activation, Active "High" 5 ST STatus Feedback; Active "Low", connect with external pull-up resistor to "High" 6 IN3 INput channel 3; Input signal for channel 3 activation, Active "High" 7 IN4 INput channel 4; Input signal for channel 4 activation, Active "High" 8 OUT4 OUTput 4; Protected high side power output channel 4 10 OUT3 OUTput 3; Protected high side power output channel 3 12 OUT2 OUTput 2; Protected high side power output channel 2 14 OUT1 OUTput 1; Protected high side power output channel 1 9,11,13 N.C. Not Connected Exposed Pad VS Voltage Supply 1) To ensure proper functionality of the device the TM pin must be connected to device ground. In order to protect the pin furthermore in case of reverse polarity conditions or ground shifts the TM pin needs to be connected with a serial resistor to device ground. The recommended value for this resistor is 2.2 k. Data Sheet 6 Rev. 1.01 2018-06-14 ITS4075Q-EP-D 75 m Quad Channel Smart High-Side Power Switch Pin Configuration 3.3 Voltage and Current Definitions Figure 3 shows all terms used in this data sheet, with associated convention for positive values. IIN1 OUT1 IN2 OUT2 IOUT1 IOUT2 VDS4 IIN2 IN1 VDS3 VS VDS2 VDS1 IS IN4 OUT 4 VIN4 GND IGND Figure 3 Data Sheet IOUT3 IOUT4 VOUT4 OUT 3 VIN3 VST IIN4 IN3 VOUT3 VIN2 IIN3 ITS4075Q-EP-D VOUT2 ST VOUT1 VIN1 VS IST Voltage and Current Definitions 7 Rev. 1.01 2018-06-14 ITS4075Q-EP-D 75 m Quad Channel Smart High-Side Power Switch General Product Characteristics 4 General Product Characteristics 4.1 Absolute Maximum Ratings Table 1 Absolute Maximum Ratings 1) Tj = -40C to 150C, positive current flowing into pin; (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number V - P_4.1.1 Min. Typ. Max. Supply Voltages Supply voltage VS -0.3 - 45 Reverse polarity voltage -VS(REV) 0 - 28 V 2) Supply voltage for short circuit protection VS(SC) 0 - 36 V - P_4.1.4 Voltage at INPUT pins VIN -0.3 - 45 V VS > VIN P_4.1.5 Current through INPUT pins IIN -2 2 mA - P_4.1.6 Voltage at ST pin VST -0.3 - 45 V VS > VST P_4.1.7 Current through ST pin IST -2 - 2 mA - P_4.1.8 Power dissipation (DC) PTOT - - 1.9 W 3) TA = 85C Tj < 150C P_4.1.10 Maximum energy dissipation Single pulse (one channel) EAS - - 60 mJ IL = 2 A Tj = 150C VS = 28 V P_4.1.11 Voltage at power transistor VDS - - 65 V - P_4.1.12 Current through ground pin I GND -20 - 20 mA - P_4.1.13 Temporary reverse current through ground pin to VS I GND -200 - - mA t < 2 min P_4.1.21 Junction temperature Tj -40 - 150 C - P_4.1.14 Storage temperature TSTG -55 - 150 C - P_4.1.15 - 2 kV HBM4) P_4.1.16 kV 4) P_4.1.17 t < 2 min TA = 25C RL 25 ZGND = 150 Power Resistor P_4.1.3 Input Pins - STATUS Pin Power Stage Currents Temperatures ESD Susceptibility ESD susceptibility (all pins) VESD_HBM -2 ESD susceptibility OUT Pin vs. VESD_HBM -4 GND and VS connected Data Sheet - 4 8 HBM Rev. 1.01 2018-06-14 ITS4075Q-EP-D 75 m Quad Channel Smart High-Side Power Switch General Product Characteristics Table 1 Absolute Maximum Ratings 1) (cont'd) Tj = -40C to 150C, positive current flowing into pin; (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. ESD susceptibility ESD susceptibility pin (corner pins) VESD_CDM -500 - VESD_CDM -750 - 500 750 V CDM5) P_4.1.18 V 5) P_4.1.19 CDM 1) Not subject to production test; specified by design. 2) Reverse polarity protection can only be achieved in combination with external components: to limit the current through the GND-path a 150 power resistor needs to be placed between GND-pin and ground. An alternative solution is to use a reverse current diode in the GND-path to realize reverse polarity protection. In this case placing a resistor in the range of 27 in series to the diode is recommended to improve at the same time the overvoltage capability in case of overvoltage pulses on VS. 3) This parameter serves as reference for the thermal budget: it illustrates the power dissipation that can be handled by the device in an application under the given boundary conditions before exceeding the maximum rating of Tj when assuming a RthJA value for a thermally well dimensioned PCB connection like given in the JEDEC case P_4.3.3 in Chapter 4.4. As RthJA depends strongly on the applied PCB and layout of any individual application the actual achievable values of PTOT can either be lower or higher depending on the given application. 4) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS-001(1.5 k, 100 pF). 5) ESD susceptibility, Charged Device Model "CDM" JEDEC JESD22-C101. Notes 1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as "outside" normal operating range. Protection functions are not designed for continuous repetitive operation. Data Sheet 9 Rev. 1.01 2018-06-14 ITS4075Q-EP-D 75 m Quad Channel Smart High-Side Power Switch General Product Characteristics 4.2 Functional Range Table 2 Functional Range Tj = -40C to 150C; (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Min. Typ. Max. Number Nominal operating voltage VS(NOM) 8 24 36 V VS > VIN P_4.2.1 Extended operating voltage VS(EOP) 5 - 45 V 1) VS > VIN IOUT = 2 A VDS < 0.5 V P_4.2.2 Minimum functional supply voltage during power-up VS(OP)_MIN - 4.3 5 V VS > VIN IOUT = 0 A to VDS < 0.5 V (VS rising; P_4.2.3 powering up) Undervoltage shutdown VS(UV) 3 3.5 4.1 V VS > VIN from VDS < 0.5 V to IOUT = 0 A (VS dropping from functional range) P_4.2.4 Undervoltage shutdown hysteresis VS(UV)_HYS - 850 - mV 1) P_4.2.5 Operating current One channel active IGND_1 - 2 3 mA VS = VIN = 24 V Device in RDS(ON) P_4.2.6 Operating current All channels active IGND_4 - 5.2 7 mA VS = VIN = 24 V Device in RDS(ON) P_4.2.9 Junction Temperature Tj -40 - 150 C - P_4.2.8 - 1) Not subject to production test; specified by design. Note: Data Sheet Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table. 10 Rev. 1.01 2018-06-14 ITS4075Q-EP-D 75 m Quad Channel Smart High-Side Power Switch General Product Characteristics 4.3 Typical Performance Characteristics Operating Current Typical Performance Characteristics Operating Current IGND versus Junction Temperature Tj Operating Current IGND versus Supply VoltageVS 7 7 1 channel active 2 channels active 3 channels active 4 channels active VS = 24 V 6 5 5 4 4 IGND [mA] IGND [mA] 6 3 3 2 2 1 1 0 -50 Data Sheet 0 50 Tj [C] 100 1 channel active 2 channels active 3 channels active 4 channels active Tj = 25 C 0 150 0 10 20 30 40 VS [V] 11 Rev. 1.01 2018-06-14 ITS4075Q-EP-D 75 m Quad Channel Smart High-Side Power Switch General Product Characteristics 4.4 Thermal Resistance Table 3 Thermal Resistance 1) Parameter Symbol Values Unit Note or Number Test Condition Min. Typ. Max. Junction to exposed pad soldering point RthJC - 1 - K/W - P_4.3.1 - P_4.3.3 Junction to ambient All channels active RthJA_2s2pvia - 33 - K/W 2) Junction to ambient All channels active RthJA_1s0p - 102 - K/W 3) - P_4.3.4 Junction to ambient All channels active RthJA_1s0p_300mm - 48 - K/W 4) - P_4.3.5 Junction to ambient All channels active RthJA_1s0p_600mm - 40 - K/W 5) - P_4.3.6 1) Not subject to production test; specified by design. 2) Specified RthJA value is according to JEDEC JESD51-2,-5,-7 at natural convection on FR4 2s2p board; the product (chip + package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70 m Cu, 2 x 35 m Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer. 3) Specified RthJA value is according to JEDEC JESD51-3 at natural convection on FR4 1s0p board, footprint; The product (chip + package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 1 x 70 m Cu. 4) Specified RthJA value is according to JEDEC JESD51-3 at natural convection on FR4 1s0p board, 300 mm; The product (chip + package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 1 x 70 m Cu. 5) Specified RthJA value is according to JEDEC JESD51-3 at natural convection on FR4 1s0p board, 600 mm; The product (chip + package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 1 x 70 m Cu. 1000 100 Thermal Impedance (one channel active; PDISSIPATION = 0.81W) ZtH-JA [K/W] 10 1 0,1 Rth-JA (footprint only) 0,01 Rth-JA (1s0p_300mm) 0,001 Rth-JA (1s0p_600mm) 0,0001 0,00001 1,00E-09 Rth-JA (2s2p-via) 1,00E-07 1,00E-05 1,00E-03 1,00E-01 time [s] Figure 4 Data Sheet Thermal Impedance (short time scale; one channel active) 12 Rev. 1.01 2018-06-14 ITS4075Q-EP-D 75 m Quad Channel Smart High-Side Power Switch General Product Characteristics 140 120 ZtH-JA [K/W] 100 Thermal Impedance (one channel active; PDISSIPATION = 0.81W) Rth-JA (footprint only) Rth-JA (1s0p_300mm) 80 60 Rth-JA (1s0p_600mm) Rth-JA (2s2p-via) 40 20 0 1,00E-05 1,00E-03 1,00E-01 1,00E+01 1,00E+03 time [s] Figure 5 Data Sheet Thermal Impedance (long time scale; one channel active) 13 Rev. 1.01 2018-06-14 ITS4075Q-EP-D 75 m Quad Channel Smart High-Side Power Switch Power Stage 5 Power Stage The power stages are built using an N-channel vertical power MOSFET (DMOS) with charge pump. 5.1 Output ON-state Resistance The ON-state resistance RDS(ON) of the power stage depends on supply voltage as well as on junction temperature Tj. Figure 6 shows the influence of temperature on the typical ON-state resistance. The behavior of the power stage in reverse polarity condition is described in Chapter 6.3. 160 140 120 RDSON [m] 100 80 60 40 20 0 -50 0 50 Tj [C] 100 Figure 6 Typical ON-state Resistance 5.2 Turn ON/OFF Characteristics with Resistive Load 150 A "High" signal at the input pin (see Chapter 8) causes the power DMOS to switch ON with a dedicated slope, which is optimized in terms of EMC emission. Figure 7 shows the typical timing when switching a resistive load. IN VIN_H VIN_L t VOUT dV/dt ON dV/dt t ON 90% VS tOFF_delay 70% VS 30% VS 10% VS OFF tON_delay tOFF t Switching times.vsd Figure 7 Data Sheet Switching a Resistive Load Timing 14 Rev. 1.01 2018-06-14 ITS4075Q-EP-D 75 m Quad Channel Smart High-Side Power Switch Power Stage 5.3 Inductive Load 5.3.1 Output Clamping When switching OFF inductive loads with high-side switches, the voltage VOUT drops below ground potential, because the inductance intends to continue driving the current. To prevent the destruction of the device by avalanche due to high voltage drop over the power stage a voltage clamp mechanism ZDS(AZ) is implemented that limits negative output voltage to a certain level (VS - VDS(AZ)). The clamping mechanism allows in addition a fast demagnetization of inductive loads because during the phase of active clamping the power is dissipated to a great extent rapidly inside the switch. On the other hand the power dissipated inside the switch while switching off inductive loads can cause considerable stress to the device. Therefore the maximum allowed energy at a given current (and by this also the inductance) is limited. In Figure 8 and Figure 9 the basic principle of active clamping as well as simplified waveforms when switching off inductive loads are illustrated. ITS4075Q-EP-D VS VS VDS Bias ZDS(AZ) Driver Logic INx OUTx IL L, RL VIN GND VOUT ZGND Figure 8 Output Clamp IN t VOUT VS t VS-VDS(AZ) IL t Switching an inductance.vsd Figure 9 Data Sheet Switching an Inductive Load Timing 15 Rev. 1.01 2018-06-14 ITS4075Q-EP-D 75 m Quad Channel Smart High-Side Power Switch Power Stage 5.3.2 Maximum Load Inductance During demagnetization of inductive loads, the following energy must be dissipated by the ITS4075Q-EP-D. This energy can be calculated by help of the following equation: V S - V DS ( AZ ) RL x IL L E = V DS ( AZ ) x ------ x -------------------------------x ln 1 - -------------------------------+ IL RL RL V S - V DS ( AZ ) (5.1) Following equation gets simplified under the assumption of RL = 0 : VS 2 1 E = --- x L x I x 1 - -------------------------------2 V S - V DS ( AZ ) (5.2) The energy, which may be converted into heat, is limited by the thermal design of the component. See Figure 10 for the maximum allowed energy dissipation as a function of the load current for a singular pulse event on one channel. 600 Single Channel Pulse @ 150C Single Channel Pulse @ 125C 500 EAS [mJ] 400 300 200 100 0 0.5 1 1.5 2 2.5 3 3.5 4 ILoad [A] Figure 10 Maximum Energy Dissipation Single Pulse for a Single Channel; VS = 28 V 5.4 Inverse Current Capability In case of inverse current, meaning a voltage VINV at the OUTput higher than the supply voltage VS, a current IINV will flow from output to VS pin via the body diode of the power transistor (please refer to Figure 11). Channels that are active (ON-state) by the time when the inverse current condition appears will remain active and their output stage will follow the state of the corresponding IN pin, which means that the channel can be switched off during inverse current condition. Channels that are inactive (OFF-state) by the time when the inverse current condition appears will remain inactive regardless of the state of the corresponding IN pin. If during an inverse current condition the IN-pin of a channel is set from "Low" to "High" in order to activate the channel, the output stage of the channel is kept OFF until the inverse current disappears. For all cases the current IINV should not be higher than IL(INV). Please note that during inverse current condition the protection functions of concerned channels are not available. Data Sheet 16 Rev. 1.01 2018-06-14 ITS4075Q-EP-D 75 m Quad Channel Smart High-Side Power Switch Power Stage VS ITS4075Q-EP-D Bias Gate Driver INx VINV Device Logic Inv. Comp OUTx IL(INV) GND ZGND Figure 11 Inverse Current Circuitry IL(INV) Inverse Current Event t VIN t Channel State ON" OFF" ON" OFF" t Figure 12 Data Sheet Inverse Current event: channel in OFF-state (channel remains off for duration of inverse current event) 17 Rev. 1.01 2018-06-14 ITS4075Q-EP-D 75 m Quad Channel Smart High-Side Power Switch Power Stage IL(INV) Inverse Current Event t VIN t Channel State ON" OFF" ON" OFF" OFF" t Figure 13 Inverse Current event: channel in ON-state (output not influenced but can be switched off) 5.5 Electrical Characteristics: Power Stage Table 4 Electrical Characteristics: Power Stage VS = 8 V to 36 V, Tj = -40C to 150C (unless otherwise specified). Typical values are given at VS = 24 V, Tj = 25C Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. - - 75 m ILx = 2 A VIN = 4.5 V Tj = 25C P_5.5.18 P_5.5.19 ON-state resistance per channel (Tj = 25C) RDS(ON) ON-state resistance per channel (Tj = 125C) RDS(ON)_125 - 120 - m 2) ON-state resistance per channel (Tj = 150C) RDS(ON)_150 - - 150 m ILx= 2 A VIN = 4.5 V Tj = 150C P_5.5.1 Nominal load current per channel IL(NOM)1 - - 2.6 A 1) 2) P_5.5.2 Drain to source clamping voltage VDS(AZ) = [VS - VOUT] VDS(AZ) 65 70 75 V IDS = 5 mA P_5.5.5 Output leakage current per channel IL(OFF) - 0.1 0.5 A 2) P_5.5.6 Output leakage current per channel IL(OFF)_150 - 1 5 A VIN floating VOUT = 0 V Tj = 150C P_5.5.4 Inverse current capability IL(INV) - 2.2 - A 2) 3) P_5.5.7 Data Sheet 18 ILx = 2 A VIN = 4.5 V Tj = 125C Tj < 150C VIN floating VOUT = 0 V Tj 85C VS < VOUTX t < 2 min Rev. 1.01 2018-06-14 ITS4075Q-EP-D 75 m Quad Channel Smart High-Side Power Switch Power Stage Table 4 Electrical Characteristics: Power Stage (cont'd) VS = 8 V to 36 V, Tj = -40C to 150C (unless otherwise specified). Typical values are given at VS = 24 V, Tj = 25C Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Slew rate (switch on) 30% to 70% of VS V/tON 0.3 0.75 1.9 V/s RL = 12 VS = 24 V P_5.5.8 Slew rate (switch off) 70% to 30% of VS -V/tOFF 0.3 0.75 1.9 V/s RL = 12 VS = 24 V P_5.5.9 Turn-ON time to VOUT = 90% VS tON 20 55 100 s RL = 12 VS = 24 V P_5.5.11 Turn-OFF time to VOUT = 10% tOFF 20 55 100 s RL = 12 VS = 24 V P_5.5.12 Turn-ON / OFF matching tSW -50 0 50 s RL = 12 VS = 24 V P_5.5.13 Turn-ON time to VOUT = 10% tON_delay - 25 50 s RL = 12 VS = 24 V P_5.5.14 Turn-OFF time to VOUT = 90% tOFF_delay - 25 50 s RL = 12 VS = 24 V P_5.5.15 VS tOFF - tON VS VS 1) This parameter describes the nominal load capability per channel from an electrical point of view respecting a maximum Tj 150C. Please note that depending on the individual thermal design of a real application (and a potentially insufficient thermal budget resulting hereof) additional restrictions for IL(NOM) may occur for pure thermal reasons in order not to exceed the maximum allowed junction temperature Tj = 150C. The latter needs to be considered especially for cases where all four channels are operating simultaneously under high load conditions and at high ambient temperature TAMB. For further details about potential derating of the nominal load current due to thermal restrictions please refer to "Thermal Considerations" on Page 38. 2) Not subject to production test; specified by design. 3) Please note that during inverse current condition the protection features are not operational. Data Sheet 19 Rev. 1.01 2018-06-14 ITS4075Q-EP-D 75 m Quad Channel Smart High-Side Power Switch Power Stage 5.6 Typical Performance Characteristics Power Stage Typical Performance Characteristics ON-State Resistance RDSON versus Junction Temperature Tj Leakage Current per channel IL(OFF) versus Junction Temperature Tj 2 160 VS = 24 V; I Load = 2A 1.8 VS = 24 V 140 1.6 120 1.4 IL(OFF) [uA] RDSON [m] 100 80 1.2 1 0.8 60 0.6 40 0.4 20 0.2 0 -50 0 50 Tj [C] 100 150 0 -50 0 50 Tj [C] 100 150 Output Clamp Voltage VDS(AZ) versus Junction Temperature Tj 75 74 73 VDS(AZ) [V] 72 71 70 69 68 67 CH 1 CH 2 CH 3 CH 4 66 65 -50 Data Sheet 0 50 Tj [C] 100 150 20 Rev. 1.01 2018-06-14 ITS4075Q-EP-D 75 m Quad Channel Smart High-Side Power Switch Power Stage Turn-ON time tON to VOUT = 90% versus Junction Temperature Tj Turn-OFF time tOFF to VOUT = 90% versus Junction Temperature Tj 100 100 VS = 24V 90 90 80 80 70 70 60 60 tOFF [us] tON [us] VS = 24V 50 50 40 40 30 30 I Load = 0.5A 20 I Load = 0.5A 20 I Load = 1.0A I Load = 1.0A I Load = 2.0A 10 I Load = 2.0A 10 I Load = 2.5A 0 -50 0 50 Tj [C] 100 I Load = 2.5A 0 -50 150 Turn-ON delay time tON_delay to VOUT = 10% versus Junction Temperature Tj 50 Tj [C] VS = 24V 45 40 40 35 35 30 30 tOFF_delay [us] 45 25 20 15 25 20 15 I Load = 0.5A 10 I Load = 0.5A 10 I Load = 1.0A I Load = 1.0A I Load = 2.0A 5 I Load = 2.0A 5 I Load = 2.5A Data Sheet 150 50 VS = 24V 0 -50 100 Turn-OFF delay time tOFF_delay to VOUT = 10% versus Junction Temperature Tj 50 tON_delay [us] 0 0 50 Tj [C] 100 I Load = 2.5A 0 -50 150 21 0 50 Tj [C] 100 150 Rev. 1.01 2018-06-14 ITS4075Q-EP-D 75 m Quad Channel Smart High-Side Power Switch Power Stage Turn-ON time tON to VOUT = 90% versus Load Current I Load Turn-OFF time tOFF to VOUT = 90% versus Load Current I Load 100 100 Tj = -40 C 90 Tj = 25 C Tj = 150 C 80 Tj = 25 C Tj = 150 C 80 70 70 60 60 tOFF [us] tON [us] Tj = -40 C 90 50 50 40 40 30 30 20 20 10 10 VS = 24 V 0 0 0.5 VS = 24 V 1 1.5 ILoad [A] 2 2.5 0 3 Turn-ON delay time tON_delay to VOUT = 10% versus Load Current I Load 0 0.5 1 1.5 ILoad [A] 2 50 Tj = -40 C 45 Tj = -40 C 45 Tj = 25 C Tj = 150 C 40 35 35 30 30 25 20 20 15 10 10 5 VS = 24 V 0 Data Sheet 0.5 Tj = 150 C 25 15 5 Tj = 25 C 40 tOFF_delay [us] tON_delay [us] 3 Turn-OFF delay time tOFF_delay to VOUT = 10% versus Load Current I Load 50 0 2.5 1 1.5 ILoad [A] 2 2.5 0 3 22 VS = 24 V 0 0.5 1 1.5 ILoad [A] 2 2.5 3 Rev. 1.01 2018-06-14 ITS4075Q-EP-D 75 m Quad Channel Smart High-Side Power Switch Protection Functions 6 Protection Functions The device provides integrated protection functions. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Protection functions are designed to prevent the destruction of the ITS4075Q-EP-D due to fault conditions described in the data sheet. Please note that fault conditions are not considered as normal operation conditions and the protection functions are neither designed for continuous operation nor for repetitive operation. 6.1 Loss of Ground Protection In case of loss of module ground when the load remains connected to ground, the device protects itself by automatically turning OFF (when it was previously ON) or remains OFF, regardless of the voltage applied at the input pins. In an application where the inputs are directly controlled by logic levels < VS (e.g. by a microcontroller without galvanic isolation), it is recommended to use input resistors 1) between the external control circuit (microcontroller) and the ITS4075Q-EP-D to protect also the external control circuit in case of loss of device ground. In case of loss of module or device ground, a current (IOUT(GND)) can flow out of the DMOS. Figure 14 sketches the situation. ZGND is recommended to be a resistor in series to a diode. ITS4075Q-EP-D VS + RST RIN Z DS(AZ) ZD(AZ) ST INx Logic IOUT(GND) OUTx GND ZGND Figure 14 Loss of Ground Protection with External Components 1) Recommended value is 10 k Data Sheet 23 Rev. 1.01 2018-06-14 ITS4075Q-EP-D 75 m Quad Channel Smart High-Side Power Switch Protection Functions 6.2 Undervoltage Protection If the supply voltage falls below VS(UV) the undervoltage protection of the device is triggered. VS(UV) represents hence the minimum voltage for which the switch still can hold ON. Once the device is off VS(OP)_MIN represents the lowest voltage where the device is turning on again (and thus the channels can be switched again). If the supply voltage is below the undervoltage threshold VS(UV), the channels of the device are OFF (or turning OFF). As soon as the supply voltage is recovering and exceeding the threshold of the functional supply voltage VS(OP)_MIN, the device is re-powering and its channels can be switched again. In addition the protection functions as well as diagnosis become operational once VSOP_MIN is reached. Figure 15 sketches the undervoltage mechanism. VOUT VS(UV) Figure 15 Undervoltage Behavior 6.2.1 Overvoltage Protection V S(OP)_MIN VS There is an integrated clamping mechanism for overvoltage protection (ZD(AZ)). To ensure this mechanism operates properly in the application, the current in the Zener diode ZD(AZ) must be limited by a ground resistor. Figure 16 shows a typical application to withstand overvoltage issues. In case of supply voltage higher than VS(AZ), the voltage across supply to ground path is clamped. As a result, the internal ground potential rises to VS - VS(AZ). Due to the ESD Zener diodes, the potential at pin INx rises almost to that potential, depending on the impedance of the connected circuitry 1). In the case the device was ON, prior to overvoltage, the ITS4075QEP-D remains ON. In case the ITS4075Q-EP-D was OFF, prior to overvoltage, the power transistor can be activated. In case the supply voltage is above VS(SC) and below VDS(AZ), the output transistor is still operational and follows the input. If at least one channel is in ON-state, parameters are no longer within specified range and lifetime is reduced compared to the nominal supply voltage range. This especially impacts the short circuit robustness, as well as the maximum energy EAS capability. ZGND is recommended to be either a resistor (27 ) in series to a diode or alternatively a 150 power resistor. 1) Hence, the usage of external input resistors needs to be considered Data Sheet 24 Rev. 1.01 2018-06-14 ITS4075Q-EP-D 75 m Quad Channel Smart High-Side Power Switch Protection Functions ISOV VS + Z DS(AZ) RST RIN ZD(AZ) ST INx Logic IOUT OUTx ITS4075Q-EP-D GND ZGND Figure 16 Data Sheet Overvoltage Protection with External Components 25 Rev. 1.01 2018-06-14 ITS4075Q-EP-D 75 m Quad Channel Smart High-Side Power Switch Protection Functions 6.3 Reverse Polarity Protection In case of reverse polarity, the intrinsic body diodes of the affected power DMOS channels will dissipate power. The current flowing through the intrinsic body diode is limited externally by the load itself. But in addition the current into the ground path and the logic pins must be limited by an external resistor to the maximum allowed current described in Chapter 4.1. Figure 17 shows a typical application. ZGND resistor is used to limit the current through the Zener protection of the device. ZGND is recommended to be either a resistor (~ 27 ) in series to a diode or alternatively a power resistor (~ 150 ). During reverse polarity no protection functions are available. ITS4075Q-EP-D Microcontroller Protection diodes VS VDS(REV) + -VS(REV) ZDS(AZ) R ST RIN ZD(AZ) ST INx Logic OUTx GND ZGND Figure 17 Data Sheet Reverse Polarity Protection with External Components 26 Rev. 1.01 2018-06-14 ITS4075Q-EP-D 75 m Quad Channel Smart High-Side Power Switch Protection Functions 6.4 Overload Protection In case of overload, such as high inrush current of a cold lamp filament, or short circuit to ground, the ITS4075Q-EP-D offers a set of protection mechanisms which is illustrated in Figure 18. 6.4.1 Current Limitation As a first step, the instantaneous power in the switch is contained within a safe range by limiting the current to the maximum current allowed in the switch IL(LIM). During this time, where the current is limited to IL(LM), the DMOS temperature is increasing caused by the voltage drop VDS over the DMOS. Overtemperature concept: Overtemperature behavior: VIN H L Tj(SC) ON tON VOUT t tOFF heating up 0 OFF Tj cooling down Device Status t Tj Tj(SC) Tj(SC) Tj(SC) Normal Toggling Overtemperature t VST H L t OFF Waveforms turn on into a short circuit: ON OFF VIN H H L tON VOUT L t tOFF 0 tON VOUT tOFF 0 t IL(LIM) t t IL(LIM) 0 0 t VST tST(FAULT) VST tST(FAULT)_SC1 t H H L L t OFF Overloaded OFF t OFF Shut down by overtemperature and restart after cooling down (thermal toggling) once the device exceeds thermal threshold after being heated up during current limitation state Data Sheet OFF Waveforms short circuit during on state: VIN Figure 18 ON Normal operation OUT shorted to GND OFF Shut down by overtemperature and restart after cooling down (thermal toggling) once the device exceeds thermal threshold after being heated up during current limitation state Protection behavior of the ITS4075Q-EP-D 27 Rev. 1.01 2018-06-14 ITS4075Q-EP-D 75 m Quad Channel Smart High-Side Power Switch Protection Functions 6.4.2 Temperature Limitation in the Power DMOS Each channel incorporates one temperature sensor. Activation of this temperature sensor will cause an overheated channel to switch OFF to prevent destruction. Any protective overtemperature shutdown event triggered within a channel is switching OFF the output of the corresponding channel until the temperature reaches an acceptable value again. A restart functionality is implemented that is switching the channel ON again after the DMOS temperature has sufficiently cooled down. 6.5 Electrical Characteristics: Protection Functions Table 5 Electrical Characteristics: Protection Functions 1) VS = 8 V to 36 V, Tj = -40C to 150C (unless otherwise specified). Typical values are given at VS = 24 V, Tj = 25C Parameter Symbol Values Unit Note or Test Condition Number P_6.5.1 Min. Typ. Max. IOUT(GND) - 0.1 - mA 2) 3) VDS(REV) - 650 700 mV IL = -2 A Tj = 150C P_6.5.2 VS(AZ) 65 70 75 V 4) P_6.5.3 Load current limitation IL(LIM) 3.3 4.1 4.9 A - Thermal shutdown temperature Tj(SC) 150 175 200 C 3) - P_6.5.6 Thermal shutdown hysteresis Tj(SC) - 30 - K 3) - P_6.5.7 Loss of Ground Output leakage current while GND disconnected VS = 24 V Reverse Polarity Drain source diode voltage during reverse polarity Overvoltage Overvoltage protection ISOV = 5 mA Overload Condition P_6.5.4 1) Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Integrated protection functions are designed to prevent IC from destruction under fault conditions described in the data sheet. Fault conditions are considered as "outside" normal operating range. Protection functions are designed neither for continuous nor repetitive operation. 2) All pins are disconnected except VS and OUT. 3) Not subject to production test; specified by design. 4) For practical cases it is recommended to place a resistor in the range of 27 into the GND path to limit the GND current associated with overvoltage events. Data Sheet 28 Rev. 1.01 2018-06-14 ITS4075Q-EP-D 75 m Quad Channel Smart High-Side Power Switch Protection Functions 6.6 Typical Performance Characteristics Protection Functions Typical Performance Characteristics Current Limit IL(LIM) versus Junction Temperature Tj Clamping Voltage VS(AZ) versus Voltage Tj 6 75 74 5 73 72 4 VS(AZ) [V] IL(LIM) [A] 71 3 70 69 2 68 67 1 66 VDS = 12V 0 -50 Data Sheet 0 50 Tj [C] 100 65 -50 150 29 0 50 Tj [C] 100 150 Rev. 1.01 2018-06-14 ITS4075Q-EP-D 75 m Quad Channel Smart High-Side Power Switch Diagnostic Functions 7 Diagnostic Functions For diagnosis purpose, the ITS4075Q-EP-D provides a digital signal at pin ST. This signal is called STATUS. The STATUS pin is realized as open drain output and must be connected to an external pull-up resistor. During normal operation the STATUS signal is logic "High" (H). During short circuit to ground or overtemperature condition the STATUS signal is logic "Low" (L). Table 6 shows the corresponding truth table. Table 6 Diagnostic Truth Table 1) 2) Device Operation INX all INi except INX OUTX all OUTi except OUTX ST Comment Normal Operation L L OFF OFF H 3) H H ON ON H H don't care ON X H L don't care OFF X H Short Circuit to GND H don't care ON X L 3) 4) Overtemperature don't care OFF 5) X L 3) 1) 2) 3) 4) 5) H External pull up at ST pin Please refer to Table 7 for more details. Not subject to production test; specified by design. "X" denotes status of OUTi according to the status of the corresponding input signals INi. Device not in specified RDS(ON). Channel remains off during cooling-down phase of power stage; then channel tries to re-start. 7.1 Electrical Characteristics: Diagnostic Functions Table 7 Electrical Characteristics: Diagnostic Functions VS = 8 V to 36 V, Tj = -40C to 150C (unless otherwise specified). Typical values are given at VS = 24 V, Tj = 25C Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition - 25 - s STATUS settling time for channel tST(FAULT)_SC1 - start-up into existing overload 2) 45 90 s Number Diagnostic Timing in Overload Condition STATUS settling time for overload tST(FAULT) detection "Low" level STATUS voltage VST(L) VS = 24 V; load jump of RL: 12 -> 3.3 ; Please refer to Figure 18 for more details P_7.1.1 VDS 8 V; P_7.1.9 Please refer to Figure 18 for more details - - 0.5 V IST = 1.6 mA 3) P_7.1.3 4) V VS > VST P_7.1.4 mA VST < 0.5 V P_7.1.5 "High" level STATUS voltage VST(H) 2 - - Current through STATUS pin (Operating Range) IST - - 1.6 Data Sheet 1) 30 Rev. 1.01 2018-06-14 ITS4075Q-EP-D 75 m Quad Channel Smart High-Side Power Switch Diagnostic Functions Table 7 Electrical Characteristics: Diagnostic Functions (cont'd) VS = 8 V to 36 V, Tj = -40C to 150C (unless otherwise specified). Typical values are given at VS = 24 V, Tj = 25C Parameter Symbol Channel fault detection interrogation time (Sequential Pulse Width) Tx Tm STATUS signal "High" valid window after Tx on fault affected channel Minimum delay between subsequent Tx interrogation windows. TX-2-X Maximum delay time between Tx TD ("High" to "Low") on fault affected channel and STATUS "High" signal Tm Values Min. Typ. Max. Unit Note or Test Condition Number 3 - 6 s VST < 0.5 V 5) P_7.1.2 40 80 150 s 5) - P_7.1.6 200 - - s 1) - P_7.1.8 - 8 - s 1) - P_7.1.7 1) Not subject to production test; specified by design. 2) This parameter describes the status settling time when a channel is switched on into an already existing overload condition. This parameter is referenced to the edge of the input pin IN that switches the channel into overload. 3) Levels referenced to device ground. 4) Depends on pull-up circuit that is used within application; maximum ratings of STATUS pin need to be respected. 5) Please refer to "Channel Fault Detection" on Page 31 for more details. 7.2 Channel Fault Detection The ITS4075Q-EP-D is equipped with an intelligent channel fault detection system, which allows with the aid of a microcontroller to identify and communicate the channel on which the fault occurs. During normal operation the STATUS pin is kept "High" by the external pull-up resistor as shown in Table 6. If - in case of a fault - the application requires the information on which of the channels the fault occurs when a "Low" STATUS is flagged, then the microcontroller can be programmed according to the sequence depicted as an example in Figure 19. The figure shows a case where three channels are active (these are channels 1, 2 and 4). Channel 3 in this example is not switched ON. During normal operation of channels 1, 2 and 4 the STATUS signal is "High". If a fault occurs, e.g. at channel 4, the STATUS signal goes "Low" to flag an error to the microcontroller. The microcontroller, in order to identify on which channel the fault occurs, must send a "Low" pulse sequentially to the input of each active channel, that is channels 1, 2 and 4 in this case. These pulses are shown in Figure 19 and their width is denominated Tx. The pulse width Tx should be between 3 s up to 6 s in order to make sure that the output does not react to this short inversion input level. The STATUS signal will go to "High" for a short period of time Tmonly after the channel on which the fault occurs gets a "Low" pulse from the microcontroller, which in this case is after channel 4 receives a "Low" pulse for a time Tx. In this way, by reading back whether an inversion of the STATUS flag within Tm occurs, the microcontroller is able to detect on which channel the fault occurs. Once the microcontroller receives this information it can start to switch OFF the channel on which the fault occurs (channel 4 in this case) via the corresponding input pin. For the delay time TD between Tx going "Low" and Tm going "High" a value of 8 s needs to be taken into account. Data Sheet 31 Rev. 1.01 2018-06-14 ITS4075Q-EP-D 75 m Quad Channel Smart High-Side Power Switch Diagnostic Functions Normal Operation Fault at channel 4 Tm ? STATUS IN1 Tm TD TD TD TX IN2 IN3 Tm Fault Channel ? TX Normal Operation TX-2-X TX-2-X TX IN4 t An inverted ST-pin signal following a TX interrogation pulse within a time window Tm on a given channel confirms a fault channel. A non-inverted ST-pin signal after a TX pulse (dashed lines) indicate that corresponding channel is not in fault condition. Figure 19 Data Sheet Channel Fault Detection Timing Diagram 32 Rev. 1.01 2018-06-14 ITS4075Q-EP-D 75 m Quad Channel Smart High-Side Power Switch Diagnostic Functions 7.3 Typical Performance Characteristics Diagnostic Functions Typical Performance Characteristics Status Settling Time tST(FAULT) versus Junction Temperature Tj (overload during ON) Status Settling Time tST(Fault)_SC1 versus Junction Temperature Tj (switch on into overload) 50 80 typ. t ST(Fault) for R L: 12 -> 3.3 45 40 tST(Fault)_SC1 typ. t ST(Fault) for R L: 12 -> 0 70 VS = 24V 60 tST(Fault)_SC1 [us] t ST(Fault) [us] 35 30 25 20 50 40 30 15 20 10 10 5 VS = 24V VDS = 8V 0 -50 0 50 Tj [C] 100 0 -50 150 0 50 Tj [C] 100 150 Maximum Delay Time TD (TX `H->L' to ST `L->H') vs. ST "High" Valid window (after TX) TM versus Junction Temperature Tj Junction Temperature Tj 10 100 TM 9 90 8 80 7 70 6 60 TM [us] TD [us] TD 5 50 4 40 3 30 2 20 1 10 VS = 24V 0 -50 Data Sheet 0 VS = 24V 50 Tj [C] 100 0 -50 150 33 0 50 Tj [C] 100 150 Rev. 1.01 2018-06-14 ITS4075Q-EP-D 75 m Quad Channel Smart High-Side Power Switch Input Pins 8 Input Pins 8.1 Input Circuitry The input circuitry is compatible with 3.3 V and 5 V microcontrollers as well as input levels up to VS 1). The concept of the input pin is to react to voltage thresholds which are referenced to device ground. An implemented Schmitt trigger avoids any undefined state if the voltage on the input pin is slowly increasing or decreasing. The output is either OFF or ON but cannot be in a linear or undefined state. Figure 20 shows the electrical equivalent input circuitry. In case a channel is permanently not needed, the corresponding input pin shall not be left floating but tied with a serial resistor to device ground (not module ground). The recommended value for the serial resistor is 2.2 k. VS ITS4075Q-EP-D Bias Gate Driver INx VIH Inv. Comp Device Logic OUTx GND ZGND Figure 20 Input Pin Circuitry 8.2 Input Pin Voltage The input pin IN uses a comparator with hysteresis. Switching "ON / OFF" of the channels takes place in a defined region, set by the thresholds VIN(L),max and VIN(H),min. The exact values where the "ON" and "OFF" take place depend on the process, as well as on the temperature. To avoid cross talk and parasitic turn-ON or turnOFF, a hysteresis is implemented. This ensures an improved immunity to noise. 1) VIN must not exceed VS. The relation VIN VS must always be fulfilled. Data Sheet 34 Rev. 1.01 2018-06-14 ITS4075Q-EP-D 75 m Quad Channel Smart High-Side Power Switch Input Pins 8.3 Electrical Characteristics: Input Pins Table 8 Electrical Characteristics: Input Pins VS = 8 V to 36 V, Tj = -40C to 150C (unless otherwise specified). Typical values are given at VS = 24 V, Tj = 25C Parameter Symbol Values Min. Typ. Max. Unit Note or Test Condition Number Input Pins Characteristics "Low" level input voltage range VIN(L) -0.3 - 0.8 V - 1) P_8.3.1 "High" level input voltage range VIN(H) 2 - 36 V VS > VIN 1) P_8.3.2 Input voltage hysteresis VIN(HYS) - 250 - mV - 2) P_8.3.3 "Low" level input current IIN(L) - 35 70 A VIN = 0.8 V P_8.3.4 "High" level input current IIN(H) - 43 70 A VIN = 24 V P_8.3.5 1) Levels referenced to device ground. 2) Not subject to production test; specified by design. Data Sheet 35 Rev. 1.01 2018-06-14 ITS4075Q-EP-D 75 m Quad Channel Smart High-Side Power Switch Input Pins 8.4 Typical Performance Characteristics Input Pins Typical Performance Characteristics Input Voltage thresholds VIN(L) VIN(H) versus Junction Temperature Tj Input Voltage hysteresis VIN(HYS) versus Junction Temperature Tj 2 0.5 VIN(H) VIN(HYS) 0.45 VIN(L) 1.6 0.4 1.4 0.35 1.2 0.3 VIN [V] VIN [V] 1.8 1 0.25 0.8 0.2 0.6 0.15 0.4 0.1 0.2 0.05 VS = 24V VS = 24V 0 0 50 Tj [C] 100 0 150 Input Pin Current IIN(H) versus Supply Voltage V S 0 50 Tj [C] 100 150 100 150 Input Pin Current IIN(H) versus Junction Temperature Tj 70 70 VIN = 24V Tj -40C Tj 25C 60 60 Tj 150C 40 40 IIN [uA] 50 IIN [uA] 50 30 30 20 20 10 10 VS = 28.8V 0 0 Data Sheet 5 10 15 VIN [V] 20 0 25 36 0 50 Tj [C] Rev. 1.01 2018-06-14 ITS4075Q-EP-D 75 m Quad Channel Smart High-Side Power Switch Application Information 9 Application Information 9.1 Application Diagram Note: This is a very simplified example of an application circuit. The function must be verified in the real application. Linear Voltage Regulator e.g. IFX1763 VOUT External components for Surge Immunity VIN COUT VS VDD I/O I/O IN1 OUT1 IN2 OUT2 LOAD 1 VS Microcontroller e.g. XMC4xxx I/O ITS4075Q-EP-D OUT3 IN3 OUT4 IN4 LOAD 4 I/O ST TM GND LOAD 3 30 k I/O LOAD 2 VDD 2.2 k GND ZGND External components for reverse polarity protection and overvoltage pulses. Recommended setup for ZGND is a diode for reverse polarity in series with a resistor of ~27 to limit GND current during overvoltage spikes. Figure 21 Application Diagram with ITS4075Q-EP-D In Figure 21 above a simplified application diagram is shown where the inputs are galvanically isolated from VS with optocouplers. Thanks to the fact that the input pins are 24 V capable they can be directly connected to the optocouplers. Reverse polarity protection can be achieved with external components. In this context it should be noted that input pins of channels which are permanently unused have to be tied with 2.2 k resistance to device ground. In addition the TM-pin must be always be tied with a serial resistor to device ground in order to protect the pin in case of reverse polarity. The recommended value for this serial resistor is also 2.2 k. For applications where no galvanic isolation is present between the external control circuitry (e.g microcontroller) and the input pins of the ITS4075Q-EP-D serial input resistors need to be placed in order to Data Sheet 37 Rev. 1.01 2018-06-14 ITS4075Q-EP-D 75 m Quad Channel Smart High-Side Power Switch Application Information protect the external control circuitry and the input structures of the ITS4075Q-EP-D under fault conditions (like e.g. reverse polarity, loss of ground or overvoltage). For further details please also refer to the corresponding sections in Chapter 6. The recommended value for such serial input resistors is 10 k however application specific optimized values may also depend on the individual application conditions as well as the applied external control circuitry / microcontroller. 9.2 Thermal Considerations If the cooling possibilities within the application are not sufficient to sink the heat of the dissipated power the junction temperature Tj of the device may exceed its maximum specified rating of 150C and eventually trigger a thermal shutdown of the overheated channels to protect the device from destruction. Such thermal shutdown events may occur e.g. if one or more channels are operated in overload conditions that are causing the current limitation functionality to become active. If the current limitation of a channel becomes active the power dissipation will rise rapidly and in many cases lead to thermal shutdown events of the corresponding channels within short periods of time. But also under nominal load conditions the power dissipation can become too high inside an application if it is applied at high environmental temperature TAMB and if at the same time the cooling capability of the PCB is not sufficient. In general the cooling capability of an IC on a PCB within an application can be described for static cases by its thermal resistance from junction-to-ambient RthJA. The thermal resistance RthJA can be improved by adding cooling area on top- or bottom layer of the PCB or by adding inner layers that are connected to the VS layer with thermal vias. Thermal vias show the best efficiency for heat distribution if directly placed underneath the exposed pad of the ITS4075Q-EP-D. The achievable values for RthJA will differ from application to application. As reference simulation values of RthJA for a set of standardized JEDEC cases are provided in Chapter 4.4 "Thermal Resistance" on Page 12. Actual values in real applications naturally can be lower or higher. For cases where the achievable thermal resistance RthJA and the hereof resulting thermal budget within an application is not sufficient for a given ambient temperature TAMB there is no other choice than to lower the load current to smaller numbers than the allowed maximum nominal current of 2.6 A. Figure 22 illustrates how the derating of the nominal current due to excessive power dissipation can look like as a function of achievable RthJA and given TAMB. The graphs show how the thermal budget with its limiting condition Tj = 150C can be shared between the influencing parameters TAMB, RthJA, ILoad depending on the number of active channels nCH. Next to the standardized JEDEC cases mentioned above also an arbitrarily chosen value of RthJA = 25 K/W as additional reference for a highly optimized PCB solution is included in the graphs. The calculation of the thermal budget displayed in the graphs follows simple rules as given in the equations below. It should be noted that the calculation is restricted to static cases where the resulting TAMB and Tj have reached a stable equilibrium. (9.1) Tj = TAMB + RthJA x PDISS (9.2) PDISS = I2Load x RDS(ON) x nCH + VS x IGND Data Sheet 38 Rev. 1.01 2018-06-14 ITS4075Q-EP-D 75 m Quad Channel Smart High-Side Power Switch 2.5 2.5 2 2 Inom,max [A] Inom,max [A] Application Information 1.5 1 1.5 1 RthJA = 25 K/W RthJA = 25 K/W RthJA = 33 K/W 0.5 RthJA =102 K/W 40 50 60 70 TAMB [C] 80 90 RthJA =102 K/W 0 20 100 2.5 2.5 2 2 1.5 1 30 60 70 TAMB [C] 80 90 100 RthJA = 25 K/W RthJA = 33 K/W 40 50 RthJA = 40 K/W 3 channels active (VS = 28V) RthJA =102 K/W 30 RthJA = 33 K/W 0.5 RthJA = 40 K/W RthJA = 48 K/W Data Sheet 50 1 0.5 Figure 22 40 1.5 RthJA = 25 K/W 0 20 2 channels active (VS = 28V) RthJA = 48 K/W Inom,max [A] Inom,max [A] 30 RthJA = 40 K/W 1 channel active (VS = 28V) RthJA = 48 K/W 0 20 RthJA = 33 K/W 0.5 RthJA = 40 K/W 60 70 TAMB [C] 80 90 4 channels active (VS = 28V) RthJA = 48 K/W RthJA =102 K/W 0 20 100 30 40 50 60 70 TAMB [C] 80 90 100 Possible thermal derating of nominal current due to insufficient cooling capability of PCB 39 Rev. 1.01 2018-06-14 ITS4075Q-EP-D 75 m Quad Channel Smart High-Side Power Switch Package Outlines [ & & [ 6($7,1* &23/$1$5,7< 3/$1( s s ' [ $% & [ %27720 9,(: $ ,1'(; 0$5.,1* % s s s [ s ' *$8*( 3/$1( s rr 0$; s 67$1'2)) Package Outlines 10 ' $% '2(6 127 ,1&/8'( 3/$67,& 25 0(7$/ 3527586,21 2) 0$; 3(5 6,'( '$0%$5 352786,21 6+$// %( 0$;,080 00 727$/ ,1 (;&(66 2) /($' :,'7+ $// ',0(16,216 $5( ,1 81,76 00 7+( '5$:,1* ,6 ,1 &203/,$1&( :,7+ ,62 352-(&7,21 0(7+2' > @ Figure 23 PG-TSDSO-14 (Plastic Dual Small Outline Package) (RoHS-Compliant) Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). For further information on alternative packages, please visit our website: http://www.infineon.com/packages. Data Sheet 40 Dimensions in mm Rev. 1.01 2018-06-14 ITS4075Q-EP-D 75 m Quad Channel Smart High-Side Power Switch Revision History 11 Revision History Revision Date Changes 1.01 2018-06-14 Data Sheet Rev. 1.01 Editorial changes 1.0 2018-05-22 Data Sheet (Initial Release) Data Sheet 41 Rev. 1.01 2018-06-14 Trademarks All referenced product or service names and trademarks are the property of their respective owners. Edition 2018-06-14 Published by Infineon Technologies AG 81726 Munich, Germany (c) 2018 Infineon Technologies AG. All Rights Reserved. Do you have a question about any aspect of this document? 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