SN54LVC646A, SN74LVC646A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCAS302I - JANUARY 1993 - REVISED AUGUST 2002 D D D D D SN54LVC646A . . . JT OR W PACKAGE SN74LVC646A . . . DB, DW, NS, OR PW PACKAGE (TOP VIEW) Operate From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 7.4 ns at 3.3 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25C Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25C Support Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC) Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) - 1000-V Charged-Device Model (C101) CLKAB SAB DIR A1 A2 A3 A4 A5 A6 A7 A8 GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC CLKBA SBA OE B1 B2 B3 B4 B5 B6 B7 B8 SN54LVC646A . . . FK PACKAGE (TOP VIEW) DIR SAB CLKAB NC VCC CLKBA SBA D D D D description/ordering information The SN54LVC646A octal bus transceiver and register is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVC646A octal bus transceiver and register is designed for 1.65-V to 3.6-V VCC operation. 5 4 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 19 11 12 13 14 15 16 17 18 OE B1 B2 NC B3 B4 B5 A7 A8 GND NC B8 B7 B6 A1 A2 A3 NC A4 A5 A6 NC - No internal connection ORDERING INFORMATION -55C to 125C TOP-SIDE MARKING Tube SN74LVC646ADW Tape and reel SN74LVC646ADWR SOP - NS Tape and reel SN74LVC646ANSR LVC646A SSOP - DB Tape and reel SN74LVC646ADBR LC646A TSSOP - PW Tape and reel SN74LVC646APWR LC646A CDIP - JT Tube SNJ54LVC646AJT SNJ54LVC646AJT CFP - W Tube SNJ54LVC646AW SNJ54LVC646AW LCCC - FK Tube SNJ54LVC646AFK SOIC - DW -40C to 85C ORDERABLE PART NUMBER PACKAGE TA LVC646A SNJ54LVC646AFK Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SN54LVC646A, SN74LVC646A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCAS302I - JANUARY 1993 - REVISED AUGUST 2002 description/ordering information (continued) These devices consist of bus-transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that are performed with the 'LVC646A devices. Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode, data present at the high-impedance port is stored in either register or in both. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR determines which bus receives data when OE is low. In the isolation mode (OE high), A data is stored in one register and B data can be stored in the other register. When an output function is disabled, the input function still is enabled and can be used to store and transmit data. Only one of the two buses, A or B, can be driven at a time. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. FUNCTION TABLE INPUTS DATA I/O OE DIR CLKAB CLKBA SAB SBA A1-A8 B1-B8 X X X X X Input Unspecified OPERATION OR FUNCTION X X X X X Unspecified Input Store A, B unspecified Store B, A unspecified H X X X Input Input Store A and B data H X H or L H or L X X Input disabled Input disabled Isolation, hold storage L L X X X L Output Input Real-time B data to A bus L L X H or L X H Output Input Stored B data to A bus L H X X L X Input Output Real-time A data to B bus L H H or L X H X Input Output Stored A data to B bus The data-output functions can be enabled or disabled by various signals at OE and DIR. Data-input functions always are enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs. 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54LVC646A, SN74LVC646A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS 21 OE L 3 DIR L 1 23 CLKAB CLKBA X X 2 SAB X BUS B BUS A BUS A BUS B SCAS302I - JANUARY 1993 - REVISED AUGUST 2002 22 SBA L 21 OE L 3 DIR H 3 DIR X X X 1 23 CLKAB CLKBA X X 2 SAB L 2 SAB X X X 22 SBA X BUS B BUS A BUS A 21 OE X X H 23 CLKBA X REAL-TIME TRANSFER BUS A TO BUS B BUS B REAL-TIME TRANSFER BUS B TO BUS A 1 CLKAB X 22 SBA X X X STORAGE FROM A, B, OR A AND B 21 OE L L 3 DIR L H 1 CLKAB X H or L 23 CLKBA H or L X 2 SAB X H 22 SBA H X TRANSFER STORED DATA TO A AND/OR B Figure 1. Bus-Management Functions POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SN54LVC646A, SN74LVC646A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCAS302I - JANUARY 1993 - REVISED AUGUST 2002 logic diagram (positive logic) OE DIR CLKBA SBA CLKAB SAB 21 3 23 22 1 2 One of Eight Channels 1D C1 A1 4 20 1D C1 To Seven Other Channels Pin numbers shown are for the DB, DW, JT, NS, PW, and W packages. 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 B1 SN54LVC646A, SN74LVC646A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCAS302I - JANUARY 1993 - REVISED AUGUST 2002 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Package thermal impedance, JA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 4) SN54LVC646A VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage VI Input voltage VO Output voltage Operating Data retention only VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V MAX MIN MAX 2 3.6 1.65 3.6 1.5 High level output current High-level IOL Low level output current Low-level t/v Input transition rise or fall rate 1.5 0.65xVCC 1.7 2 UNIT V V 2 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V 0.35xVCC 0.7 VCC = 2.7 V to 3.6 V IOH SN74LVC646A MIN 0.8 V 0.8 0 5.5 0 5.5 V High or low state 0 0 VCC 5.5 0 3-state VCC 5.5 V VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V -4 -8 -12 -12 -24 -24 VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V 0 mA 4 8 12 12 24 24 10 10 mA ns/V TA Operating free-air temperature -55 125 -40 85 C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SN54LVC646A, SN74LVC646A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCAS302I - JANUARY 1993 - REVISED AUGUST 2002 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS 2.7 V to 3.6 V IOH = -4 mA IOH = -8 mA Control inputs 2.2 3V 2.4 2.4 3V 2.2 2.2 0.2 2.7 V to 3.6 V 0.2 0.45 0.7 IOL = 12 mA IOL = 24 mA 2.7 V 0.4 0.4 3V 0.55 0.55 VI = 0 to 5.5 V 3.6 V 5 5 A VO = 0 to 5.5 V VI = VCC or GND 3.6 V VI 5.5 V IO = 0 VI = VCC or GND 36V 3.6 2.7 V to 3.6 V V 10 A 15 10 A 10 10 10 10 500 500 0 3.6 V One input at VCC - 0.6 V, Other inputs at VCC or GND Control inputs 2.2 2.3 V VI or VO = 5.5 V Ci V 1.7 2.7 V 1.65 V IOZ ICC 1.2 IOL = 4 mA IOL = 8 mA Ioff ICC VCC-0.2 1.65 V to 3.6 V IOL = 100 A UNIT VCC-0.2 2.3 V IOH = -24 mA II MIN 1.65 V IOH = -12 12 mA VOL SN74LVC646A TYP MAX MIN 1.65 V to 3.6 V IOH = -100 100 A VOH SN54LVC646A TYP MAX VCC A A 3.3 V 4.5 4.5 pF Cio A or B ports VO = VCC or GND 3.3 V All typical values are at VCC = 3.3 V, TA = 25C. For I/O ports, the parameter IOZ includes the input leakage current. This applies in the disabled state only. 7.5 7.5 pF timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) SN54LVC646A VCC = 2.7 V MIN MIN 150 UNIT MAX fclock tw Clock frequency Pulse duration 3.3 3.3 ns tsu Setup time, data before CLK 1.6 1.5 ns Hold time, data after CLK 1.7 1.7 ns th 6 MAX VCC = 3.3 V 0.3 V POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 150 MHz SN54LVC646A, SN74LVC646A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCAS302I - JANUARY 1993 - REVISED AUGUST 2002 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) SN74LVC646A VCC = 1.8 V 0.15 V MIN fclock tw Clock frequency tsu VCC = 2.5 V 0.2 V MAX MIN MAX VCC = 2.7 V MIN MAX VCC = 3.3 V 0.3 V MIN 150 UNIT MAX 150 MHz Pulse duration 3.3 3.3 ns Setup time, data before CLK 1.6 1.5 ns 1.7 1.7 ns th Hold time, data after CLK This information was not available at the time of publication. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) SN54LVC646A FROM (INPUT) PARAMETER TO (OUTPUT) VCC = 2.7 V MIN fmax MAX 150 A or B tpd B or A CLK A or B SBA or SAB VCC = 3.3 V 0.3 V MIN UNIT MAX 150 MHz 7.9 1 7.4 8.8 1 8.4 9.9 1 8.6 ns ten OE A 10.2 1 8.2 ns tdis OE A 8.9 1 7.5 ns ten DIR B 10.4 1 8.3 ns tdis DIR B 8.7 1 7.9 ns switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) SN74LVC646A PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 1.8 V 0.15 V MIN fmax A or B tpd MAX CLK SBA or SAB B or A A or B VCC = 2.5 V 0.2 V MIN MAX VCC = 2.7 V MIN MAX 150 VCC = 3.3 V 0.3 V MIN UNIT MAX 150 MHz 7.9 1.4 7.4 8.8 1.3 8.4 9.9 1.4 8.6 ns ten OE A 10.2 1 8.2 ns tdis OE A 8.9 1 7.5 ns ten DIR B 10.4 1.2 8.3 ns 8.7 1.1 7.9 ns tdis B DIR This information was not available at the time of publication. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 SN54LVC646A, SN74LVC646A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCAS302I - JANUARY 1993 - REVISED AUGUST 2002 operating characteristics, TA = 25C TEST CONDITIONS PARAMETER Cpd Power dissipation capacitance per transceiver Outputs enabled Outputs disabled f = 10 MHz VCC = 1.8 V TYP POST OFFICE BOX 655303 VCC = 3.3 V TYP 75 9 This information was not available at the time of publication. 8 VCC = 2.5 V TYP * DALLAS, TEXAS 75265 UNIT pF SN54LVC646A, SN74LVC646A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCAS302I - JANUARY 1993 - REVISED AUGUST 2002 PARAMETER MEASUREMENT INFORMATION RL From Output Under Test CL (see Note A) VLOAD Open S1 GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V 0.15 V 2.5 V 0.2 V 2.7 V 3.3 V 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V 2 ns 2 ns 2.5 ns 2.5 ns VM VLOAD CL RL V VCC/2 VCC/2 1.5 V 1.5 V 2 x VCC 2 x VCC 6V 6V 30 pF 30 pF 50 pF 50 pF 1 k 500 500 500 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH tPHL VOH VM Output VM VOL tPHL Output Waveform 1 S1 at VLOAD (see Note B) tPLH VM VM VM 0V tPLZ tPZL VLOAD/2 VM VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + V VOL tPHZ tPZH VOH Output VI Output Control VM VOH - V VOH 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 . D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 2. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 MECHANICAL DATA MCER004A - JANUARY 1995 - REVISED JANUARY 1997 JT (R-GDIP-T**) CERAMIC DUAL-IN-LINE 24 LEADS SHOWN PINS ** A 13 24 B 1 24 28 A MAX 1.280 (32,51) 1.460 (37,08) A MIN 1.240 (31,50) 1.440 (36,58) B MAX 0.300 (7,62) 0.291 (7,39) B MIN 0.245 (6,22) 0.285 (7,24) DIM 12 0.070 (1,78) 0.030 (0,76) 0.100 (2,54) MAX 0.320 (8,13) 0.290 (7,37) 0.015 (0,38) MIN 0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN 0.023 (0,58) 0.015 (0,38) 0-15 0.014 (0,36) 0.008 (0,20) 0.100 (2,54) 4040110/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. Falls within MIL STD 1835 GDIP3-T24, GDIP4-T28, and JEDEC MO-058 AA, MO-058 AB POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 MECHANICAL DATA MCFP007 - OCTOBER 1994 W (R-GDFP-F24) CERAMIC DUAL FLATPACK 0.375 (9,53) 0.340 (8,64) Base and Seating Plane 0.006 (0,15) 0.004 (0,10) 0.090 (2,29) 0.045 (1,14) 0.045 (1,14) 0.026 (0,66) 0.395 (10,03) 0.360 (9,14) 0.360 (9,14) 0.240 (6,10) 1 0.360 (9,14) 0.240 (6,10) 24 0.019 (0,48) 0.015 (0,38) 0.050 (1,27) 0.640 (16,26) 0.490 (12,45) 0.030 (0,76) 0.015 (0,38) 12 13 30 TYP 1.115 (28,32) 0.840 (21,34) 4040180-5 / B 03/95 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Falls within MIL-STD-1835 GDFP2-F24 and JEDEC MO-070AD Index point is provided on cap for terminal identification only. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 MECHANICAL DATA MLCC006B - OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 MECHANICAL DATA MSOI003E - JANUARY 1995 - REVISED SEPTEMBER 2001 DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 16 PINS SHOWN 0.020 (0,51) 0.014 (0,35) 9 0.050 (1,27) 16 0.010 (0,25) 0.419 (10,65) 0.400 (10,15) 0.010 (0,25) NOM 0.299 (7,59) 0.291 (7,39) Gage Plane 0.010 (0,25) 1 8 0- 8 0.050 (1,27) 0.016 (0,40) A Seating Plane 0.104 (2,65) MAX 0.012 (0,30) 0.004 (0,10) PINS ** 0.004 (0,10) 16 18 20 24 28 A MAX 0.410 (10,41) 0.462 (11,73) 0.510 (12,95) 0.610 (15,49) 0.710 (18,03) A MIN 0.400 (10,16) 0.453 (11,51) 0.500 (12,70) 0.600 (15,24) 0.700 (17,78) DIM 4040000/E 08/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MS-013 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 MECHANICAL DATA MSSO002E - JANUARY 1995 - REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0-8 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 MECHANICAL DATA MTSS001C - JANUARY 1995 - REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0- 8 A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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