Single-Supply, Rail-to-Rail,
Low Power, FET Input Op Amp
AD820
Rev. H
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FEATURES
True single-supply operation
Output swings rail-to-rail
Input voltage range extends below ground
Single-supply capability from 5 V to 30 V
Dual-supply capability from ±2.5 V to ±15 V
Excellent load drive
Capacitive load drive up to 350 pF
Minimum output current of 15 mA
Excellent ac performance for low power
800 μA maximum quiescent current
Unity-gain bandwidth: 1.8 MHz
Slew rate of 3 V/μs
Excellent dc performance
800 μV maximum input offset voltage
2 μV/°C typical offset voltage drift
25 pA maximum input bias current
Low noise: 13 nV/√Hz @ 10 kHz
APPLICATIONS
Battery-powered precision instrumentation
Photodiode preamps
Active filters
12-bit to 14-bit data acquisition systems
Medical instrumentation
Low power references and regulators
PIN CONFIGURATIONS
NC = NO CONNECT
NULL1
–IN 2
+IN 3
–VS4
NC
8
+VS
7
VOUT
6
NULL
5
AD820
TOP VIEW
(Not t o Scale)
00873-001
Figure 1. 8-Lead PDIP
NC = NO CONNECT
NC 1
–IN 2
+IN 3
–VS4
NC
8
+VS
7
VOUT
6
NC
5
AD820
TOP VIEW
(Not t o Scale)
00873-002
Figure 2. 8-Lead SOIC_N and 8-Lead MSOP
GENERAL DESCRIPTION
The AD820 is a precision, low power FET input op amp that
can operate from a single supply of 5 V to 36 V, or dual supplies
of ±2.5 V to ±18 V. It has true single-supply capability, with an
input voltage range extending below the negative rail, allowing
the AD820 to accommodate input signals below ground in the
single-supply mode. Output voltage swing extends to within
10 mV of each rail, providing the maximum output dynamic range.
Offset voltage of 800 μV maximum, offset voltage drift of
2 μV/°C, typical input bias currents below 25 pA, and low input
voltage noise provide dc precision with source impedances up
to 1 GΩ. 1.8 MHz unity gain bandwidth, −93 dB THD at
10 kHz, and 3 V/μs slew rate are provided for a low supply
current of 800 μA. The AD820 drives up to 350 pF of direct
capacitive load and provides a minimum output current of
15 mA. This allows the amplifier to handle a wide range of load
conditions. This combination of ac and dc performance, plus
the outstanding load drive capability, results in an exceptionally
versatile amplifier for the single-supply user.
The AD820 is available in two performance grades. The A and
B grades are rated over the industrial temperature range of
−40°C to +85°C. The AD820 is offered in three 8-lead package
options: plastic DIP (PDIP), surface mount (SOIC) and (MSOP).
00873-004
100
90
10
0%
1V1V
1V
20µs
Figure 3. Gain-of-2 Amplifier; VS = 5 V, 0 V, VIN = 2.5 V Sine Centered at 1.25 V
AD820
Rev. H | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Pin Configurations ........................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution .................................................................................. 9
Typical Performance Characteristics ........................................... 10
Applications Information .............................................................. 16
Input Characteristics .................................................................. 16
Output Characteristics............................................................... 17
Single-Supply Half-Wave and Full-Wave Rectifiers .............. 17
4.5 V Low Dropout, Low Power Reference ............................. 18
Low Power, 3-Pole, Sallen Key Low-Pass Filter ...................... 18
Offset Voltage Adjustment ............................................................ 19
Outline Dimensions ....................................................................... 20
Ordering Guide .......................................................................... 21
REVISION HISTORY
3/11—Rev. G to Rev. H
Changes to Figure 43 ...................................................................... 18
2/10—Rev. F to Rev. G
Changes to Features Section............................................................ 1
Changes to Open-Loop Gain Parameter ....................................... 3
Changes to Input Voltage Parameter ............................................. 9
Updated Outline Dimensions ....................................................... 20
11/08—Rev. E to Rev. F
Added 8-Lead MSOP ......................................................... Universal
Changes to Features Section, Figure 2 Caption, and General
Description Section .......................................................................... 1
Changes to Settling Time Parameter, Common-Mode Voltage
Range Parameter, and Power Supply Rejection Parameter in
Table 1 ................................................................................................ 3
Changes to Settling Time Parameter, Common-Mode Voltage
Range Parameter, and Power Supply Rejection Parameter in
Table 2 ................................................................................................ 5
Changes to Settling Time Parameter, Common-Mode Voltage
Range Parameter, and Power Supply Rejection Parameter in
Table 3 ................................................................................................ 7
Changes to Table 4 ............................................................................ 9
Added Thermal Resistance Section ............................................... 9
Added Table 5; Renumbered Sequentially ..................................... 9
Changes to Figure 26 ...................................................................... 13
Changes to Figure 27 ...................................................................... 14
Changed Application Notes Section to Applications
Information Section ....................................................................... 16
Changes to Figure 40, Figure 41, and Figure 42 ......................... 17
Changes to Figure 44 ...................................................................... 18
Moved Offset Voltage Adjustment Section ................................. 19
Updated Outline Dimensions ....................................................... 20
Added Figure 49; Renumbered Sequentially .............................. 21
Changes to Ordering Guide .......................................................... 21
2/07—Rev. D to Rev. E
Updated Format .................................................................. Universal
Updated Outline Dimensions ....................................................... 21
Changes to the Ordering Guide ................................................... 22
5/02—Rev. C to Rev. D
Change to SOIC Package (R-8) Drawing .................................... 15
Edits to Features................................................................................. 1
Edits to Product Description ........................................................... 1
Delete Specifications for AD820A-3 V ........................................... 5
Edits to Ordering Guide ................................................................... 6
Edits to Typical Performance Characteristics ................................ 8
AD820
Rev. H | Page 3 of 24
SPECIFICATIONS
VS = 0 V, 5 V @ TA = 25°C, VCM = 0 V, V OUT = 0.2 V, unless otherwise noted.
Table 1.
AD820A AD820B
Parameter Conditions Min Typ Max Min Typ Max Unit
DC PERFORMANCE
Initial Offset 0.1 0.8 0.1 0.4 mV
Maximum Offset over Temperature 0.5 1.2 0.5 0.9 mV
Offset Drift 2 2 μV/°C
Input Bias Current VCM = 0 V to 4 V 2 25 2 10 pA
At T
MAX
0.5 5 0.5 2.5 nA
Input Offset Current 2 20 2 10 pA
At TMAX 0.5 0.5 nA
Open-Loop Gain VOUT = 0.2 V to 4 V
RL = 100 kΩ 400 1000 500 1000 V/mV
TMIN to TMAX 400 400 V/mV
R
L
= 10 kΩ 80 150 80 150 V/mV
TMIN to TMAX 80 80 V/mV
RL = 1 kΩ 15 30 15 30 V/mV
TMIN to TMAX 10 10 V/mV
NOISE/HARMONIC PERFORMANCE
Input Voltage Noise
f = 0.1 Hz to 10 Hz 2 2 μV p-p
f = 10 Hz 25 25 nV/√Hz
f = 100 Hz 21 21 nV/√Hz
f = 1 kHz 16 16 nV/√Hz
f = 10 kHz 13 13 nV/√Hz
Input Current Noise
f = 0.1 Hz to 10 Hz 18 18 fA p-p
f = 1 kHz 0.8 0.8 fA/√Hz
Harmonic Distortion R
L
= 10 kΩ to 2.5 V
f = 10 kHz VOUT = 0.25 V to 4.75 V −93 −93 dB
DYNAMIC PERFORMANCE
Unity Gain Frequency 1.8 1.8 MHz
Full Power Response VOUT p-p = 4.5 V 210 210 kHz
Slew Rate 3 3 V/μs
Settling Time VOUT = 0.2 V to 4.5 V
To 0.1% 1.4 1.4 μs
To 0.01% 1.8 1.8 μs
INPUT CHARACTERISTICS
Common-Mode Voltage Range1
TMIN to TMAX −0.2 +4 –0.2 +4 V
CMRR VCM = 0 V to 2 V 66 80 72 80 dB
TMIN to TMAX 66 66 dB
Input Impedance
Differential 1013||0.5 1013||0.5 Ω||pF
Common Mode 1013||2.8 1013||2.8 Ω||pF
AD820
Rev. H | Page 4 of 24
AD820A AD820B
Parameter Conditions Min Typ Max Min Typ Max Unit
OUTPUT CHARACTERISTICS
Output Saturation Voltage2
VOL − VEE ISINK = 20 μA 5 7 5 7 mV
TMIN to TMAX 10 10 mV
VCC − VOH ISOURCE = 20 μA 10 14 10 14 mV
TMIN to TMAX 20 20 mV
VOL − VEE ISINK = 2 mA 40 55 40 55 mV
TMIN to TMAX 80 80 mV
VCC − VOH ISOURCE = 2 mA 80 110 80 110 mV
T
MIN
to T
MAX
160 160 mV
VOL − VEE ISINK = 15 mA 300 500 300 500 mV
TMIN to TMAX 1000 1000 mV
VCC − VOH ISOURCE = 15 mA 800 1500 800 1500 mV
TMIN to TMAX 1900 1900 mV
Operating Output Current 15 15 mA
TMIN to TMAX 12 12 mA
Short-Circuit Current 25 25 mA
Capacitive Load Drive 350 350 pF
POWER SUPPLY
Quiescent Current TMIN to TMAX 620 800 620 800 μA
Power Supply Rejection V+ = 5 V to 15 V 70 80 66 80 dB
TMIN to TMAX 70 66 dB
1 This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range ((V+) − 1 V) to V+. Common-mode error
voltage is typically less than 5 mV with the common-mode voltage set at 1 V below the positive supply.
2 VOL − VEE is defined as the difference between the lowest possible output voltage (VOL) and the negative voltage supply rail (VEE). VCC − VOH is defined as the difference
between the highest possible output voltage (VOH) and the positive supply voltage (VCC).
AD820
Rev. H | Page 5 of 24
VS = ±5 V @ TA = 25°C, VCM = 0 V, VOUT = 0 V, unless otherwise noted.
Table 2.
AD820A AD820B
Parameter Conditions Min Typ Max Min Typ Max Unit
DC PERFORMANCE
Initial Offset 0.1 0.8 0.3 0.4 mV
Maximum Offset over Temperature 0.5 1.5 0.5 1 mV
Offset Drift 2 2 μV/°C
Input Bias Current VCM = −5 V to +4 V 2 25 2 10 pA
At TMAX 0.5 5 0.5 2.5 nA
Input Offset Current 2 20 2 10 pA
At TMAX 0.5 0.5 nA
Open-Loop Gain V
OUT
= −4 V to +4 V
RL = 100 kΩ 400 1000 400 1000 V/mV
TMIN to TMAX 400 400 V/mV
RL = 10 kΩ 80 150 80 150 V/mV
TMIN to TMAX 80 80 V/mV
RL = 1 kΩ 20 30 20 30 V/mV
T
MIN
to T
MAX
10 10 V/mV
NOISE/HARMONIC PERFORMANCE
Input Voltage Noise
f = 0.1 Hz to 10 Hz 2 2 μV p-p
f = 10 Hz 25 25 nV/√Hz
f = 100 Hz 21 21 nV/√Hz
f = 1 kHz 16 16 nV/√Hz
f = 10 kHz 13 13 nV/√Hz
Input Current Noise
f = 0.1 Hz to 10 Hz 18 18 fA p-p
f = 1 kHz 0.8 0.8 fA/√Hz
Harmonic Distortion RL = 10 kΩ
f = 10 kHz VOUT = ±4.5 V −93 −93 dB
DYNAMIC PERFORMANCE
Unity Gain Frequency 1.9 1.8 MHz
Full Power Response VOUT p-p = 9 V 105 105 kHz
Slew Rate 3 3 V/μs
Settling Time VOUT = 0 V to ±4.5 V
To 0.1% 1.4 1.4 μs
To 0.01% 1.8 1.8 μs
INPUT CHARACTERISTICS
Common-Mode Voltage Range1
T
MIN
to T
MAX
−5.2 +4 −5.2 +4 V
CMRR VCM = −5 V to +2 V 66 80 72 80 dB
TMIN to TMAX 66 66 dB
Input Impedance
Differential 1013||0.5 1013||0.5 Ω||pF
Common Mode 1013||2.8 1013||2.8 Ω||pF
AD820
Rev. H | Page 6 of 24
AD820A AD820B
Parameter Conditions Min Typ Max Min Typ Max Unit
OUTPUT CHARACTERISTICS
Output Saturation Voltage2
VOL − VEE ISINK = 20 μA 5 7 5 7 mV
TMIN to TMAX 10 10 mV
VCC − VOH ISOURCE = 20 μA 10 14 10 14 mV
TMIN to TMAX 20 20 mV
VOL − VEE ISINK = 2 mA 40 55 40 55 mV
TMIN to TMAX 80 80 mV
VCC − VOH ISOURCE = 2 mA 80 110 80 110 mV
T
MIN
to T
MAX
160 160 mV
VOL − VEE ISINK = 15 mA 300 500 300 500 mV
TMIN to TMAX 1000 1000 mV
VCC − VOH ISOURCE = 15 mA 800 1500 800 1500 mV
TMIN to TMAX 1900 1900 mV
Operating Output Current 15 15 mA
T
MIN
to T
MAX
12 12 mA
Short-Circuit Current 30 30 mA
Capacitive Load Drive 350 350 pF
POWER SUPPLY
Quiescent Current TMIN to TMAX 650 800 620 800 μA
Power Supply Rejection V+ = 5 V to 15 V 70 80 70 80 dB
TMIN to TMAX 70 70 dB
1 This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range ((V+) − 1 V) to V+. Common-mode error
voltage is typically less than 5 mV with the common-mode voltage set at 1 V below the positive supply.
2 VOL − VEE is defined as the difference between the lowest possible output voltage (VOL) and the negative voltage supply rail (VEE). VCC − VOH is defined as the difference
between the highest possible output voltage (VOH) and the positive supply voltage (VCC).
AD820
Rev. H | Page 7 of 24
VS = ±15 V @ TA = 25°C, VCM = 0 V, VOUT = 0 V, unless otherwise noted.
Table 3.
AD820A AD820B
Parameter Conditions Min Typ Max Min Typ Max Unit
DC PERFORMANCE
Initial Offset 0.4 2 0.3 1.0 mV
Maximum Offset over Temperature 0.5 3 0.5 2 mV
Offset Drift 2 2 μV/°C
Input Bias Current V
CM
= 0 V 2 25 2 10 pA
VCM = −10 V 40 40 pA
At TMAX VCM = 0 V 0.5 5 0.5 2.5 nA
Input Offset Current 2 20 2 10 pA
At TMAX 0.5 0.5 nA
Open-Loop Gain VOUT = −10 V to +10 V
R
L
= 100 kΩ 500 2000 500 2000 V/mV
TMIN to TMAX 500 500 V/mV
RL = 10 kΩ 100 500 100 500 V/mV
TMIN to TMAX 100 100 V/mV
RL = 1 kΩ 30 45 30 45 V/mV
TMIN to TMAX 20 20 V/mV
NOISE/HARMONIC PERFORMANCE
Input Voltage Noise
f = 0.1 Hz to 10 Hz 2 2 μV p-p
f = 10 Hz 25 25 nV/√Hz
f = 100 Hz 21 21 nV/√Hz
f = 1 kHz 16 16 nV/√Hz
f = 10 kHz 13 13 nV/√Hz
Input Current Noise
f = 0.1 Hz to 10 Hz 18 18 fA p-p
f = 1 kHz 0.8 0.8 fA/√Hz
Harmonic Distortion RL = 10 kΩ
f = 10 kHz VOUT = ±10 V −85 −85 dB
DYNAMIC PERFORMANCE
Unity Gain Frequency 1.9 1.9 MHz
Full Power Response VOUT p-p = 20 V 45 45 kHz
Slew Rate 3 3 V/μs
Settling Time VOUT = 0 V to ±10 V
To 0.1% 4.1 4.1 μs
To 0.01% 4.5 4.5 μs
INPUT CHARACTERISTICS
Common-Mode Voltage Range1
TMIN to TMAX −15.2 +14 −15.2 +14 V
CMRR VCM = –15 V to +12 V 70 80 74 90 dB
T
MIN
to T
MAX
70 74 dB
Input Impedance
Differential 1013||0.5 1013||0.5 Ω||pF
Common Mode 1013||2.8 1013||2.8 Ω||pF
AD820
Rev. H | Page 8 of 24
AD820A AD820B
Parameter Conditions Min Typ Max Min Typ Max Unit
OUTPUT CHARACTERISTICS
Output Saturation Voltage2
VOL − VEE ISINK = 20 μA 5 7 5 7 mV
TMIN to TMAX 10 10 mV
VCC − VOH ISOURCE = 20 μA 10 14 10 14 mV
TMIN to TMAX 20 20 mV
V
OL
− V
EE
I
SINK
= 2 mA 40 55 40 55 mV
TMIN to TMAX 80 80 mV
VCC − VOH ISOURCE = 2 mA 80 110 80 110 mV
TMIN to TMAX 160 160 mV
VOL − VEE ISINK = 15 mA 300 500 300 500 mV
T
MIN
to T
MAX
1000 1000 mV
VCC − VOH ISOURCE = 15 mA 800 1500 800 1500 mV
TMIN to TMAX 1900 1900 mV
Operating Output Current 20 20 mA
TMIN to TMAX 15 15 mA
Short-Circuit Current 45 45 mA
Capacitive Load Drive 350 350 pF
POWER SUPPLY
Quiescent Current TMIN to TMAX 700 900 700 900 μA
Power Supply Rejection V+ = 5 V to 15 V 70 80 70 80 dB
T
MIN
to T
MAX
70 70 dB
1 This is a functional specification. Amplifier bandwidth decreases when the input common-mode voltage is driven in the range ((V+) − 1 V) to V+. Common-mode error
voltage is typically less than 5 mV with the common-mode voltage set at 1 V below the positive supply.
2 VOL − VEE is defined as the difference between the lowest possible output voltage (VOL) and the negative voltage supply rail (VEE). VCC − VOH is defined as the difference
between the highest possible output voltage (VOH) and the positive supply voltage (VCC).
AD820
Rev. H | Page 9 of 24
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
Supply Voltage ±18 V
Internal Power Dissipation
8-Lead PDIP (N) 1.6 W
8-Lead SOIC_N (R) 1.0 W
8-Lead MSOP (RM) 0.8 W
Input Voltage1 ((V+) + 0.2 V) to
(V−) − 20 V
Output Short-Circuit Duration Indefinite
Differential Input Voltage ±30 V
Storage Temperature Range
8-Lead PDIP (N) −65°C to +125°C
8-Lead SOIC_N (R) −65°C to +150°C
8-Lead MSOP (RM) −65°C to +150°C
Operating Temperature Range
AD820A/AD820B −40°C to +85°C
Lead Temperature(Soldering, 60 sec) 260°C
1 See Input Characteristics section.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 5. Thermal Resistance
Package Type θJA Unit
8-Lead PDIP (N) 90 °C/W
8-Lead SOIC_N (R) 160 °C/W
8-Lead MSOP (RM) 190 °C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD820
Rev. H | Page 10 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
50
0
–0.5 0.5
OFFSET VOLTAGE (mV)
NUMBER OF UNIT S
00873-005
40
30
20
10
–0.4 –0.3 –0.2 –0.1 00.1 0.2 0.3 0.4
V
S
= 0V, 5V
Figure 4. Typical Distribution of Offset Voltage (248 Units)
48
0
–10 10
OFFSET VOLTAGE DRIFT (µV/ºC)
% IN BIN
00873-006
40
32
24
16
8
–8 –6 –4 –2 02468
V
S
= ±5V
V
S
= ±15V
Figure 5. Typical Distribution of Offset Voltage Drift (120 Units)
50
0010
INP UT BIAS CURRE NT (pA)
NUMBER OF UNIT S
00873-007
45
40
35
30
25
20
15
10
5
123456789
Figure 6. Typical Distribution of Input Bias Current (213 Units)
5
–5–5 5
COMMON-MODE VOLT AGE (V)
INP UT BIAS CURRE NT (pA)
00873-008
0
–4 –3 –2 –1 01234
V
S
= ±5V
V
S
= 0V, + 5V AND ± 5V
Figure 7. Input Bias Current vs. Common-Mode Voltage;
VS = +5 V, 0 V and VS = ±5 V
1k
0.1
–16 16
COMMON-MODE VOLT AGE (V)
INP UT BIAS CURRE NT (pA)
00873-009
1
10
100
–12 –8 –4 04812
Figure 8. Input Bias Current vs. Common-Mode Voltage; VS = ±15 V
100k
0.120 140
TEMPERATURE (ºC)
INP UT BIAS CURRE NT (pA)
00873-010
1
10
100
1k
10k
40 60 80 100 120
Figure 9. Input Bias Current vs. Temperature; VS = 5 V, VCM = 0 V
AD820
Rev. H | Page 11 of 24
10M
10k
100 100k
LOAD RESISTANCE (Ω)
OPEN-LOO P G AIN (V/V)
00873-011
1k 10k
100k
1M V
S
= ±15V
V
S
= 0V, + 5V
Figure 10. Open-Loop Gain vs. Load Resistance
10M
10k
–60 140
TEMPERATURE (ºC)
OPEN-LOO P G AIN (V/V)
00873-012
100k
1M
–40 –20 020 40 60 80 100 120
V
S
= ±15V
R
L
= 100kΩ
R
L
= 10kΩ
V
S
= 0V, + 5V
V
S
= ±15V
V
S
= 0V, + 5V
V
S
= ±15V
V
S
= 0V, + 5V
R
L
= 600Ω
Figure 11. Open-Loop Gain vs. Temperature
300
–300
–16 16
OUTPUT VOLTAGE (V)
INPUT ERROR VOLTAGE (µV)
00873-013
200
100
0
–100
–200
–12 –8 –4 04812
R
L
= 100kΩ
R
L
= 600Ω
R
L
= 10kΩ
Figure 12. Input Error Voltage vs. Output Voltage for Resistive Loads
40
–40 0300
OUTPUT VOLTAGE FROM RAILS (mV)
INPUT ERROR VOLTAGE (µV)
00873-014
20
0
–20
60 120 180 240
R
L
= 100kΩ
R
L
= 20kΩ
R
L
= 2kΩ
POSITIVE
RAIL
POSITIVE
RAIL
POSITIVE
RAIL
NEGATIVE
RAIL
NEGATIVE
RAIL
NEG ATIV E RAIL
Figure 13. Input Error Voltage vs. Output Voltage Within 300 mV of Either
Supply Rail for Various Resistive Loads; VS = ±5 V
1k
1110k
FRE QUENCY ( Hz )
INPUT VOLTAGE NOISE (nV/√Hz)
00873-015
10 100 1k
10
100
Figure 14. Input Voltage Noise vs. Frequency
–40
–110
100 100k
FRE QUENCY ( Hz )
THD ( dB)
00873-016
1k 10k
–50
–60
–70
–80
–90
–100
R
L
= 10kΩ
A
CL
= –1
V
S
= ±15V; V
OUT
= 20V p - p
V
S
= ±5V; V
OUT
= 9V p-p
V
S
= 0V, +5V; V
OUT
= 4.5V p-p
Figure 15. Total Harmonic Distortion vs. Frequency
AD820
Rev. H | Page 12 of 24
00873-017
100
–2010 10M
FRE QUENCY ( Hz )
OPEN-LOOP GAIN (dB)
100 1k 10k 100k 1M
80
60
40
20
0
PHASE MARGIN (DEGREES)
100
–20
80
60
40
20
0
GAIN
PHASE
R
L
= 2kΩ
C
L
= 100pF
Figure 16. Open-Loop Gain and Phase Margin vs. Frequency
1k
0.01
100 10M
FRE QUENCY ( Hz )
OUTPUT IMPEDANCE (Ω)
00873-018
1k 10k 100k 1M
0.1
1
10
100
A
CL
= +1
V
S
= ±15V
Figure 17. Output Impedance vs. Frequency
16
–16 0 5
SETTLING TIME (µs)
OUTPUT SWING FROM 0 TO ±V
00873-019
12
8
4
0
–4
–8
–12
1234
1%
1%
0.1% 0.01% ERROR
Figure 18. Output Swing and Error vs. Settling Time
100
010 10M
FRE QUENCY ( Hz )
COM M ON-MODE RE JE CTI ON (dB)
00873-020
100 1k 10k 100k 1M
90
80
70
60
50
40
30
20
10
V
S
= 0V, + 5V V
S
= ±15V
Figure 19. Common-Mode Rejection vs. Frequency
5
0–1 3
COMMON-MODE VOLT AGE F ROM SUPPLY RAILS (V)
COMMON-MODE ERROR VOLTAGE (mV)
00873-021
4
3
2
1
012
NEGATIVE
RAIL POSITIVE
RAIL
+25ºC
–55ºC –55ºC
+125ºC +125ºC
Figure 20. Absolute Common-Mode Error vs. Common-Mode Voltage
from Supply Rails (VS − VCM)
1k
1
0.001 100
LOAD CURRENT ( mA)
OUTPUT SATURATION VOLTAGE (mV)
00873-022
0.01 0.1 110
10
100
V
S
– V
OH
V
OL
– V
S
Figure 21. Output Saturation Voltage vs. Load Current
AD820
Rev. H | Page 13 of 24
1k
1
–60 140
TEMPERATURE (ºC)
OUTPUT SATURATION VOLTAGE (mV)
00873-023
–40 –20 020 40 60 80 100 120
10
100
I
SOURCE
= 10mA
I
SINK
= 10mA
I
SOURCE
= 10µA
I
SINK
= 10µA
I
SOURCE
= 1mA
I
SINK
= 1mA
Figure 22. Output Saturation Voltage vs. Temperature
80
0
–60 140
TEMPERATURE (ºC)
SHO RT-CI RCUIT CURRE NT L IMIT ( mA)
00873-024
–40 –20 020 40 60 80 100 120
70
60
50
40
30
20
10
V
S
= ±15V
V
S
= ±15V
V
S
= 0V, + 5V
V
S
= 0V, + 5V
–OUT
–
+
+
Figure 23. Short-Circuit Current Limit vs. Temperature
800
0036
TOTAL SUPPLY VOLTAGE (V)
QUIESCE NT CURRENT (µ A)
00873-025
700
600
500
400
300
200
100
4 8 12 16 20 24 28 32
T = + 25ºC
T = + 125ºC
T = –55ºC
Figure 24. Quiescent Current vs. Supply Voltage over Different Temperatures
120
010 10M
FRE QUENCY ( Hz )
POWER SUPPLY REJECTION (dB)
00873-026
100 1k 10k 100k 1M
110
100
90
80
70
60
50
40
30
20
10
+PSRR
–PSRR
Figure 25. Power Supply Rejection vs. Frequency
30
0
10k 10M
FRE QUENCY ( Hz )
OUTPUT VOLTAGE (V)
00873-027
100k 1M
25
20
15
10
5
V
S
= ±15V
R
L
= 2kΩ
V
S
= 0V, + 5V
Figure 26. Large Signal Frequency Response
AD820
Rev. H | Page 14 of 24
00873-028
AD820
–
+
–
+
+VS
–VS
RL100pF
0.01µF
0.01µF VOUT
VIN
3
2
4
7
6
–
+
Figure 27. Unity-Gain Follower, Used for Figure 28 Through Figure 32
00873-029
100
90
10
0%
5V 10µs
Figure 28. 20 V, 25 kHz Sine Input; Unity-Gain Follower; RL = 600 Ω, V
S = ±15 V
00873-030
100
90
10
0%
1V 2µs
GND
Figure 29. VS = 5 V, 0 V; Unity-Gain Follower Response to 0 V to 4 V Step
00873-031
100
90
10
0%
5V 5µs
Figure 30. Large Signal Response Unity-Gain Follower; VS = ±15 V, RL = 10 kΩ
00873-032
100
90
10
0%
10mV 500ns
Figure 31. Small Signal Response Unity-Gain Follower; VS = ±15 V, RL = 10 kΩ
00873-033
100
90
10
0%
1V 2µs
GND
Figure 32. VS = 5 V, 0 V; Unity-Gain Follower Response to 0 V to 5 V Step
AD820
Rev. H | Page 15 of 24
00873-034
AD820
–
+
+V
S
R
L
100pF
0.01µF
V
OUT
V
IN
3
2
4
7
6
–
+
Figure 33. Unity-Gain Follower, Used for Figure 34
00873-037
100
90
10
0%
10mV 2µs
GND
Figure 34. VS = 5 V, 0 V; Unity-Gain Follower Response to 40 mV Step
Centered 40 mV Above Ground
00873-035
AD820
–
+
+V
S
R
L
100pF
0.01µF
V
IN
2
3
4
7
6
V
OUT
–
+
10kΩ 20kΩ
Figure 35. Gain-of-2 Inverter, Used for Figure 36 and Figure 37
00873-036
100
90
10
0%
1V 2µS
GND
Figure 36. VS = 5 V, 0 V; Gain-of-2 Inverter Response to 2.5 V Step,
Centered −1.25 V Below Ground
00873-038
100
90
10
0%
10mV 2µs
GND
Figure 37. VS = 5 V, 0 V; Gain-of-2 Inverter Response to 20 mV Step, Centered
20 mV Below Ground
AD820
Rev. H | Page 16 of 24
APPLICATIONS INFORMATION
INPUT CHARACTERISTICS
In the AD820, N-channel JFETs are used to provide a low offset,
low noise, high impedance input stage. Minimum input common-
mode voltage extends from 0.2 V below –VS to 1 V less than
+VS. Driving the input voltage closer to the positive rail causes a
loss of amplifier bandwidth (as can be seen by comparing the
large signal responses shown in Figure 29 and Figure 32) and
increased common-mode voltage error, as illustrated in
Figure 20.
The AD820 does not exhibit phase reversal for input voltages
up to and including +VS. Figure 38a shows the response of an
AD820 voltage follower to a 0 V to 5 V (+VS) square wave input.
The input and output are superimposed. The output polarity
tracks the input polarity up to +VS with no phase reversal. The
reduced bandwidth above a 4 V input causes the rounding of
the output waveform. For input voltages greater than +VS, a
resistor in series with the AD820 positive input prevents phase
reversal, at the expense of greater input voltage noise. This is
illustrated in Figure 38b.
Because the input stage uses N-channel JFETs, input current
during normal operation is negative; the current flows out from
the input terminals. If the input voltage is driven more positive
than +VS − 0.4 V, the input current reverses direction as internal
device junctions become forward biased. This is illustrated in
Figure 7.
A current-limiting resistor should be used in series with the
input of the AD820 if there is a possibility of the input voltage
exceeding the positive supply by more than 300 mV, or if an
input voltage is applied to the AD820 when ±VS = 0 V. The
amplifier can be damaged if left in that condition for more than
10 seconds. A 1 kΩ resistor allows the amplifier to withstand up
to 10 V of continuous overvoltage, and increases the input
voltage noise by a negligible amount.
Input voltages less than −VS are a completely different story.
The amplifier can safely withstand input voltages 20 V below
the negative supply voltage as long as the total voltage from
the positive supply to the input terminal is less than 36 V. In
addition, the input stage typically maintains picoamp level
input currents across that input voltage range.
The AD820 is designed for 13 nV/√Hz wideband input voltage
noise and maintains low noise performance to low frequencies
(refer to Figure 14). This noise performance, along with the
AD820 low input current and current noise, means that the
AD820 contributes negligible noise for applications with source
resistances greater than 10 kΩ and signal bandwidths greater
than 1 kHz. This is illustrated in Figure 39.
00873-039
100
90
10
0%
1V 1V
1V
10µs
GND
+V
S
100
90
10
0%
1V
1V
2µs
GND
AD820
–
+
5V
R
P
V
OUT
–
+
V
IN
–
+
(b)
(a)
Figure 38. (a) Response with RP = 0 Ω; VIN from 0 V to +VS
(b) VIN = 0 V to +VS + 200 mV,
VOUT = 0 V to +VS, RP = 49.9 kΩ
100k
0.1
10k 10G
SOURCE IMPEDANCE (Ω)
INPUT VOLTAGE NOISE (µV rms)
00873-040
10k
1k
100
10
1
100k 1M 10M 100M 1G
WHE NE V E R JOHNSO N NOI S E IS GREATER T HAN
AMPLIFIER NOISE, AMPLIFIER NOISE CAN BE
CONSIDERED NEGLIGIBLE FOR APPLICATION.
RESIST OR JO HNS ON
NOISE
1kHz
10Hz
AMPLIFIER-GENERATED
NOISE
Figure 39. Total Noise vs. Source Impedance
AD820
Rev. H | Page 17 of 24
OUTPUT CHARACTERISTICS
The AD820 unique bipolar rail-to-rail output stage swings
within 5 mV of the negative supply and 10 mV of the positive
supply with no external resistive load. The approximate output
saturation resistance of the AD820 is 40 Ω sourcing and 20 Ω
sinking. This can be used to estimate output saturation voltage
when driving heavier current loads. For instance, when sourcing
5 mA, the saturation voltage to the positive supply rail is 200 mV;
when sinking 5 mA, the saturation voltage to the negative rail
is 100 mV.
The open-loop gain characteristic of the amplifier changes
as a function of resistive load, as shown in Figure 10 through
Figure 13. For load resistances over 20 kΩ, the AD820 input
error voltage is virtually unchanged until the output voltage is
driven to 180 mV of either supply.
If the AD820 output is driven hard against the output saturation
voltage, it recovers within 2 μs of the input returning to the
linear operating region of the amplifier.
Direct capacitive load interacts with the effective output imped-
ance of the amplifier to form an additional pole in the amplifier
feedback loop, which can cause excessive peaking on the pulse
response or loss of stability. The worst case occurs when the
amplifier is used as a unity-gain follower. Figure 40 shows
AD820 pulse response as a unity-gain follower driving 350 pF.
This amount of overshoot indicates approximately 20 degrees
of phase margin—the system is stable, but is nearing the edge.
Configurations with less loop gain, and as a result less loop
bandwidth, are much less sensitive to capacitance load effects.
Figure 41 is a plot of noise gain vs. the capacitive load that results
in a 20 degree phase margin for the AD820. Noise gain is the
inverse of the feedback attenuation factor provided by the
feedback network in use.
00873-041
20mV 2µs
100
90
10
0%
Figure 40. Small Signal Response of AD820 as Unity-Gain Follower Driving
350 pF Capacitive Load
00873-042
5
1
300 30k
CAPACITIVE LOAD FOR 20º PHASE MARGIN (pF)
NOISE GAIN (1+ )
P
I
P
F
4
3
2
1k 3k 10k
–
+
R
F
R1
Figure 41. Noise Gain vs. Capacitive Load Tolerance
Figure 42 shows a possible configuration for extending
capacitance load drive capability for a unity-gain follower. With
these component values, the circuit drives 5000 pF with a 10%
overshoot.
0
0873-043
AD820
–
+
–
+
+
V
S
–V
S
0.01µF
0.01µF
20pF
20kΩ
100Ω
V
OUT
V
IN
3
2
4
7
6
–
+
Figure 42. Extending Unity-Gain Follower Capacitive Load Capability
Beyond 350 pF
SINGLE-SUPPLY HALF-WAVE AND FULL-WAVE
RECTIFIERS
An AD820 configured as a unity-gain follower and operated
with a single supply can be used as a simple half-wave rectifier.
The AD820 inputs maintain picoamp level input currents even
when driven well below the negative supply. The rectifier puts
that behavior to good use, maintaining an input impedance of
over 1011 Ω for input voltages from 1 V from the positive supply
to 20 V below the negative supply.
The full- and half-wave rectifier shown in Figure 43 operates as
follows: when VIN is above ground, R1 is bootstrapped through
the unity-gain follower, A1, and the loop of Amplifier A2. This
forces the inputs of A2 to be equal; thus, no current flows through
R1 or R2, and the circuit output tracks the input. When VIN is
below ground, the output of A1 is forced to ground. The
AD820
Rev. H | Page 18 of 24
noninverting input of Amplifier A2 sees the ground level output
of A1; therefore, A2 operates as a unity-gain inverter. The output at
Node C is then a full-wave rectified version of the input. Node B is
a buffered half-wave rectified version of the input. Input voltages
up to ±18 V can be rectified, depending on the voltage supply used.
00873-045
A1
–
+
–
+
+VS
0.01µF
R1
100kΩ R2
100kΩ
AD820
FULL-WAVE
RECTIF IED OUPUT
VIN
3
AC
2
4
7
6
–
+
–
+
HALF-WAVE
RECTIF IED OUPUT
–
+B
A
B
C
100
90
10
0%
A2
+VS0.01µF
AD820
3
2
4
7
6
Figure 43. Single-Supply Half- and Full-Wave Rectifier
4.5 V LOW DROPOUT, LOW POWER REFERENCE
The rail-to-rail performance of the AD820 can be used to
provide low dropout performance for low power reference
circuits powered with a single low voltage supply. Figure 44
shows a 4.5 V reference using the AD820 and the AD680, a low
power 2.5 V band gap reference. R2 and R3 set up the required
gain of 1.8 to develop the 4.5 V output. R1 and C2 form a low-
pass RC filter to reduce the noise contribution of the AD680.
00873-046
R2
90kΩ
(20kΩ)
R1
100kΩ R3
100kΩ
(25kΩ)
U2
AD820
–
+
2.5V
OUTPUT
4.5V
OUTPUT
5V
REF
COMMON
C3
10µF/25V
U1
AD680
C2
0.1µF FILM
3 2
4
4
7
6
2
63 2.5V ± 10mV
C1
0.1µF
Figure 44. Single Supply 4.5 V Low Dropout Reference
With a 1 mA load, this reference maintains the 4.5 V output
with a supply voltage down to 4.7 V. The amplitude of the
recovery transient for a 1 mA to 10 mA step change in load
current is under 20 mV, and settles out in a few microseconds.
Output voltage noise is less than 10 μV rms in a 25 kHz noise
bandwidth.
LOW POWER, 3-POLE, SALLEN KEY LOW-PASS
FILTER
The high input impedance of the AD820 makes it a good
selection for active filters. High value resistors can be used to
construct low frequency filters with capacitors much less than
1 μF. The AD820 picoamp level input currents contribute
minimal dc errors.
Figure 45 shows an example of a 10 Hz three-pole Sallen Key
filter. The high value used for R1 minimizes interaction with
signal source resistance. Pole placement in this version of the
filter minimizes the Q associated with the two-pole section of
the filter. This eliminates any peaking of the noise contribution
of Resistor R1, Resistor R2, and Resistor R3, thus minimizing
the inherent output voltage noise of the filter.
AD820
–
+
+V
S
–V
S
0.01µF
0.01µF V
OUT
3
2
4
7
6
–
+
R3
243kΩ
C3
0.022µF
–
+
V
IN
R2
243kΩ
R1
243kΩ
C1
0.022µF
C2
0.022µF
0
–100
0.1 1k
FREQUENCY ( Hz )
FILTER GAIN RESPONSE (dB)
00873-047
110 100
–10
–20
–30
–40
–50
–60
–70
–80
–90
Figure 45. 10 Hz Sallen Key Low-Pass Filter
AD820
Rev. H | Page 19 of 24
OFFSET VOLTAGE ADJUSTMENT
The offset voltage of the AD820 is low, so external offset voltage
nulling is not usually required. Figure 46 shows the recommended
technique for the AD820 packaged in plastic DIP. Adjusting offset
voltage in this manner changes the offset voltage temperature drift
by 4 μV/°C for every millivolt of induced offset. The null pins
are not functional for the AD820 in the 8-lead SOIC and MSOP
packages.
00873-044
AD820
–
+
+V
S
3
2
–V
S
4
7
5
6
1
20kΩ
Figure 46. Offset Null
AD820
Rev. H | Page 20 of 24
OUTLINE DIMENSIONS
COMPLIANT TO JE DE C S TANDARDS MS - 001
CONTROLLING DIMENSIONSARE IN INCHES; MILLI MET ER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED- OFF I NCH E QUIVALENTS FOR
REF E RE NCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNE R LEADS MAY BE CONF IG URE D AS WHOLE OR HALF L E ADS .
070606-A
0.022 ( 0.56)
0.018 ( 0.46)
0.014 ( 0.36)
SEATING
PLANE
0.015
(0.38)
MIN
0.210 ( 5.33)
MAX
0.150 ( 3.81)
0.130 ( 3.30)
0.115 (2.92)
0.070 ( 1.78)
0.060 ( 1.52)
0.045 ( 1.14)
8
14
5
0.280 ( 7.11)
0.250 ( 6.35)
0.240 ( 6.10)
0.100 ( 2.54)
BSC
0.400 ( 10.16)
0.365 ( 9.27)
0.355 ( 9.02)
0.060 ( 1.52)
MAX
0.430 ( 10.92)
MAX
0.014 ( 0.36)
0.010 ( 0.25)
0.008 ( 0.20)
0.325 ( 8.26)
0.310 ( 7.87)
0.300 ( 7.62)
0.195 ( 4.95)
0.130 ( 3.30)
0.115 (2.92)
0.015 ( 0.38)
GAUGE
PLANE
0.005 ( 0.13)
MIN
Figure 47. 8-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-8)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN D
ESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
8 5
5.00(0.1968)
4.80(0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 48. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
AD820
Rev. H | Page 21 of 24
COMPLIANT TO JEDEC STANDARDS MO-187-AA
6°
0°
0.80
0.55
0.40
4
8
1
5
0.65 BSC
0.40
0.25
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.09
3.20
3.00
2.80
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
10-07-2009-B
Figure 49. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1Temperature Range Package Description Package Option Branding
AD820AN −40°C to +85°C 8-Lead PDIP N-8
AD820ANZ −40°C to +85°C 8-Lead PDIP N-8
AD820AR −40°C to +85°C 8-Lead SOIC_N R-8
AD820AR-REEL −40°C to +85°C 8-Lead SOIC_N R-8
AD820AR-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8
AD820ARZ −40°C to +85°C 8-Lead SOIC_N R-8
AD820ARZ-REEL −40°C to +85°C 8-Lead SOIC_N R-8
AD820ARZ-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8
AD820ARMZ −40°C to +85°C 8-Lead MSOP RM-8 A2L
AD820ARMZ-RL −40°C to +85°C 8-Lead MSOP RM-8 A2L
AD820ARMZ-R7 −40°C to +85°C 8-Lead MSOP RM-8 A2L
AD820BR −40°C to +85°C 8-Lead SOIC_N R-8
AD820BR-REEL −40°C to +85°C 8-Lead SOIC_N R-8
AD820BRZ −40°C to +85°C 8-Lead SOIC_N R-8
AD820BRZ-REEL −40°C to +85°C 8-Lead SOIC_N R-8
AD820BRZ-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8
1 Z = RoHS Compliant Part.
AD820
Rev. H | Page 22 of 24
NOTES
AD820
Rev. H | Page 23 of 24
NOTES
AD820
Rev. H | Page 24 of 24
NOTES
©1996–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00873-0-3/11(H)
