VECANA01 VECA NA01 www.ti.com 10-Channel, 12-Bit DATA ACQUISITION SYSTEM FEATURES APPLICATIONS 10 FULLY DIFFERENTIAL INPUTS 5 SIMULTANEOUS SAMPLED CHANNELS PLUS 2 SYNCHRONIZED SAMPLING CHANNELS 3 SYNCHRONIZED 12-BIT ADCs AC MOTOR SPEED CONTROLS THREE PHASE POWER CONTROL UNINTERRUPTABLE POWER SUPPLIES VIBRATION ANALYSIS 12.8s THROUGHPUT RATE DIGITALLY SELECTABLE INPUT RANGES 2 IUP/N 5V POWER SUPPLIES SERIAL DIGITAL INPUT/OUTPUTS 7 SIGN AND 3 DIGITALLY PROGRAMMABLE WINDOW COMPARATOR 2 A1P/N SH1 PGA1 ADC1 12-Bit ADOUT1 SH2 PGA2 ADC2 12-Bit ADOUT2 SH3 PGA3 ADC3 12-Bit ADOUT3 2 A2P/N MUX1 2 IVP/N 2 B1P/N DESCRIPTION 2 B2P/N The VECANA01 consists of three 12-bit analog-todigital converters preceded by five simultaneously operating sample-hold amplifiers, and multiplexers for 10 differential inputs. The ADCs have simultaneous serial outputs for high speed data transfer and data processing. The VECANA01 also offers a programmable gain amplifier with programmable gains of 1.0V/V, 1.25V/V, 2.5V/V, and 5.0V/V. Channel selection and gain selection are selectable through the serial input control word. The high through put rate is maintained by simultaneously clocking in the 13-bit input control word for the next conversion while the present conversions are clocked out. MUX2 2 IWP/N 2 AN1P/N AN2P/N 2 2 AN3P/N MUX3 2.5V Ref Input Select Control Logic Input Setup Register DAC REFOUT The part also contains an 8-bit digital-to-analog converter whose digital input is supplied as part of the input control word. Gain Select ADIN DAC 8-Bit DAOUT ADCLK ADCONV ADBUSY 7 7 COMP 3 ILIM DAIN Copyright (c) 2000, Texas Instruments Incorporated SBAS155 Printed in U.S.A. October, 2000 SPECIFICATIONS At VANA+ = +5V, VANA- = -5V, VDIG+ = +5V, VDIG- = -5V, and TA = -40C to +85C, using internal reference, fCLOCK = 1.25MHz. ANALOG-TO-DIGITAL CONVERTER CHANNELS VECANA01N PARAMETER CONDITIONS RESOLUTION ANALOG INPUT Full Scale Voltage, Differential G = 1.0V/V G = 1.25V/V G = 2.5V/V G = 5.0V/V 0.5 Zero Error - ADC Zero Error - Asynchronous, Synchronous Zero Error Drift AC ACCURACY Total Harmonic Distortion fIN = 1kHz fIN = 1MHz CMR DIGITAL OUTPUTS Data Format Data Coding VOL VOH Leakage Current Output Capacitance 2 2.5 2.0 1.0 0.5 See Table VII 1012 20 10.4 12.8 0.5 0.5 2 2 0.5 0.5 3 3 2 4 100 100 15 20 12 G = 1.0V/V = = = = = 10 10 0.5 0.5 0.5 1.0V/V 2.5V/V 1.0V/V 1.0V/V 1.0V/V 92 70 50 VCM = 0.5V, fCM = 1MHz 2.25 2.5 0.25 10 10 2.5 At All Digital Input Pins LSB LSB Bits LSB LSB % of FSR % of FSR ppm/C ppm/C LSB LSB ppm/C dB dB dB 2 2.75 V % ppm/C A V A 10 0 +3.5 s s kHz V/s s ns ps ns 0.1 0.5 50 50 3 G G G G G UNITS V V V V V pF 78 REFERENCE Internal Reference Voltage Internal Reference Accuracy Internal Reference Drift Internal Reference Source Current External Reference Voltage Range for Specified Linearity External Reference Current Drain DIGITAL INPUTS Logic Levels VIL VIH IIL IIH Input Capacitance MAX Bit CLK = 1.25MHz Acquire and Convert SAMPLING DYNAMICS S/H Droop Rate S/H Acquisition Time S/H Aperture Delay S/H Aperture Jitter Sampling Skew, Channel-to-Channel DC ACCURACY Integral Linearity - ADC Differential Linearity - ADC No Missing Codes Integral Linearity - Asynchronous, Synchronous Differential Linearity - Asynchronous, Synchronous Full Scale Error Full Scale Error Other Gains Full Scale Error Drift TYP 12 Common-Mode Voltage Impedance Capacitance THROUGHPUT SPEED Conversion Time Complete Cycle Throughput Rate MIN 1.5 +5 10 10 15 V V A A pF 0.4 5 5 15 V V A pF 12-Bit Serial BTC ISINK = 1.6mA ISOURCE = 500A At All Digital Output Pins 0 4.2 VECANA01 SBAS155 SPECIFICATIONS (Cont.) At VANA+ = +5V, VANA- = -5V, VDIG+ = +5V, VDIG- = -5V, and TA = -40C to +85C, using internal reference, fCLOCK = 1.25MHz. ANALOG-TO-DIGITAL CONVERTER CHANNELS VECANA01N PARAMETER POWER SUPPLIES VANA+ VANA- VDIG+ VDIG- IANA+ IANA- IDIG+ IDIG- Power Dissipation CONDITIONS MIN TYP MAX UNITS +4.75 -4.75 +4.75 -4.75 +5.0 -5.0 +5.0 -5.0 15 -8 12 -10 225 +5.25 -5.25 +5.25 -5.25 V V V V mA mA mA mA mW +85 +125 +150 C C C MAX UNITS +2.5 1 1 1 10 2 V s LSB LSB A mV % MAX UNITS 2.5 V Specified Performance TEMPERATURE RANGE Specified Performance Derated Performance Storage -40 -55 -65 DIGITAL-TO-ANALOG CONVERTER VECANA01N PARAMETER RESOLUTION Output Range Output Settling Time Linearity Error Differential Linearity Output Current Offset Error Full Scale Error (including REF) CONDITIONS MIN TYP 8-Bits 0 0.5LSB 0.2 200 1 SIGN AND WINDOW COMPARATORS VECANA01 PARAMETER CONDITIONS MIN TYP Differential Input Voltage Range of the Window Comparators Offset Error of the Window Comparators Hysteresis of the Window Comparators Offset Error of the Sign Current Comparators Hysteresis of the Sign Current Comparators Offset Error of the Sign Sensor Signal Comparators 20 60 5 10 5 80 100 20 30 30 mV mV mV mV mV Hysteresis of the Sign Sensor Signal Comparators 75 90 mV 2.9 25 250 3.2 150 1500 V ns ns Absolute Input Range of the Comparators Delay Time of the Sign Comparators Delay Time of the Window Comparators The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. VECANA01 SBAS155 3 ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS Ground Voltage Difference: AGND and DGND ................................ 0.3V Power Supply Voltages: VANA+ ................................................................................................. +7V VANA- ................................................................................................. -7V VDIG+ ................................................................................................. +7V VDIG- ................................................................................................. -7V Digital Inputs .............................................................. -0.3V to VDIG +0.3V Maximum Junction Temperature ................................................... +165C Internal Power Dissipation ............................................................. 825mW Lead Temperature (soldering, 10s) .............................................. +300C This integrated circuit can be damaged by ESD. BurrBrown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. CONVERSION AND DATA TIMING SYMBOL DESCRIPTION tCONV A/D Conversion Time 10.4 MIN TYP MAX UNITS 6.2 s CLK A/D Conversion Clock 1.25 2.1 MHz t1 Setup Time for Conversion Before Rising Edge of Clock 50 ns t2 Hold Time for Conversion After Rising Edge of Clock 50 ns t3 Setup Time for Serial Out t4 Setup Time for Serial Input 30 ns t5 Hold Time for Serial Input 30 ns 125 ns PACKAGE/ORDERING INFORMATION PRODUCT PACKAGE PACKAGE DRAWING NUMBER VECANA01 PLCC-68 312 SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA -40C to +85C VECANA01 VECANA01 Rails AN3P AN3N 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 DAIN AN2N DAOUT AN2P REFOUT AN1N REFIN AN1P REFGND NC UN5V IWN 9 UP5V IWP AGND PIN CONFIGURATION NC 10 60 NC IVN 11 59 IUN IVP 12 58 IUP NC 13 57 NC B1N 14 56 A1N B1P 15 55 A1P NC 16 54 NC B2N 17 53 A2N B2P 18 52 A2P VECANA01 NC 19 51 NC NC 20 50 NC B_2 21 49 A_2 B_1 22 48 A_1 V_ILIM 23 47 U_ILIM V_COMP 24 46 U_COMP W_ILIM 25 45 NC W_COMP 26 44 NC 4 NC NC DATACLK ADBUSY ADIN NPSH ADCONV ADCLK ADOUT1 ADOUT3 ADOUT2 NC UDN5V DGND UDP5V TP2 TP1 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 VECANA01 SBAS155 PIN DEFINITIONS PIN NO NAME TYPE(1) 36 ADCLK DI Clock for the A/D converters. The nominal clock frequency is 1.25MHz. 37 ADCONV DI Start signal for the A/D converter, active low. The first rising clock edge of ADCLK, when ADCONV is 0, starts the conversion. 38 NPSH DI Sample/hold control for sampling the position sensor signals. If the value is 1, the signals are sampled, if it is 0 they are stored. 39 ADIN DI Serial input signal for programming the D/A converter for setting the limit value of the current signals for the input voltage range of the A/D converters and for the input multiplexer of the A/D converters. 40 ADBUSY DO Conversion is executing, active low 41 DATACLK -- Test pin, do not connect to in normal operation. Signal B analog input of position sensor 1, Negative Side 42 NC -- No Connection Signal B analog input of position sensor 1, Positive Side 43 NC -- No Connection 44 NC -- No Connection NC -- No Connection PIN NO NAME TYPE(1) 1 AN3N AI Auxiliary analog input channel 3, Negative Side 2 AN3P AI Auxiliary analog input channel 3, Positive Side 3 AN2N AI Auxiliary analog input channel 2, Negative Side 4 AN2P AI Auxiliary analog input channel 2, Positive Side 5 AN1N AI Auxiliary analog input channel 1, Negative Side 6 AN1P AI Auxiliary analog input channel 1, Positive Side 7 NC -- No Connection 8 IWN AI Analog input of phase W current, Negative Side 9 IWP AI Analog input of phase W current, Positive Side 10 NC -- No Connection 11 IVN AI Analog input of phase V current, Negative Side 12 IVP AI Analog input of phase V current, Positive Side 13 NC -- No Connection 14 B1N AI 15 B1P AI DESCRIPTION DESCRIPTION 16 NC -- No Connection 45 17 B2N AI Signal B analog input of position sensor 2, Negative Side 46 U_COMP DO 18 B2P AI Signal B analog input of position sensor 2, Positive Side Sign of phase U current signal (IUP, IUN). If the value is positive (IUP > IUN) U_COMP is 1, if the value is negative (IUP < IUN) U_COMP is 0. 47 U_ILIM DO 19 NC -- No Connection Over-current output of phase U, active low. If IUP-IUN is greater then the positive limiting value or less than the negative limiting value, U_ILIM becomes 0. 20 NC -- No Connection 21 B_2 DO Sign of signal B position sensor 2 (B2P, B2N). If the value is positive (B2P > B2N) B_2 is 1, if the value is negative (B2P < B2N) B_2 is 0. 48 A_1 DO Sign of signal A position sensor 1 (A1P, A1N). If the value is positive (A1P > A1N) A_1 is 1, if the value is negative (A1P < A1N) A_1 is 0. 22 B_1 DO Sign of signal B position sensor 1 (B1P, B1N). If the value is positive (B1P > B1N) B_1 is 1, if the value is negative (B1P < B1N) B_1 is 0. 49 A_2 DO Sign of signal A position sensor 2 (A2P, A2N). If the value is positive (A2P > A2N) A_2 is 1, if the value is negative (A2P < A2N) A_2 is 0. 23 V_ILIM DO Over-current output of phase V, active low. If IVP-IVN is greater then the positive limiting value or less than the negative limiting value, U_ILIM becomes 0. 50 NC -- No Connection 51 NC -- No Connection 52 A2P AI Signal A analog input of position sensor 2, Negative Side 53 A2N AI Signal A analog input of position sensor 2, Positive Side 54 NC -- No Connection 55 A1P AI Signal A analog input of position sensor 1, Positive Side 56 A1N AI Signal A analog input of position sensor 1, Negative Side 57 NC -- No Connection 58 IUP AI Analog input of phase U current, Positive Side 59 IUN AI Analog input of phase U current, Negative Side 60 NC -- No Connection 61 DAIN AI Input for setting the over-current value. Normally connected to DAOUT 62 DAOUT AO Output of the D/A converter for programming the over-current limit. Output is programmable from 0V to +2.5V. REFOUT AO Output pin of the integrated reference source, nominal voltage 2.5V. 24 V_COMP DO Sign of phase V current signal (IVP, IVN). If the value is positive (IVP > IVN) V_COMP is 1, if the value is negative (IVP < IVN) V_COMP is 0. 25 W_ILIM DO Over-current output of phase W, active low. If IWP-IWN is greater then the positive limiting value or less than the negative limiting value, U_ILIM becomes 0. 26 W_COMP DO Sign of phase W current signal (IWP, IWN). If the value is positive (IWP > IWN) W_COMP is 1, if the value is negative (IWP < IWN) W_COMP is 0. 27 TP1 -- Test pin, do not connect to in normal operation. 28 TP2 -- Test pin, do not connect to in normal operation. 29 UDP5V P Digital Supply Voltage, +5V 30 DGND P Digital Supply Voltage, Ground 31 UDN5V P Digital Supply Voltage, -5V 32 NC -- No Connection 33 ADOUT2 DO Serial output signal of A/D converter 2. Rising clock edges of ADCLK outputs the bits of the A/D converter with MSB first. 63 64 REFIN AI Input pin for an external reference voltage. 34 ADOUT3 DO Serial output signal of A/D converter 3. Rising clock edges of ADCLK outputs the bits of the A/D converter with MSB first. 65 REFGND P Ground pin of the reference source. 35 ADOUT1 DO Serial output signal of A/D converter 1. Rising clock edges of ADCLK outputs the bits of the A/D converter with MSB first. 66 UN5V P Analog Supply Voltage, -5V 67 AGND P Analog Supply Voltage, Ground 68 UP5V P Analog Supply Voltage, +5V NOTE: (1) AI is Analog Input, AO is Analog Output, DI is Digital Input, DO is Digital Output, P is Power Supply Connection. VECANA01 SBAS155 5 TYPICAL PERFORMANCE CURVES At VANA+ = +5V, VANA- = -5V, VDIG+ = +5V, VDIG- = -5V and TA = 25C, using internal reference, fCLOCK = 1.25MHz. FULL SCALE vs TEMPERATURE OFFSET vs TEMPERATURE 0.9 1.4 0.8 1.2 0.7 Full Scale (%) Offset (LSB) 1.0 0.8 0.6 0.6 0.5 0.4 0.3 0.4 0.2 0.2 0.1 0 0 -55 -40 -25 0 25 70 85 -55 125 -40 -25 0.40 -0.100 0.35 -0.200 -0.300 -0.400 -0.500 -0.600 70 85 125 0.30 0.25 0.20 0.15 0.10 0.05 0 -0.700 -55 -40 -25 0 25 70 85 -55 125 -40 -25 Temperature (C) 0 25 70 85 125 Temperature (C) INTEGRAL LINEARITY (MIN) vs TEMPERATURE INTEGRAL LINEARITY (MAX) vs TEMPERATURE 0.000 0.45 -0.050 0.40 -0.100 0.35 Integral Linearity (LSB) Integral Linearity (LSB) 25 DIFFERENTIAL LINEARITY (MAX) vs TEMPERATURE 0.000 Differential Linearity (LSB) Differential Linearity (LSB) DIFFERENTIAL LINEARITY (MIN) vs TEMPERATURE -0.150 -0.200 -0.250 -0.300 -0.350 -0.400 0.30 0.25 0.20 0.15 0.10 0.05 -0.450 0 -55 -40 -25 0 25 Temperature (C) 6 0 Temperature (C) Temperature (C) 70 85 125 -55 -40 -25 0 25 70 85 125 Temperature (C) VECANA01 SBAS155 TYPICAL PERFORMANCE CURVES (Cont.) At VANA+ = +5V, VANA- = -5V, VDIG+ = +5V, VDIG- = -5V and TA = 25C, using internal reference, fCLOCK = 1.25MHz. DAC OFFSET vs TEMPERATURE DAC FULL SCALE vs TEMPERATURE 3.5 0 3.0 -0.05 DAC Full Scale (%) DAC Offset (mV) -0.10 2.5 2.0 1.5 1.0 -0.15 -0.20 -0.25 -0.30 -0.35 0.5 -0.40 0 -0.45 -55 -40 -25 0 25 Temperature (C) VECANA01 SBAS155 70 85 125 -55 -40 -25 0 25 70 85 125 Temperature (C) 7 FUNCTIONAL DESCRIPTION sample-and-hold amplifier. It communicates over three synchronous SPI/SSI serial output and one input ports. The VECANA01 operates on external clock that also determines the output data rate (see Figure 2). The VECAN01 is a triple 12-bit SAR A/D converter that operates from dual 5V power supplies. The part contains three 12-bit successive approximation ADCs, multiplexer for 10 fully differential inputs, 5 differential input synchronized sample-and-hold amplifiers, plus two asynchronous IUP/N A1P/N A2P/N 2 2 2 2 SH1 MUX1 2 SH2 2 2 2 2 2 PGA1 ADC1 ADOUT1 MUX6 SH6 2 Ref Conv MUX2 NPSH IVP/N B1P/N B2P/N 2 2 2 2 SH3 MUX3 2 SH4 2 2 2 2 2 PGA2 ADC2 ADOUT2 MUX7 SH7 2 Ref Conv MUX4 AN1 Through AN3 NPSH IWP/N AN1P/N AN2P/N AN3P/N 2 2 2 2 2 SH5 REFIN ADC3 ADOUT3 IW Only MUX5 Input Gain Select Select Ref REFOUT 2 PGA3 2 2.5V Ref Ref Conv Decoder Conv Control Logic 3 Sample 2 Input Setup Register DAC Input 8 ADIN DAC 8-Bit DAOUT NPSH ADCLK ADCONV ADBUSY DATACLK 2 U_COMP 2 A_1 2 A_2 2 V_COMP 2 B_1 2 B_2 2 W_COMP U_ILIM V_ILIM W_ILIM DAIN FIGURE 1. Functional Diagram. 8 VECANA01 SBAS155 MULTIPLEXERS The VECANA01 has several input multiplexers that are used to select the desired analog inputs and connect the proper sample-and-hold outputs to the PGAs and A/D converters. A decoder receives its inputs from the Input Setup Register and drives the MUXs (see Table VII and Table VIII for information on selecting the input channel). The input multiplexers can take full differential or single-ended signals (see Figure 4 and Table III). The analog signals stay differential through the sample holds and the PGAs all the way to the inputs of the A/D converter. This provides the best possible noise rejection. able to sample the quadrature inputs of a given position sensor at the same time (even though they are converted on successive conversion cycles) (see Table VII), so that their values are captured at the same shaft position. The VECANA01 also has the capability for limited asynchronous sampling. The sampling of SH 6 and SH 7 is controlled asynchronously by the control signal NPSH (see Table VII). This allows two inputs, each on Channel 1 and Channel 2 (see Table VIII) to be sampled asynchronously from the timing of the other sample holds. This can be useful in motor control applications where the two inputs for each channel need to be sampled asynchronously to a reference point. SAMPLE-AND-HOLD The VECANA01 contains seven sample-and-hold amplifiers. Five of them (SH1 through SH5) sample simultaneously and have their sample-and-hold timing internally synchronized (the timing is shown in Figure 2). Three of the sample-andholds (SH1, SH3, and SH5) are connected to the input multiplexers so that they can provide simultaneous sampling for all of their channel inputs. In addition, SH 2 and SH 4 simultaneously sample the third input of their channel (A2 and B2, respectively). This is useful in motor control applications where A1 and B1 are the quadrature inputs for one position sensor, and A2 and B2 are the quadrature inputs for a second position sensor (see Figure 9). In that application, it is desir- ADCS AND PGAS The VECANA01 contains three signal channels each with a 12-bit A/D converter output. The A/D converters operate synchronously and their serial outputs occur simultaneously (Table IX gives the analog input/digital output relationships). Programmable gain amplifiers precede the A/D converters (Table IX gives gain select information). For channels one and two, the PGAs are effective for all three analog inputs. For the third channel, only the IW input is gain changed by the PGA. Inputs AN1, AN2, and AN3 are connected to the A/D converter three at a fixed gain of 1.0V/V regardless of the gain select value. CLOCK AND CONTROL SIGNALS(1) Clock Pulse Reference No. ADCLK (Input)(2) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 DATACLK (Output) t1 t2 ADCONV (Input) SAMPLE (Internal) tCONV ADBUSY (Output) t3 A-to-D CONVERTER OUTPUTS tSAMPLE ADOUT1 Bit 0 MSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 LSB Bit 0 ADOUT2 Bit 0 MSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 LSB Bit 0 ADOUT3 Bit 0 MSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 LSB Bit 0 CONTROL WORD INPUT t4 ADIN How Used t5 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 7 6 5 4 3 2 1 0 1 DAC Input 0-7 Bit 9 Bit 10 Bit 11 Bit 12 0 Gain Select0-1 2 1 Bit 0 0 Input Select0-2 NOTE: (1) See the specification table for timing specifications. (2) 50% duty cycle. FIGURE 2. Timing Diagram. VECANA01 SBAS155 9 VOLTAGE REFERENCE The VECANA01 contains an internal 2.5V voltage reference. It is available externally through an output buffer amplifier. If it is desired to use an external reference, one may be connected at the REFIN pin. The output resistance of this pin for the external reference voltage is typically 7k. This then overrides the internal 2.5V reference and is connected to the A/D converter. It is also available as a buffered output at the REFOUT pin. The reference voltage shall be buffered by an external capacitor (approx. 2.2F) on the REFIN pin and also on the REFOUT pin (see Figure 3), as close as possible to the pin. 7k Internal Connection REFOUT + 2.5V Reference REFIN + 2.2F REFGND 2.2F input. This allows the conversion to be synchronous with system timing so that transient noise effects can be minimized. The ADCLK signal may run continuously or may be supplied only during convert sequences. The ADBUSY and DATACLK signals are internally generated and are supplied to make interfaces with microprocessors easier (see Figures 2 and 9). POWER-UP INITIALIZATION When power is applied to the VECANA01, two conversion cycles are required for initialization before valid digital data is transmitted on the third cycle. The first conversion, after power is applied, is performed with indeterminate configuration values in the double buffer output of the Input Setup Register. The second conversion cycle loads the desired values into the register. The third conversion uses those values to perform proper conversions and output valid digital data from each of the A/D converters. CLOCK POSITIONS(1) DESCRIPTION FUNCTIONS 2-9 DAC Input0-7 Sets DAC Output Voltage 10-11 Gain Select0-1 Sets PGA Gains 12-14 Input Select0-2 Conditions Determines Multiplexers NOTE: (1) See Figure 2, "Clock Pulse Reference No." FIGURE 3. Reference Voltage Connection. TABLE II. Description of Configurable Parameters. DIGITAL-TO-ANALOG CONVERTER An 8-bit DAC provides 256 output voltage levels from 0V to 2.499V (see Table I for input/output relationships). The DAC is controlled by the DAC Input portion of the input setup word. The DAC Input portion of the word is strobed into the DAC at the end of the conversion cycle (14th CLK pulse in Figure 2). DIGITAL INPUT DAC INPUT0-7 ANALOG OUTPUT HEX CODE BINARY CODE 00H 01H 0000 0000 0000 0001 0V +0.0098V * * * * * * * * * FFH 1111 1111 +2.499 TABLE I. DAC Input/Output Relationships. DAC OUTPUT VOLTAGE The value of the DAC output voltage is determined by the DAC Input portion of the ADIN word (bits 0 through 7, see Figure 2). The 8-bit DAC has 256 possible output steps from 0V to +2.499V. The value of 1LSB is 0.0098V. OTHER DIGITAL INPUTS AND OUTPUTS Sampling and conversion is controlled by the ADCONV and ADCLK input (see Figure 2). The VECANA01 is designed to operate from an external clock supplied at the ADCLK 10 CONFIGURABLE PARAMETERS Configurable parameters are: * PGA Gain * Input Multiplexer and Sample-and-Hold Selection * DAC Output Voltage Configuration information for these parameters is contained in the ADIN word (see Figure 2). As one conversion is taking place, the configuration for the next conversion is being loaded into the buffered Input Setup Register via the ADIN word. Tables I, VII, VIII and X shows information regarding these parameters. ANALOG-TO-DIGITAL CONVERTERS ARCHITECTURE The A/D converters are 12-bit, successive approximation types implemented with a switched capacitor circuitry. CLOCK RATE The clock for the A/D converter conversion is supplied externally at the ADCLK pin. Typical clock frequency for specified accuracy is 1.25MHz. This results in a complete conversion cycle (S/H acquisition and A/D conversion) of 10.4s. VECANA01 SBAS155 INPUT/OUTPUT The VECANA01 is designed for bipolar input voltages and uses a binary two's complement digital output code. A programmable gain function is associated with each A/D converter. This changes the full-scale analog input range and the analog resolution of the converter. Details are shown in Table IX. DIFFERENTIAL AND COMMON-MODE INPUT VOLTAGES The VECANA01 is designed with full differential signal paths all the way from the multiplexer inputs through to the input of the A/D converters. This was done to provide superior high frequency noise rejection. As is common with most differential input semiconductor devices, there are compound restrictions on the combination of differential and common-mode input voltages. This matter is made slightly more complicated by the fact that most of the analog inputs are capable of being affected by the programmable gain function. The possible differential and single-ended configurations are shown in Figures 4a and 4b. The maximum differential and common-mode restrictions are shown in Table III. GAIN SELECT CODE 0 1 2 3 Gain 5.0V/V 2.5V/V 1.25V/V 1.0V/V Full Scale Range (VD with VCM = 0) 0.5V 1.0V 2.0V 2.5V Largest Positive Common Mode Voltage, VCM+ +2.7V +2.4V +1.9V +1.6V Largest Negative Common Mode Voltage, VCM- -2.7V -2.4V -1.9V -1.6V TABLE III. Differential and Common Mode Voltage Restrictions. (A) IUP IUP + VD 2 - VD 2 - + - IUN (B) VD 2 VCM IU IUP + VD VD SIGN OF THE INPUT SIGNALS The VECANA01 contains seven comparators, which acquire the signals of the first seven input analog signals. The digital outputs of the sign comparators are the signals X_COMP. If the positive input value is greater than the negative input value, the X-COMP output becomes High (logic "1") or if the reverse, the X-COMP output is Low (logic "0"), (see Table IV). IUP - IUN U_COMP A1P - A1N A_1 A2P - A2P A_2 IVP - IVN V_COMP B1P - B1N B_1 B2P - B2N B_2 IWP - IWN W_COMP >0 1 <0 0 VCM IUN VD 2 INPUT MULTIPLEXER AND SAMPLE HOLD SELECTION The Input Select portion of the ADIN word (bits 10, 11 and 12) (see Figure 2) are decoded and determine the open/ closed condition of the multiplexer switches. This in turn determines which input signals are connected to the sample and holds and which sample and holds are connected to the PGAs/ADCs. TABLE IV. Input - Output Relation. VCM + INPUT SETUP As the A/D converters are converting and transmitting their serial digital data for one conversion cycle, a setup word is received to be used for the next conversion cycle. The 13-bit word is supplied at the ADIN pin (see Figure 1), and is stored in the buffered Input Setup Register. The Input Select and Gain Select portions of the word are decoded and determine the state of the multiplexers and PGAs (see CONFIGURABLE PARAMETERS section). VCM - IUN + VCM - The typical hysteresis value of comparators U_COMP, V_COMP and W_COMP is 10mV. The typical hysteresis value of comparators A_1, A_2, B_1, and B_2 is 50mV. AC motor control applications will typically use 10mV hysteresis for phase current measurement and 50mV hysteresis for positioning sensor measurement. OVER RANGE RECOGNITION The VECANA01 also includes three window comparators for the three input signals IU, IV and IW. Each window comparator is composed of two comparators that are monitoring the input value on the positive range limit (UPLIM) and negative range limit (UNLIM). The output values of the window comparators are output via the pins U_ILIM, V_ILIM and W_ILIM. The two range limiting values are symmetrical to the zero point (UNLIM = -UPLIM) and are determined by pin FIGURE 4. (a) Differential Signal Source. (b) Single-ended Input. VECANA01 SBAS155 11 DAIN. See Figure 5 for graphical view of the over limit set function (typically used for setting the current protection value), The DAIN value will determine the fixed range. Normally this pin is connected to DAOUT (the DAC output). In order to be able to program the range value through the control value DAC Input word, the DAC Input is an 8-bit wide unsigned value (controls the digital-to-analog converter output voltage (DAOUT)). This D/A converter has an output voltage range of 0V to 2.5V (see Table I). DAC INPUT UPLIM UNLIM 0H 0V 0V 1H +0.0098V -0.0098V 2H +0.0195V -0.0195V 0FEH +2.4805V -2.4805V 0FFH +2.4902V -2.4902V TABLE V. Over-Current Limit as a Function DAC Input. If the input voltage exceeds the positive range limit (IXP - IXN > UPLIM) or it remains under the negative range (IXP - IXN < UNLIM), then the corresponding window comparator output is Low (logic "0") (U_ILIM, V_ILIM, or W_ILIM). If the input value is within the limits, the comparator output is High (logic "1"). The input signal and output X_ILIM signals are shown in Table VI. IUP - IUN U_ILIM IVP - IVN V_ILIM IWP - IWN W_ILIM (IXP - IXN) > UPLIM 0 UPLIM > (IXP - IXN) > UNLIM 1 UNLIM > (IXP - IXN) 0 TABLE VI. The Limiting Value as Function of DAC Input. The input voltage range of the comparators is the same as the A/D converter when the Gain Select is 3. The typical value of the hysteresis of the comparators is 50mV. Figure 5 shows the Logic State of the U_COMP and U_ILIM outputs for the input signal IVP - IUN. The output resistance of the D/A converter is approximately 10k. The output voltage, DAOUT should be buffered by a capacitor of approximately 100nF (see Figure 6) The resulting time constant is approximately 1ms and typical does not disturb most applications. INPUT SIGNALS FOR PGAS/ADCS Table VII shows the relationships between the value of Input Select0-2 and the signals that are converted. Input Select = 7H--Synchronously sample and convert input signals IU, IV, and IW. = Hysteresis IUP - IUN UPLIM UNLIM U_COMP U_ILIM FIGURE 5. Acquisition of the Current Sign and of the OverCurrent. INPUT SELECT0-2 HEX CODE 0H 1H 2H 3H 4H 5H 6H 7H ANALOG SIGNAL CONNECTED TO PGAX/ADCX BINARY CODE PGA1 /ADC1 PGA2 /ADC2 PGA3 /ADC2 000 001 010 011 100 101 110 111 Undefined A_X via SH6(1) A_2 via SH1 A_2 via SH2 A1 A1 A1 IU Undefined B_X via SH7(1) B_2 via SH3 B_2 via SH4 B1 B1 B1 IV AN3 AN3 AN2 AN2 AN1 AN1 AN1 IW NOTE: (1) See Table VIII for Operation. TABLE VII. Input Controls for Synchronous Sample Holds. Input Select = 4H, 5H, 6H--Synchronously sample and convert input signals A1, B1, and AN1. These codes also cause SH2 and SH4 to sample their inputs. Values 4H, 5H, 6H have different effects on the inputs to SH6 and SH7 (see Table VIII). INPUT SELECT0-2 HEX CODE 0H 1H 2H 3H 4H 5H 6H 7H BINARY CODE 000 001 010 011 100 101 110 111 ANALOG SIGNAL CONNECTED TO SH6 SH7 No Effect No Effect No Effect No Effect Open A1 A2 No Effect No Effect No Effect No Effect No Effect Open B1 B2 No Effect TABLE VIII. Input Controls for Asynchronous Sample Holds. Input Select = 3H--Convert A2 via SH2, B2 via SH4, and AN2 (A2 and B2 are from the value sampled in a preceding conversion cycle with Input Select = 4H, 5H or 6H). Input Select = 2H --Convert A2 via SH1, B2 via SH3, and AN2. 12 VECANA01 SBAS155 +5V -5V GND GND 4.7F 4.7F 2.2F 100nF 100nF 2.2F AN2N AN3P AN3N UP5V 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 DAIN AN2P DAOUT AN1N REFOUT AN1P REFIN NC REFGND IWN 9 UN5V IWP AGND 100nF NC 10 60 NC IVN 11 59 IUN IN- IVP 12 58 IUP IN+ NC 13 57 NC B1N 14 56 A1N B1P 15 55 A1P NC 16 54 NC B2N 17 53 A2N B2P 18 52 A2P VECANA01 NC 19 51 NC NC 20 50 NC B_2 21 49 A_2 B_1 22 48 A_1 V_ILIM 23 47 U_ILIM V_COMP 24 46 U_COMP W_ILIM 25 45 NC W_COMP 26 44 NC 4.7F 4.7F 100nF + 100nF NC NC DATACLK ADBUSY ADIN NPSH ADCONV ADCLK ADOUT1 ADOUT3 ADOUT2 NC UDN5V DGND TP2 UDP5V TP1 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Ground Plane +5V GND -5V FIGURE 6. Basic Circuit Configuration. VECANA01 SBAS155 13 DESCRIPTION ANALOG INPUT GAIN SELECT CODE DIGITAL OUTPUT 0 1 2 3 GAIN 5V/V 2.5V/V 1.25V/V 1.0V/V FULL SCALE RANGE 0.5V 1.0V 2.0V 2.5V HEX CODE +0.49976 +0.244mV 0V -0.244V -0.500V +0.9995V +0.488mV 0V -0.488mV -1.000V +1.999V +0.976mV 0V -0.976mV -2.000V +2.499 +1.22mV 0V -1.22mV -2.500V 7FFH 001H 000H FFFH 800H +Full Scale (FS -1LSB) One Bit above Mid-Scale Mid-Scale One Bit Below Mid-Scale -Full Scale BINARY TWO'S COMPLIMENT FORMAT BINARY CODE 0111 0000 0000 1111 1000 1111 0000 0000 1111 0000 1111 0001 0000 1111 0000 NOTE: The programmable gain function applies to all three input channels for ADC1 and ADC 2. However, the programmable gain function only applies to the first input (IW) for ADC3. The other three inputs (AN1, AN2, and AN3) are not affected by the GAIN SEL input. They operate at a fixed gain of 1V/V and thus have a fixed 2.5V full scale input range. TABLE IX. Analog Input - Digital Output Relationships. Input Select = 1H--Input AN3 is converted by ADC3. The output of the asynchronous sample holds, SH6 and SH7, are converted by PGA1/ADC1 and PGA2/ADC2, respectively. Note that the inputs to SH6 and SH7 are determined by previous Input Select values (see Table VIII). Thus, to properly convert the output of one of the asynchronous sample holds it is first necessary to choose its input with a previous conversion cycle. Also, the output of SH6 or SH7 will only be converted if NPSH goes low before the ADCONV command is received. Input Select = 0 H--AN3 is converted by ADC3. The inputs to PGA1/ADC1 and PGA2/ADC2 are undefined. PGA GAIN The PGA gain is determined by the Gain Select portion (bits 8 and 9) in the ADIN word (see Figure 2). There is one gain input that sets the same gain for all three PGAs. The gain values and allowable full-scale inputs are shown in Table X. GAIN SELECT0-1 0H 1H 2H 3H GAIN SETTING FULL SCALE INPUT 5.0V/V 2.5V/V 1.25V/V 1.0V/V 0.5V 1.0V 2.0V 2.5V TABLE X. Gain Select Information. For channels one and two the PGAs set the gain for all three analog inputs. For the third channel, only the IW input is gain changed by the PGA. Inputs AN1, AN2, and AN3 are connected to A/D converter three at a fixed gain of 1.0V/V regardless of the Gain Select value. CONVERSIONS FROM THE ASYNCHRONOUS SAMPLE HOLDS Decoding the Input Select value also determines which inputs are applied to the two asynchronously controlled sample holds (SH6 and SH7) (see Table VIII.) One of the three possible inputs is selected by the Input Select value 14 being 4, 5, or 6. The "No Effect" states indicate that these values of Input Select have no effect on the multiplexers at the input of SH6 and SH7. When one of the "No Effect" values of Input Select is presented, the multiplexers will not be changed (i.e., their condition is determined by the last 4, 5, or 6 value of Input Select that existed prior to the "No Effect" state). Note that Input Select = 1H presents the output of SH6 and SH7 to PGA1/ADCl and PGA2/ADC2, respectively (see Table VII). Therefore, in order to properly convert the asynchronous sampled signals, it is first necessary to choose an input signal (Input Select equal 5 or 6 in Table VIII) with one load/convert cycle and then convert the sample hold output (Input Select = 4 in Table VII) in a following conversion cycle. POWER SUPPLY The VECANA01 requires an analog and digital supply voltage of 5V. The substrate is connected to UP5V. The voltage difference between the analog and digital supply pin is not allowed to exceed a maximal value of 300mV. For this reason the circuit shown in Figure 7 is recommended for the power supply. The analog and digital power supplies are driven by a common source. Intermediate resistors provide for decoupling. Local current-limited voltage regulators generate the 5V from the analog supply voltages UB. This guarantees a further noise reduction. The diodes are responsible for protecting the regulation and prevent polarity inversion. The zener diode protects against over-voltage possible from over-voltages to the analog inputs. Typical values for the resistors and capacitors are: * RA 3 * RD 3 * CD 22F * CA 22F * CB 100nF * CR 2.2F VECANA01 SBAS155 VECANA01 CR REFIN CR REFOUT RA +5V IN +UB UP5V UDP5V OUT + 5.6V IN OUT 5.6V RD + CD CB CD CB + CA CB CA CB AGND DGND + -UB CA CA RD + + REFGND UDN5V UN5V -5V RA Ground Plane Voltage Regulator, Current Limited FIGURE 7. Power Supply of VECANA01. CONNECTION BETWEEN VECANA01 AND DSP The interface between the VECANA01 and dSMC101 comprises the control signals for the A/D converters (ADCLK, ADCONV, ADIN, ADOUT1-3, NPSH, ADBUSY and DATACLK) and the comparator signals (X_COMP and X_ILIM). The signal levels and the driver capacity of the two chips are compatible. In order to avoid noise injection of the digital power supply into the analog VECANA01 chip, it is recommended to damp all digital lines with an intermediate resistor of approximately 100 as near as possible to the analog chip. SICAN dSMC101 INTERFACE The internal logic of the VECANA01 is designed for easy control and data interface with DSPs. Figure 9 shows the interface for loading the input control word from the DSP data bus into the serial input of the VECANA01. U/V/W_COMP IUP/N PhaseCurrents IVP/N U/V/W_ILIM IWP/N A_1, B_1 Encoder1 A1P/N A_2, B_2 B1P/N ADCLK A2P/N Encoder2 VECANA01 100 Motor Control DSP FIGURE 8. Damping of All Digital Lines. VECANA01 SBAS155 B2P/N AN1P/N Auxillary AN2P/N Inputs AN3P/N VECANA01 ADCONV Sican dSMC101 ADOUT1-3 ADIN NPSH FIGURE 9. DSP Interface for Sican dSMC101. 15 PACKAGE OPTION ADDENDUM www.ti.com 20-Jul-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) VECANA01 NRND PLCC FN 68 18 Green (RoHS & no Sb/Br) CU SN Level-3-245C-168 HR VECANA01G3 NRND PLCC FN 68 18 Green (RoHS & no Sb/Br) CU SN Level-3-245C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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