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FAN6757-- mWSaver(R) PWM Controller Features Description Single-Ended Topologies, such as Flyback and Forward Converters mWSaver(R) Technology The FAN6757 is a next-generation Green Mode PWM controller with innovative mWSaver(R) technology, which dramatically reduces standby and no-load power consumption, enabling conformance to worldwide Standby Mode efficiency guidelines. - Achieves Low No-Load Power Consumption: <50 mW at 230 VAC (EMI Filter Loss Included) - Eliminates X (R)Capacitor Discharge Resistor Loss with AX-CAP Technology - Linearly Decreases Switching Frequency to 23 kHz - Burst Mode Operation at Light-Load Condition - 500 V High-Voltage JFET Startup Circuit to Eliminate Startup Resistor Loss Highly Integrated with Rich Features - Proprietary Frequency Hopping to Reduce EMI - High-Voltage Sampling to Detect Input Voltage - Peak-Current-Mode Control with Slope Compensation - Cycle-by-Cycle Current Limiting with Line Protections ensure safe operation of the power system in various abnormal conditions. A proprietary frequencyhopping function decreases EMI emission. Built-in synchronized slope compensation allows more stable Peak-Current-Mode control over a wide range of input voltage and load conditions. The proprietary internal line compensation ensures constant output power limit over the entire universal line voltage range. Requiring a minimum number of external components, FAN6757 provides a basic platform that is well suited for cost-effective flyback converter designs that require extremely low standby power consumption. Applications Compensation - Leading-Edge Blanking (LEB) - Built-In 7 ms Soft-Start (R) An innovative AX-CAP method minimizes losses in the EMI filter stage by eliminating X-cap discharge resistors while meeting IEC61010-1 safety requirements. Flyback power supplies that demand extremely low standby power consumption, such as: Advanced Protections - Brown-In/Brownout Recovery - Internal Overload / Open-Loop Protection (OLP) - VDD Under-Voltage Lockout (UVLO) - VDD Over-Voltage Protection (VDD OVP) - Over-Temperature Protection (OTP) - Current-Sense Short-Circuit Protection (SSCP) Adapters for Notebooks, Printers, Game Consoles Open-Frame SMPS for LCD TV, LCD Monitors, Printers Ordering Information Part Number FAN6757MRMX Protections (1) OLP OVP OTP SSCP Operating Temperature Range A/R L L A/R -40 to +105C Package Packing Method 8-Pin, Small-Outline Package (SOP) Tape & Reel Note: 1. A/R = Auto Recovery Mode protection, L = Latch Mode protection. (c) 2013 Fairchild Semiconductor Corporation FAN6757 * Rev. 1.0.1 www.fairchildsemi.com FAN6757-- mWSaver(R) PWM Controller November 2013 FAN6757-- mWSaver(R) PWM Controller Application Diagram VAC + VO - FAN6757 1 GND GATE 8 2 FB VDD 7 3 NC SENSE 6 4 HV RT 5 Figure 1. Typical Application Internal Block Diagram NC HV 3 4 VDDOVP OTP Line Sensing Latch Protection SSCP Re-Start Protection OLP Brownout Function High/Low Line Compensation VDD Internal BIAS 7 Soft Driver VLimit VPWM S OSC GATE 6 SENSE Q SSCP Comparator R UVLO 8 VRESET SSCP VSSCP-H/L tD-SSCP ... VDD-ON / VRESTART Soft-Start Comparator Pattern Generator Soft-Start Current Limit Comparator VRESET tD-VDDOVP VDD OVP VLimit Green Mode Blanking Circuit PWM Comparator VDD-OVP Max. Duty Slope Compensation VPWM VFB-OPEN IRT ZFB RT 5 tD-OTP1 OTP 3R OLP 2 tD-OLP VRTTH1 R OLP Comparator tD-OTP2 VRTTH2 FB VFB-OLP 1 GND Figure 2. Functional Block Diagram (c) 2013 Fairchild Semiconductor Corporation FAN6757 * Rev. 1.0.1 www.fairchildsemi.com 2 FAN6757-- mWSaver(R) PWM Controller Marking Information Z - Plant Code X - 1-Digit Year Code Y - 1-Digit Week Code TT - 2-Digit Die Run Code T - Package Type (M=SOP) M - Manufacture Flow Code ZXYTT 6757 TM Figure 3. Top Mark Pin Configuration SOP-8 GND 1 8 GATE FB 2 7 VDD NC 3 6 SENSE HV 4 5 RT Figure 4. Pin Configuration (Top View) Pin Definitions Pin # Name 1 GND Description Ground. This pin is used for the ground potential of all the pins. A 0.1 F decoupling capacitor placed between VDD and GND is recommended. 2 FB Feedback. The output voltage feedback information from the external compensation circuit is fed into this pin. The PWM duty cycle is determined from this pin and the current-sense signal from Pin 6. The FAN6757 performs open-loop protection: if the FB voltage is higher than a threshold voltage (around 4.6 V) for more than 57.5 ms, the controller latches off the PWM. 3 NC No connection HV High-Voltage Startup. This pin is connected to the line input or bulk capacitor, via 200 k resistors, to achieve brownout and high/low line compensation. If the voltage of the HV pin is lower than the brownout voltage (AC line peak voltage less than 100 V) and lasts for 65 ms, PWM output turns off. High/low line compensation dominates the OCP level and cycle-by-cycle current limit, to solve the unequal OCP level and power-limit problems under universal input. 5 RT Over-Temperature Protection. An external NTC thermistor is connected from this pin to the GND pin. The impedance of the NTC thermistor decreases at high temperatures. Once the voltage of the RT pin drops below the threshold voltage, the controller latches off the PWM. If the RT pin is not connected to an NTC resistor for over-temperature protection, it is recommended to place one 100 k resistor to ground to prevent from noise interference. This pin is limited by an internal clamping circuit. 6 SENSE 7 VDD Power Supply. The internal protection circuit disables PWM output as long as V DD exceeds the OVP trigger point. 8 GATE Gate Drive Output. The totem-pole output driver for the power MOSFET. It is internally clamped below 14.5 V. 4 Current Sense. The sensed voltage is used for peak-current-mode control and cycle-by-cycle current limiting. (c) 2013 Fairchild Semiconductor Corporation FAN6757 * Rev. 1.0.1 www.fairchildsemi.com 3 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. (1,2) Max. Units 30 V VVDD DC Supply Voltage VFB FB Pin Input Voltage -0.3 7.0 V VSENSE SENSE Pin Input Voltage -0.3 7.0 V VRT RT Pin Input Voltage -0.3 7.0 V VHV HV Pin Input Voltage 500 V PD Power Dissipation (TA50C) 400 mW JA Thermal Resistance (Junction-to-Air) 150 C/W TJ TSTG TL ESD Operating Junction Temperature -40 +125 C Storage Temperature Range -55 +150 C +260 C Lead Temperature (Wave Soldering or IR, 10 Seconds) All Pins except HV Pin (3) 6.5 Charged Device Model, JEDEC:JESD22-C101 All Pins except HV Pin (3) 2.0 Human Body Model, JEDEC:JESD22-A114 kV Notes: 1. All voltage values, except differential voltages, are given with respect to the network ground terminal. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 3. ESD level on the HV pin is CDM=1 kV and HBM=1 kV. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. We does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol RHV Parameter Min. Typ. Max. Unit 150 200 250 k Resistance on HV Pin (c) 2013 Fairchild Semiconductor Corporation FAN6757 * Rev. 1.0.1 www.fairchildsemi.com 4 FAN6757-- mWSaver(R) PWM Controller Absolute Maximum Ratings VDD=15 V and TJ=TA=25C unless otherwise noted. Symbol Parameter Conditions Min. Typ. Max. Unit VDD Section VDD-ON Threshold Voltage to Startup VDD Rising 16 17 18 V VUVLO Threshold Voltage to Stop Switching in Normal Mode VDD Falling 5.5 6.5 7.5 V VRESTART Threshold Voltage to enable HV Startup VDD Falling to Charge VDD in Normal Mode VDD-OFF Threshold Voltage to Stop Operating in Protection Mode VDD Falling 10 11 12 V VDD-OLP Threshold Voltage to Enable HV Startup VDD Falling to Charge VDD in Protection Mode 6 7 8 V VDD-LH Threshold Voltage to Release Latch Mode 3.5 4.0 4.5 V VDD-AC Minimum Voltage of VDD Pin for Enabling Brown-in to Avoid Startup Fail VUVLO +2.5 VUVLO +3.0 VUVLO +3.5 V IDD-ST Startup Current VDD=VDD-ON - 0.16 V 30 A IDD-OP1 Supply Current in PWM Operation VDD=15 V, VFB=3 V, Gate Open 1.8 mA IDD-OP2 Supply Current when PWM Stops VDD=15 V, VFB <1.4 V, Gate Off 800 A IDD-OLP Internal Sink Current when VDDOLP<VDD<VDD-OFF in Protection Mode VDD = VDD-OLP + 0.1 V 90 190 A ILH Internal Sink Current when VDD<VDD-OLP in Latch-Protection Mode VDD = 5 V 30 VDD-OVP Threshold Voltage for VDD Over-Voltage Protection 23.5 24.5 25.5 V tD-VDDOVP VDD Over-Voltage Protection Debounce Time 110 205 300 s 1.50 3.25 5.00 mA VDD Falling 4.7 140 V A HV Section IHV Inherent Current Limit of HV Pin VAC=90 V (VDC=120 V), VDD=0 V VAC-OFF Threshold Voltage for Brownout DC Source Series, R=200 k to HV Pin 90 100 110 V VAC-ON Threshold Voltage for Brown-In DC Source Series, R=200 k to HV Pin 100 110 120 V VAC VAC-ON - VAC-OFF DC Source Series, R=200 k to HV Pin 8 12 16 V 40 65 90 ms tD-AC-OFF Debounce Time for Brownout tS-WORK Work Period of HV-Sampling Circuit in Standby Mode VFB<VFB-ZDC 95 140 185 ms tS-REST Rest Period of HV-Sampling Circuit in Standby Mode VFB<VFB-ZDC 180 260 320 ms VHV-DIS HV Discharge Threshold RHV=200 k to HV Pin VDC x0.45 VDC x0.51 VDC x0.56 V tD-HV-DIS Debounce Time for HV Discharge 75 115 155 ms HV Discharge Time 360 510 660 ms tHV-DIS Continued on the following page... (c) 2013 Fairchild Semiconductor Corporation FAN6757 * Rev. 1.0.1 www.fairchildsemi.com 5 FAN6757-- mWSaver(R) PWM Controller Electrical Characteristics VDD=15 V and TJ=TA=25C unless otherwise noted. Symbol Parameter Conditions Min. Typ. Max. 62 65 68 Hopping Range (VFB>VFB-N) 3.55 4.25 4.95 VFB>VFB-G 5.12 6.40 7.68 20 23 26 1.25 1.50 1.75 Unit Oscillator Section fOSC Frequency in Normal Mode tHOP Hopping Period Center Frequency Center Frequency kHz ms Green-Mode Frequency Hopping Range (Increase VFB from VFB-G Until Hopping Starts) fDV Frequency Variation vs. VDD Deviation VDD=11 V to 22 V 5 % fDT Frequency Variation vs. Temperature Deviation TA=-40 to 105C 5 % 1/3.00 V/V fOSC-G kHz Feedback Input Section AV Input Voltage to Current-Sense Attenuation ZFB Pull High Impedance at Normal Mode 1/4.50 1/3.75 FB Pin Open 17 19 21 k 5.2 5.4 5.6 V VFB-OPEN Output High Voltage VFB-OLP FB Open-Loop Trigger Level 4.3 4.6 4.9 V tD-OLP Delay of FB Pin Open-Loop Protection 45.0 57.5 70.0 ms VFB-N Green-Mode Entry FB Voltage 2.6 2.8 3.0 V VFB-G Green-Mode Ending FB Voltage 2.1 2.3 2.5 V VFB-ZDCR FB Threshold Voltage for Zero-Duty Recovery at Normal Mode 1.9 2.1 2.3 V VFB-ZDC FB Threshold Voltage for Zero-Duty at Normal Mode 1.8 2.0 2.2 V 100 250 ns 200 265 330 ns Current-Sense Section tPD Delay to Output tLEB Leading-Edge Blanking Time VLIMIT-L Current Limit at Low Line (VAC-RMS=86 V) VDC=122 V, Series R=200 k to HV 0.43 0.46 0.49 V VLIMIT-H Current Limit at High Line (VAC-RMS=259 V) VDC=366 V, Series R=200 k to HV 0.36 0.39 0.42 V VSSCP-L Threshold Voltage for SENSE ShortCircuit Protection VDC=122 V, Series R=200 k to HV 30 50 70 mV VSSCP-H Threshold Voltage for SENSE ShortCircuit Protection VDC=366 V, Series R=200 k to HV 80 100 120 mV tON-SSCP On Time for VSSCP-(L/H) Checking VSENSE<VSSCP-(L/H) 4.00 4.55 5.10 s tD-SSCP Debounce Time for SENSE ShortCircuit Protection VSENSE<VSSCP-(L/H) 110 170 230 s Soft-Startup Time Startup Time 5 7 9 ms tSS Continued on the following page... (c) 2013 Fairchild Semiconductor Corporation FAN6757 * Rev. 1.0.1 www.fairchildsemi.com 6 FAN6757-- mWSaver(R) PWM Controller Electrical Characteristics VDD=15 V and TJ=TA=25C unless otherwise noted. Symbol Parameter Conditions Min. Typ. Max. Unit 75.0 82.5 90.0 % 1.5 V GATE Section DCYMAX Maximum Duty Cycle VGATE-L Gate Low Voltage VDD=15 V, IO=50 mA VGATE-H Gate High Voltage VDD=12 V, IO=50 mA 8 tr Gate Rising Time (10~90%) VDD=15 V, CL=1 nF 85 110 135 ns tf Gate Falling Time (10~90%) VDD=15 V, CL=1 nF 30 40 50 ns 11.0 14.5 18.0 V VGATE-CLAMP Gate Output Clamping Voltage VDD=22 V V RT Section IRT Output Current of RT Pin 100 A VRTTH1 Threshold Voltage, Latch Protection (Generally Used for External OTP Triggering) VRTTH2 VRT VRTTH1, After 14.5 ms Latch Off 1.000 1.035 1.070 V VRTTH2 Second Latch Protection Threshold Voltage VRTTH2 0.7 V, After 185 s Latch Off 0.65 0.70 0.75 V 9.66 10.50 11.34 k ROTP Value of VRTTH1/IRT tD-OTP1 Debounce Time, First Latch Protection Triggering VRTTH2 VRT VRTTH1 11.0 14.5 18.0 ms tD-OTP2 Debounce Time, Second Latch Protection Triggering VRT< VRTTH2 110 185 260 s Over-Temperature Protection Section (OTP) TOTP TRESTART Protection Junction Temperature +135 C Restart Junction Temperature TOTP25 C (c) 2013 Fairchild Semiconductor Corporation FAN6757 * Rev. 1.0.1 www.fairchildsemi.com 7 FAN6757-- mWSaver(R) PWM Controller Electrical Characteristics 6.0 11.4 11.2 11.0 10.8 10.6 10.4 10.2 10.0 9.8 9.6 5.0 VDD-OFF (V) VRESTART (V) 5.5 4.5 4.0 3.5 3.0 -40 -30 -15 0 25 50 75 85 100 125 -40 -30 -15 0 Temperature (C) 9.0 8 8.5 7 8.0 6 7.5 7.0 6.5 1 5.0 0 25 50 75 85 -40 100 125 -30 -15 0 25 50 75 85 100 125 Temperature (C) Temperature (C) Figure 7. VDD-OLP vs. Temperature Figure 8. VDD-LH vs. Temperature 70 100 90 80 70 60 50 40 30 20 10 0 65 ILH (A) 60 tD_OLP (ms) 100 125 3 5.5 0 85 4 2 -15 75 5 6.0 -30 50 Figure 6. VDD-OFF vs. Temperature VDD-LH (V) VDD-OLP (V) Figure 5. VRESTART vs. Temperature -40 25 Temperature (C) 55 50 45 40 35 30 -40 -30 -15 0 25 50 75 85 100 125 -40 Temperature (C) Figure 9. TD-OLP vs. Temperature (c) 2013 Fairchild Semiconductor Corporation FAN6757 * Rev. 1.0.1 -30 -15 0 25 50 75 Temperature (C) 85 100 125 Figure 10. ILH vs. Temperature www.fairchildsemi.com 8 FAN6757-- mWSaver(R) PWM Controller Typical Characteristics 115 110 VAC-OFF (V) VAC-ON (V) 120 118 116 114 112 110 108 106 104 102 100 105 100 95 90 85 80 -40 -30 -15 0 25 50 75 85 100 125 -40 -30 -15 Temperature (C) 0 25 50 75 85 100 125 Temperature (C) Figure 11. VAC-ON vs. Temperature Figure 12. VAC-OFF vs. Temperature 80 6.0 5.5 75 1/AV (V/V) fOSC (kHz) 5.0 70 65 60 55 4.0 3.5 3.0 2.5 2.0 50 -40 -30 -15 0 25 50 75 85 -40 100 125 -30 -15 0 25 50 75 85 Temperature (C) Temperature (C) Figure 13. fOSC vs. Temperature Figure 14. 1/AV vs. Temperature 21.0 20.5 20.0 19.5 19.0 18.5 18.0 17.5 17.0 16.5 16.0 VFB-OPEN (V) ZFB (k) 4.5 -40 -30 -15 0 25 50 75 85 6.0 5.9 5.8 5.7 5.6 5.5 5.4 5.3 5.2 5.1 5.0 100 125 -40 Temperature (C) -30 -15 0 25 50 75 85 100 125 Temperature (C) Figure 15. ZFB vs. Temperature (c) 2013 Fairchild Semiconductor Corporation FAN6757 * Rev. 1.0.1 100 125 Figure 16. VFB-OPEN vs. Temperature www.fairchildsemi.com 9 FAN6757-- mWSaver(R) PWM Controller Typical Characteristics 90 0.55 80 0.50 VLIMIT-L (V) 0.60 DCYMAX (%) 100 70 60 50 0.45 0.40 0.35 40 0.30 30 -40 -30 -15 0 25 50 75 85 -40 100 125 -30 -15 Figure 17. DCYMAX vs. Temperature 0.55 tLEB (ns) VLIMIT-H (V) 0.50 0.45 0.40 0.35 0.30 0.25 0.20 -30 -15 0 25 50 75 50 75 85 100 125 85 380 360 340 320 300 280 260 240 220 200 100 125 -40 Temperature (C) -30 -15 0 25 50 75 85 100 125 Temperature (C) Figure 19. VLIMIT-H vs. Temperature (c) 2013 Fairchild Semiconductor Corporation FAN6757 * Rev. 1.0.1 25 Figure 18. VLIMIT-L vs. Temperature 0.60 -40 0 Temperature (C) Temperature (C) Figure 20. tLEB vs. Temperature www.fairchildsemi.com 10 FAN6757-- mWSaver(R) PWM Controller Typical Characteristics Current Mode Control FAN6757 employs peak current-mode control, as shown in Figure 21. An opto-coupler (such as the H11A817A) and a shunt regulator (such as the KA431) are typically used to implement the feedback network. Comparing the feedback voltage with the voltage across the Rsense resistor makes it possible to control the switching duty cycle. The built-in slope compensation stabilizes the current loop and prevents sub-harmonic oscillation. 5.4 V 2 GATE 8 SENSE 6 VO VFB VFB.ZDCR VFB.ZDC IDrain VO ZFB PWM Comparator switching, reducing switching loss for lower power consumption, as shown in Figure 23. FB Switching Disabled 3R Gate driver KA431 R + Primary side + Secondary side Slope compensatin Figure 21. Current Mode Control Circuit Diagram Switching Disabled Figure 23. Burst Switching in Green Mode Operating Current In normal conditions, operating current is less than 1.8 mA (IDD-OP1). When VFB<1.4 V, operating current is further reduced below 800 A (IDD-OP2) by disabling several blocks of the FAN6757. The low operating current improves light-load efficiency and reduces the requirement of VDD hold-up capacitance. Green-Mode Operation High-Voltage Startup and Line Sensing The FAN6757 modulates the PWM frequency as a function of the FB voltage to improve the medium- and light-load efficiency, as shown in Figure 22. Since the output power is proportional to the FB voltage in currentmode control, the switching frequency decreases as load decreases. In heavy-load conditions, the switching frequency is fixed at 65 kHz. Once VFB decreases below VFB-N (2.8 V), the PWM frequency starts linearly decreasing from 65 kHz to 23 kHz to reduce switching losses. As VFB drops to VFB-G (2.3 V), where switching frequency is decreased to 23 kHz, the switching frequency is fixed to avoid acoustic noise. The HV pin is typically connected to the AC line input through two external diodes and one resistor (R HV), as shown in Figure 24. When the AC line voltage is applied, the VDD hold-up capacitor is charged by the line voltage through the diodes and resistor. After VDD reaches the turn-on threshold voltage (VDD-ON), the startup circuit charging VDD capacitor is switched off and VDD is supplied by the auxiliary winding of the transformer. Once the FAN6757 starts up, it continues operation until VDD drops below 6.5 V (VUVLO). The IC startup time with a given AC line input voltage is: fS tSTARTUP RHV CDD ln fOSC VAC IN VAC IN 2 2 2 2 (1) VDD ON RHV 4 fOSC-G HV 7 VFB-N VFB CDD VDD-ON/ VRESTART Figure 22. VFB vs. PWM Frequency CX When VFB falls below VFB-ZDC (2.0 V) as load decreases further, the FAN6757 enters Burst Mode operation, where PWM switching is disabled. Then the output voltage starts to drop, causing the feedback voltage to rise. Once VFB rises above VFB-ZDCR (2.1 V), switching resumes. Burst Mode alternately enables and disables (c) 2013 Fairchild Semiconductor Corporation FAN6757 * Rev. 1.0.1 - VFB-ZDC VFB-ZDCR VFB-G VDD + VDD Good RLS Sampling Circuit Brown-in/out Function AC Line High/ Low Line Compensation VLIMIT VOCP Figure 24. Startup Circuit www.fairchildsemi.com 11 FAN6757-- mWSaver(R) PWM Controller Functional Description increases. The current-limit level is also proportional to the RHV resistor value and the power-limit level can be tuned using the RHV resistor. OSC GATE 8 DRV Q S V BROWN -OUT (RMS) R HV V AC ON 200k 2 R HV V AC OFF 2 200k Current limit comparator HV VLIMIT + + Slope compensation SENSE Power Limit Line Compensation 6 VLIMIT (V) 0.5 Note that VDD must be larger than VDD-AC to start up, even though sensed line voltage satisfies Equation 2. 0.45 RHV=240 k AX-CAP(R) Discharge RHV=200 k 0.4 RHV=160 k 0.35 0.3 70 110 150 190 230 Line Voltage (VAC) 270 Figure 26. Current Limit vs. Line Voltage Under-Voltage Lockout (UVLO) As shown in Figure 27, as long as protection is not triggered, the turn-off threshold of VDD is fixed internally at VUVLO (6.5 V). When Protection Mode is triggered, the VDD level to terminate PWM gate switching is changed to VDD-OFF (11 V), as shown in Figure 28. When VDD drops below VDD-OFF, switching is terminated and the operating current from VDD is reduced to IDD-OLP to slow down the discharge of VDD until VDD reaches VDD-OLP. This delays re-startup after shutdown by protection to minimize the input power and voltage/current stress of switching devices during fault condition. VDD FAN6757 has pulse-by-pulse current limit, as shown in Figure 25, to limit the maximum input power with a given input voltage. If the output consumes beyond this maximum power, the output voltage drops triggering the overload protection. (c) 2013 Fairchild Semiconductor Corporation FAN6757 * Rev. 1.0.1 R Figure 25. Pulse-by-pulse Current Limit Circuit Since the internal resistor (RLS=1.62 k) of the voltage divider is much smaller than RHV, the thresholds are given as a function of RHV. As shown in Figure 25, the high/low line compensation block adjusts the current-limit level, VLIMIT, based on the line voltage. Figure 26 shows how the pulse-by-pulse current-limit level changes with the line voltage for different RHV resistors. To maintain the constant output power limit regardless of line voltage, the cycle-by-cycle current-limit level, VLIMIT, decreases as line voltage Line Sensing 4 (3) High/Low Line Compensation for Constant Power Limit SS comparator 2 FB VSS (2) The EMI filter in the front end of the Switched-Mode Power Supply (SMPS) typically includes a capacitor across the AC line connector. Most of the safety regulations, such as UL 1950 and IEC61010-1, require the capacitor be discharged to a safe level within a given time when AC plug is removed from its receptacle. Typically, discharge resistors across the capacitor are used to ensure the capacitor is discharged naturally, which introduces power loss as long as it is connected to the receptacle. (R) The innovative AX-CAP technology intelligently discharges the filter capacitor only when the power supply is unplugged from the power outlet. Since the (R) AX-CAP discharge circuit is disabled in normal operation, the power loss in the EMI filter can be virtually removed. The discharge of the capacitor is achieved through the HV pin. Once AC outlet detaching is detected, the FAN6757 discharges the capacitor across the AC line connector by the external resistor on the HV pin. 3R Q R Based on the detected line voltage, brown-in and brownout thresholds are determined as: V BROWN - IN (RMS) 5.4 V ZFB PWM Comparator VDD-ON 17 V VUVLO VRESTART 6.5 V 4.7 V GATE t Figure 27. VDD UVLO at Normal Mode www.fairchildsemi.com 12 FAN6757-- mWSaver(R) PWM Controller The HV pin detects the AC line voltage using a switched voltage divider consisting of an external resistor (RHV) and an internal resistor (RLS), as shown in Figure 24. The internal line-sensing circuit detects line voltage using a sampling circuit and a peak-detection circuit. Since the voltage divider causes power consumption when it is switched on, the switching is driven by a signal with a very narrow pulse width to minimize power loss. The sampling frequency is also adaptively changed according to the load condition to minimize power consumption in light-load condition. function. For OTP applications, an NTC thermistor, RNTC, usually in series with a resistor RA, is connected between the RT pin and ground. The internal current source, IRT, (100 A) introduces voltage on RT as: 17 V VRT I RT (RNTC R A ) 11 V VDD-OFF VDD-OLP At high ambient temperature, RNTC decreases reducing VRT. When VRT is lower than VRTTH1 (1.035 V) for longer than tD-OTP1 (14.5 ms), the protection is triggered and the FAN6757 enters latch mode protection. 7V GATE t Figure 28. VDD UVLO at Protection Mode Leading-Edge Blanking (LEB) Each time the power MOSFET is switched on, a turn-on spike occurs on the sense resistor. To avoid premature termination of the switching pulse, a leading-edge blanking time, tLEB, is introduced. During this blanking period, the current-limit comparator is disabled and cannot switch off the gate driver. Gate Output / Soft Driving The BiCMOS output stage has a fast totem-pole gate driver. The output driver is clamped by an internal 14.5 V Zener diode to protect power MOSFET gate from over voltage. A soft driving is implemented to minimize electromagnetic interference (EMI) by reducing the switching noise. VDD Over-Voltage Protection (OVP) VDD over-voltage protection prevents IC damage from over-voltage exceeding the IC voltage rating. When the VDD voltage exceeds 24.5 V, the protection is triggered. This protection is typically caused by open circuit of the secondary-side feedback network. The OTP can be also trigged by pulling down the RT pin voltage using an opto-coupler or transistor. Once VRT is less than VRTTH2 (0.7 V) for longer than tD-OTP2 (185 s), the protection is triggered and latch mode protection begins. When OTP is not used, it is recommended to place a 10 k resistor between this pin and ground to prevent noise interference. Sense-Pin Short-Circuit Protection FAN6757 provides safety protection for Limited Power Source (LPS) test. When the current-sense resistor is short circuited by a soldering defect during production, the current-sensing information is not properly obtained, which results in unstable operation of the power supply. To protect the power supply against a short circuit across the current-sense resistor, the FAN6757 shuts down when the current-sense voltage is very low, even with a relatively large duty cycle. As shown in Figure 29, the current-sense voltage is sampled tON-SSCP (4.55 s) after the gate turn-on. If the sampled voltage (VS-CS) is lower than VSSCP for 11 consecutive switching cycles (170 s), the FAN6757 shuts down immediately. VSSCP varies linearly with the line voltage. At 122 V DC input, it is typically 50 mV (VSSCP-L); while at 366 V DC, it is typically100 mV (VSSCP-H). Soft-Start An internal soft-start circuit progressively increases the pulse-by-pulse current-limit level of the MOSFET for 7 ms during startup to establish the correct working conditions for the transformers and capacitors. tD-SSCP VS-CS VSENSE GATE Over-Temperature Protection (OTP) tON-SSCP Figure 29. Timing Diagram of SSCP The RT pin provides adjustable Over-Temperature Protection (OTP) and an external latch triggering (c) 2013 Fairchild Semiconductor Corporation FAN6757 * Rev. 1.0.1 (4) www.fairchildsemi.com 13 FAN6757-- mWSaver(R) PWM Controller VDD VDD-ON Application PWM Controller Input Voltage Range Output 65 W Notebook Adapter FAN6757MRMX 85 VAC ~ 265 VAC 19 V, 3.42 A X-cap BD1 0.33F/275V 2A/600V CDO RDO 1nF/100V 23.5 LO TF1 1.5H 510H VAC + ZDSN DO P6KE150A 20A/150V DSN CIN CO2 VO 470F/ 25V FR107 120F/ 400V 1N4007 CO1 1000F/ 25V - 1N4007 Q1 FQPF7N65C RG 20 RSENSE RHV 0.176 200k FAN6757 1 GND RLPF GATE 8 2 FB 100 RD VDD 7 R1 1.2k 200k 3 NC SENSE 6 4 HV RT 5 CFB CLPF DDD RA 1nF PC817A 470pF RF CF 4.7k 2.2nF 1N4935 5.6k RNTC 100k CDD KA431 R2 47F/ 50V 30k Figure 30. Schematic of Typical Application Circuit Transformer Schematic Diagram Core: Ferrite Core RM-10 Bobbin: RM-10 RM-10 4 3-Layer Tape S N4 N1 3-Layer Tape Shielding 1-Layer Tape 3-Layer Tape N2 5 N3 N4 6 7 N3 F N2 3-Layer Tape Shielding 1-Layer Tape N1 9 Bobbin Figure 31. Transformer Specification (c) 2013 Fairchild Semiconductor Corporation FAN6757 * Rev. 1.0.1 www.fairchildsemi.com 14 FAN6757-- mWSaver(R) PWM Controller Typical Application Circuit Pin (Start Finish) Wire Turns Winding Method Remark 45 0.5x1 19 Solenoid Winding Enameled Copper Wire N1 Insulation: Polyester Tape, t = 0.025 mm, 1 Layer Shielding: Adhesive Tape of Copper Foil, t = 0.025x7 mm, 1.2 Layers, Open Loop, Connected to Pin 4 Insulation: Polyester Tape t = 0.025 mm, 3 Layers SF N2 0.9x1 8 Solenoid Winding Triple Insulated Wire 7 Solenoid Winding Enameled Copper Wire Insulation: Polyester Tape, t = 0.025mm, 3 Layers 97 N3 0.4x1 Insulation: Polyester Tape, t = 0.025 mm, 1 Layer Shielding: Adhesive Tape of Copper Foil, t = 0.025x7 mm, 1.2 Layers, Open Loop, Connected to Pin 4 Insulation: Polyester Tape t = 0.025 mm, 3 Layers 56 N4 0.5x1 19 Solenoid Winding Enameled Copper Wire Insulation: Polyester Tape t = 0.025 mm, 3 Layers Electrical Characteristics Pin Specification Remark Primary-Side Inductance 46 510 H 5% 1 kHz, 1 V Primary-Side Effective Leakage Inductance 46 20 H Maximum Short All Other Pins Typical Performance Table 1. Power Consumption Input Voltage 230 VAC Output Power Actual Output Power Input Power Specification No Load 0W 0.045 W Input Power < 0.05 W 0.25 W 0.255 W 0.360 W Input Power < 0.5 W 0.5 W 0.521 W 0.711 W Input Power < 1 W Table 2. Efficiency Output Power 16.25 W 32.5 W 48.75 W 65 W Average 115 V 60 Hz 87.84% 87.42% 86.92% 86.23% 87.10% 230 V 50 Hz 87.88% 87.95% 87.82% 87.69% 87.83% (c) 2013 Fairchild Semiconductor Corporation FAN6757 * Rev. 1.0.1 www.fairchildsemi.com 15 FAN6757-- mWSaver(R) PWM Controller Winding Specification 5.00 4.80 A 0.65 3.81 8 5 B 1.75 6.20 5.80 PIN ONE INDICATOR 4.00 3.80 1 5.60 4 1.27 (0.33) 1.27 0.25 C B A LAND PATTERN RECOMMENDATION SEE DETAIL A 0.25 0.10 0.25 0.19 C 1.75 MAX 0.10 0.51 0.33 OPTION A - BEVEL EDGE 0.50 x 45 0.25 R0.10 GAGE PLANE R0.10 OPTION B - NO BEVEL EDGE 0.36 NOTES: UNLESS OTHERWISE SPECIFIED 8 0 0.90 0.40 A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08Arev14 F) FAIRCHILD SEMICONDUCTOR. SEATING PLANE (1.04) DETAIL A SCALE: 2:1 Figure 32. 8-Pin, SOP-8 Package Package drawings are provided as a service to customers considering our components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact our representative to verify or obtain the most recent revision. Package specifications do not expand the terms of our worldwide terms and conditions, specifically the warranty therein, which covers our products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/dwg/M0/M08A.pdf. (c) 2013 Fairchild Semiconductor Corporation FAN6757 * Rev. 1.0.1 16 FAN6757-- mWSaver(R) PWM Controller Physical Dimensions FAN6757-- mWSaver(R) PWM Controller (c) 2013 Fairchild Semiconductor Corporation FAN6757 * Rev. 1.0.1 17 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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