CDCE62002RHBT - Texas Instruments

1

FEATURES

APPLICATIONS

CDCE62002

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...................................................................................................................................................................................................... SCAS882 – JUNE 2009

Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs

•Flexible Inputs With Innovative SmartMultiplexer Feature:•Frequency Synthesizer With PLL/VCO andPartially Integrated Loop Filter – Two Universal Differential Inputs AcceptFrequencies from 1 MHz up to 500 MHz•Fully Configurable Outputs Including

(LVPECL), 500 MHz (LVDS), or 250 MHzFrequency and Output Format

(LVCMOS).•Smart Input Multiplexer Automatically

– One Auxiliary Input Accepts Single EndedSwitches Between one of two Reference

Clock Source or Crystal. Auxiliary InputInputs.

Accepts Crystals in the Range of•Multiple Operational Modes Include Clock

2MHz – 42MHz or an LVCMOS Input up toGeneration via Crystal, SERDES Startup Mode,

75MHz.Jitter Cleaning, and Oscillator Based Holdover

– Clock Generator Mode Using Crystal InputMode.

– Smart Input Multiplexer can be Configured•Integrated EEPROM Determines Device

to Automatically Switch Between HighestConfiguration at Power-up.

Priority Clock Source Available Allowing•Excellent Jitter Performance

for Fail-Safe Operation.•Integrated Frequency Synthesizer Including

•Typical Power Consumption 750mW at 3.3VPLL, Multiple VCOs, and Loop Filter:

•Integrated EEPROM Stores Default Settings;– Full Programmability Facilitates Phase

Therefore, the Device can Power up in aNoise Performance Optimization Enabling

Known, Predefined State.Jitter Cleaner Mode

•Offered in QFN-32 Package– Programmable Charge Pump Gain and

•ESD Protection Exceeds 2kV HBMLoop Filter Settings

•Industrial Temperature Range – 40 ° C to 85 ° C– Unique Dual-VCO Architecture Supports aWide Tuning Range 1.750 GHz – 2.356 GHz.•Universal Output Blocks Support up to 2

•Data Converter and Data Aggregation ClockingDifferential, 4 Single-Ended, or Combinations

•Wireless Infrastructureof Differential or Single-Ended:

•Switches and Routers– 0.5 ps RMS (10 kHz to 20 MHz) Output

•Medical ElectronicsJitter Performance

•Military and Aerospace– Low Output Phase Noise: – 130 dBc/Hz

•Industrialat 1 MHz offset, Fc = 491.52 MHz

•Clock Generation and Jitter Cleaning– Output Frequency Ranges From 10.94MHz to 1.175 GHz in Synthesizer Mode– LVPECL, LVDS and LVCMOS– Independent Output Dividers SupportDivide Ratios for1,2,3,4,5,8,10,12,16,20,24 and 32.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Copyright © 2009, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

DESCRIPTION

SERDES CleanedClock

Data

CDCE62002

RecoveredClock ASICClock

ASIC

CDCE62002

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

The CDCE62002 is a high performance clock generator featuring low output jitter, a high degree of configurabilityvia a SPI interface, and programmable start up modes determined by on-chip EEPROM. Specifically tailored forclocking data converters and high-speed digital signals, the CDCE62002 achieves jitter performance under 0.5ps RMS

(1)

. It incorporates a synthesizer block with partially integrated loop filter, a clock distribution blockincluding programmable output formats, and an input block featuring an innovative smart multiplexer. The clockdistribution block includes two individually programmable outputs that can be configured to provide differentcombinations of output formats (LVPECL, LVDS, LVCMOS). Each output can also be programmed to a uniqueoutput frequency (ranging from 10.94 MHz to 1.175 GHz

(2)

). If Both outputs are configured in single-ended mode(e.g., LVCMOS), the CDCE62002 supports up to four outputs. The input block includes one universal differentialinputs which support frequencies up to 500 MHz and an auxiliary single ended input that can be connected to aCMOS level clock or configured to connect to an external AT-Cut crystal via an on board oscillator block. Thesmart input multiplexer has two modes of operation, manual and automatic. In manual mode, the user selects thesynthesizer reference via the SPI interface. In automatic mode, the input multiplexer will automatically selectbetween the highest priority input clock available.

Figure 1. CDCE62002 Application Example(1) 10 kHz to 20 MHz integration bandwidth.(2) Frequency range depends on operational mode and output format selected.

Product Folder Link(s): CDCE62002

DEVICE INFORMATION

PIN FUNCTIONS

CDCE62002

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...................................................................................................................................................................................................... SCAS882 – JUNE 2009

Table 1. CDCE62002 Pin Functions

TYPE DESCRIPTIONNAME QFN

VCC_OUT0 9,12 13,16 Power 3.3V Supply for the Output Buffers.VCC_OUT1 There is no internal connection between V

CC

and AV

CC

. It is recommended, that each V

CCuses its own supply filter.VCC_PLLDIV 22 Power 3.3V Supply Power for the PLL circuitry.VCC_PLLD 4 Power 3.3V Supply Power for the PLL circuitry.VCC_PLLA 28 A. Power 3.3V Supply Power for the PLL circuitry.VCC_VCO 24 A. Power 3.3V Supply Power for the VCO Circuitry.VCC_IN 31 Power 3.3V Supply Power for Input Buffer CircuitryVCC_AUX 1 A. Power 3.3V Supply Power for Crystal/Auxiliary Input Buffer CircuitryGND_PLLDIV 21 Ground Ground for PLL Divider circuitry. (short to GND)GND PAD Ground Ground is on Thermal PAD. See Layout recommendationSPI_MISO 7 OD 3-state LVCMOS Output that is enabled when SPI_LE is asserted low. It is the serial DataOutput to the SPI bus interface.SPI_LE 18 I LVCMOS input, control Latch Enable for Serial Programmable Interface.Note: The SPI_LE signal has to be high in order for the EEPROM to load correctly on theRising edge of PD.SPI_CLK 17 I LVCMOS input, serial Control Clock Input for the SPI bus interface, with Hysteresis.SPI_MOSI 8 I LVCMOS input, Master Out Slave In as a serial Control Data Input to CDCE62002 for theSPI bus interface.PD 6 I PD or Power Down Pin is an active low pin and can be activated externally or via thecorresponding Bit in SPI Register 2In case of PD is asserted , the Device shuts Down and after PD goes high the EEPROMLoads into RAM and the VCO core re-starts calibration, PLL will try to relock and theOutput dividers will get re-initiated. The LVPECL outputs are static low and highrespectively and the LVCMOS outputs are all low or high if inverted. The input has aninternal 150-k Ωpull-up resistor if left unconnected it will default to logic level “ 1 ” .Note: The SPI_LE signal has to be high in order for the EEPROM to load correctly intoRAM on the Rising edge of PD.AUX_IN 2 I Auxiliary Input is a Crystal input pin that connect to an internal oscillator circuitry. Thisinput can also be driven by an LVCMOS signal (as described in later future revisions ofthis document).

This input also serves as the External Feedback Input that feeds directly to the PFD.REF+ 29 I Universal Input Buffer (LVPECL, LVDS, LVCMOS) positive input for the Reference Clock.REF – 30 I Universal Input Buffer (LVPECL, LVDS,) negative input for the Reference Clock. In case ofLVCMOS signaling pull-down this pin.PLL_LOCK 32 O PLL Lock indicatorTESTSYNC 19 I Test Point for Use for TI Internal SYNC Testing.REG_CAP1 5 Analog Capacitor for the internal Regulator. Connect to a 10 µF Capacitor (Y5V)REG_CAP2 27 Analog Capacitor for the internal Regulator. Connect to a 10 µF Capacitor (Y5V)REG_CAP3 20 Analog Capacitor for the internal Regulator. Connect to a 10 µF Capacitor (Y5V)REG_CAP4 23 Analog Capacitor for the internal Regulator. Connect to a 10 µF Capacitor (Y5V)VBB 3 Analog Capacitor for the internal termination Voltage. Connect to a 1 µF Capacitor (Y5V)EXT_LFP 25 Analog External Loop Filter Input PositiveEXT_LFN 26 Analog External Loop Filter Input Negative.U0P:U0N 11,10 15,14 O The Main outputs of CDCE62002 are user definable and can be any combination of up to2 LVPECL outputs, 2 LVDS outputs or up to 4 LVCMOS outputs. The outputs areU1P:U1N

selectable via SPI interface. The power-up setting is EEPROM configurable.

Product Folder Link(s): CDCE62002

FUNCTIONAL DESCRIPTION

PD

SPI_LE

SPI _CLK

SPI_MISO

SPI_MOSI

Output

Divider 0

U0 P

U0N

Output

Divider 1

U1 P

U1N

PFD /

CP Prescaler

Feedback

Divider

Input

Divider

Reference

Divider

PRI_IN

XTAL /

AUX _IN

EEPROM

Interface

&

Control

EXT _LFP

EXT _LFN

CDCE62002

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Figure 2. CDCE62002 Block Diagram

The CDCE62002 comprises of four primary blocks: the interface and control block, the input block, the outputblock, and the synthesizer block. In order to determine which settings are appropriate for any specificcombination of input/output frequencies, a basic understanding of these blocks is required. The interface andcontrol block determines the state of the CDCE62002 at power-up based on the contents of the on-boardEEPROM. In addition to the EEPROM, the SPI port is available to configure the CDCE62002 by writing directlyto the device registers after power-up. The input block selects which of the two input ports is available for use bythe synthesizer block. The output block provides two separate clock channels that are fully programmable. Thesynthesizer block multiplies and filters the input clock selected by the input block.

NOTE:

This Section of the data sheet provides a high-level description of the features of theCDCE62002 for purpose of understanding its capabilities. For a complete descriptionof device registers and I/O, refer to the Device Configuration Section.

Product Folder Link(s): CDCE62002

Interface and Control Block

Device

Hardware

StaticRAM DeviceRegisters

Register 0

Register 1

Register 2

Interface

&

Control

PD

SPI_ LE

SPI_ CLK

SPI_ MISO

SPI_ MOSI

EEPROM DeviceRegisters

Register 0

Register 1

Register 2

Input Block

REF_IN

XTAL/

AUX_IN

LVPECL/LVDS 500 MHz

LVCMOS 250 MHz

Crystal: 2 MHz – 42 MHz

SingleEnded : 2 MHz - 75 MHz

Synthesizer

Reference

SmartMUX

Control

ReferenceDivider

/1 - /8

CDCE62002

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...................................................................................................................................................................................................... SCAS882 – JUNE 2009

The CDCE62002 is a highly flexible and configurable architecture and as such contains a number of registers sothat the user may specify device operation. The contents of nine 28-bit wide registers implemented in static RAMdetermine device configuration at all times. On power-up, the CDCE62002 copies the contents of the EEPROMinto the RAM and the device begins operation based on the default configuration stored in the EEPROM.Systems that do not have a host system to communicate with the CDCE62002 use this method for deviceconfiguration. The CDCE62002 provides the ability to lock the EEPROM; enabling the designer to implement afault tolerant design. After power-up, the host system may overwrite the contents of the RAM via the SPI (SerialPeripheral Interface) port. This enables the configuration and reconfiguration of the CDCE62002 during systemoperation. Finally, the device offers the ability to copy the contents of the RAM into EEPROM, if the EEPROM isunlocked.

Figure 3. CDCE62002 Interface and Control Block

The Input Block includes one Universal Input Buffer and an Auxiliary Input. The Input Block buffers the incomingsignals and facilitates signal routing to the Internal Synthesizer Block via the smart multiplexer (called the SmartMUX). The CDCE62002 can divide the REF_IN signal via the dividers present on the inputs of the first stage ofthe Smart MUX.

Figure 4. CDCE62002 Input Block

Product Folder Link(s): CDCE62002

Synthesizer Block

PFD/

CP

Prescaler

/2,/3,/4,/5

InputDivider

/1 - /256

SMART_MUX

SYNTH

70 kHz –

400 kHz

/1,/2,/5,/8,/10,/16,/20

/8 - /1280

1.75 GHz –

2.356 GHz

FeedbackDivider

FeedbackBypassDivider

AUX_IN

Output Block

/1,2,3,4,5

UxP

UxN

/1 - /8 /2

DigitalPhase Adjust (7-bits)

SYNTH

Sync

Pulse Enable

LVDSClockDividerModule 0 & 1

LVPECL

OutputBufferControl

CDCE62002

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Figure 5 presents a high-level overview of the Synthesizer Block on the CDCE62002. This block contains thePhase lock loop, internal loop filter and dual Voltage controlled oscillators. Only one VCO is selected at a time.The loop is closed after a Prescaler divider that feeds the output stage the feedback divider.

Figure 5. CDCE62002 Synthesizer Block

Both identical output blocks incorporate a Clock Divider Module (CDM), and a universal output array bufferdriver. If an individual clock output channel is not used, then the user should disable the CDM and Output Bufferfor the unused channel to save device power. Each channel includes 4-bit in register “ 0 ” to control the divideratio. The output divider supports divide ratios from divide by 1 (bypass the divider) 2,3,4,5,8,10,12,16,20,24 and32.

Figure 6. CDCE62002 Output Block

Product Folder Link(s): CDCE62002

COMPUTING THE OUTPUT FREQUENCY

Output

Divider 0

U0P

U0N

Output

Divider 1

U1P

U1N

PFD/

CP Prescaler

Feedback

Divider

Input

Divider

Reference

Divider

EXT_LFP

EXT_LFN

F

R

I

P

O

FOUT

Fin

OUT IN

F

F F

R I O

= ×

× ×

(1)

OUT

1.750GHz O P F 2.356GHz< × × <

(2)

IN

COMP

F

R I

=

×

(3)

CDCE62002

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...................................................................................................................................................................................................... SCAS882 – JUNE 2009

Figure 7 presents the block diagram of the CDCE62002 synthesizer highlighting the clock path for a singleoutput. It also identifies the following regions containing dividers comprising the complete clock path:•R: Is the Reference divider values.•O: The output divider value (see Output Block for more details)•I: The input divider value (see Synthesizer Block for more details)•P: The Prescaler divider value (see Synthesizer Block of more details)•F: The cumulative divider value of all dividers falling within the feedback divider (see Synthesizer Block formore details)

Figure 7. CDCE62002 Clock Path – Synthesizer

With respect to Figure 7 , any output frequency generated by the CDCE62002 relates to the input frequencyconnected to the Synthesizer Block by the following equation:

Equation 1 holds true subject to the following constraints:

And the comparison frequency F

COMP

,

40.0 kHz ≤F

COMP

≤40 MHz

Where:

Product Folder Link(s): CDCE62002

ABSOLUTE MAXIMUM RATINGS

THERMAL CHARACTERISTICS

PACKAGE

ELECTRICAL CHARACTERISTICS

CDCE62002

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over operating free-air temperature range (unless otherwise noted)

(1)

VALUE / UNIT

Supply voltage range VCC

(2)

– 0.5 V to 4.6 VInput voltage range, V

I

(3)

– 0.5 V to VCC + 0.5 VOutput voltage range, V

O

(3)

– 0.5 V to VCC + 0.5 VInput Current (V

I

< 0, V

I

> VCC) ± 20 mAOutput current for LVPECL/LVCMOS Outputs (0 < V

O

< V

CC

) ± 50 mAMaximum junction temperature, T

J

125 ° CStorage temperature range, T

stg

– 65 ° C to 150 ° C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute – maximum – rated conditions for extended periods may affect device reliability.(2) All supply voltages have to be supplied simultaneously.(3) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

Package Thermal Resistance for QFN (RGZ) Package

Airflow (lfm) θ

JP

( ° C/W) θJA ( ° C/W)

0 JEDEC Compliant Board (3X3 VIAs on PAD) 1.13 35200 JEDEC Compliant Board (3X3 VIAs on PAD) 1.13 28.3400 JEDEC Compliant Board (3X3 VIAs on PAD) 1.13 27.2

The CDCE62002 is packaged in a 32-Pin Lead Free “ Green ” Plastic Quad Flatpack Package with enhancedbottom thermal pad for heat dissipation. The Texas Instruments Package Designator is; RHB (S-PQFP-N32).Please refer to the Mechanical Data appendix at the end of this document for more information.

recommended operating conditions for the CDCE62002 Device for under the specified Industrial temperature range of – 40 ° Cto 85 ° C

PARAMETER TEST CONDITIONS MIN TYP

(1)

MAX UNIT

POWER SUPPLY

Supply voltage, V

CC_OUT

, V

CC_PLLDIV

, V

CC_PLLD

, V

CC_IN

, and V

CC_AUX

3 3.3 3.6 V

Analog Supply Voltage, VCC_PLLA, & VCC_VCO 3 3.3 3.6 V

REF at 30.72MHzP

LVPECL

850 WOutputs are LVPECL

Output 1 = 491.52 MHzREF at 30.72MHz Output 2 = 245.76 MHzP

LVDS

750 WOutputs are LVDS In case of LVCMOS Outputs (1) =245.76MHzREF at 30.72MHzP

LVCMOS

800 WOutputs are LVCMOS

P

OFF

REF at 30.72MHz Dividers and Outputs are disabled 450 W

P

PD

Device is Powered Down 40 mW

DIFFERENTIAL INPUT MODE (REF_IN)

Input amplitude, VINPP (V

_IN+

– V

IN –

) 0.1 1.3 V

Common-mode input voltage, VIC 1.0 V

CC

– 03 V

VI = VCC,I

IH

Differential input current High (No internal Termination) 20 µAVCC = 3.6 V

VI = 0 V,I

IL

Differential input current Low (No internal Termination) – 20 µAVCC = 3.6 V

Input Capacitance on REF_IN 3 pF

LVCMOS INPUT MODE (AUX_IN)

V

IL

Low-level input voltage LVCMOS 0 0.3 VCC V

(1) All typical values are at VCC = 3.3 V, temperature = 25 ° C.

Product Folder Link(s): CDCE62002

CDCE62002

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...................................................................................................................................................................................................... SCAS882 – JUNE 2009

ELECTRICAL CHARACTERISTICS (continued)recommended operating conditions for the CDCE62002 Device for under the specified Industrial temperature range of – 40 ° Cto 85 ° C

PARAMETER TEST CONDITIONS MIN TYP

(1)

MAX UNIT

V

IH

High-level input voltage LVCMOS 0.7 VCC VCC V

V

IK

LVCMOS input clamp voltage VCC = 3 V, II = – 18 mA – 1.2 V

I

IH

LVCMOS input current VI = VCC, VCC = 3.6 V 300 µA

I

IL

LVCMOS input VI = 0 V, VCC = 3.6 V – 10 10 µA

C

I

Input capacitance (LVCMOS signals) VI = 0 V or VCC 8 8 pF

CRYSTAL INPUT SPECIFICATIONS

Crystal Shunt Capacitance 10 pF

Equivalent Series Resistance (ESR) 50 Ω

LVCMOS INPUT MODE (SPI_CLK,SPI_MOSI,SPI_LE,PD, REF_IN)

V

IL

Low-level input voltage LVCMOS 0 0.3 VCC V

V

IH

High-level input voltage LVCMOS 0.7 VCC VCC V

V

IK

LVCMOS input clamp voltage VCC = 3 V, II = – 18 mA – 1.2 V

I

IH

LVCMOS input current VI = VCC, VCC = 3.6 V 20 µA

I

IL

LVCMOS input (Except REF_IN) VI = 0 V, VCC = 3.6 V – 10 – 40 µA

I

IL

LVCMOS input (REF_IN) VI = 0 V, VCC = 3.6 V – 10 10 µA

C

I

Input capacitance (LVCMOS signals) VI = 0 V or VCC 3 3 pF

SPI OUTPUT (MISO) / PLL

I

OH

High-level output current VCC = 3.3 V, V

O

= 1.65 V – 30 mA

I

OL

Low-level output current VCC = 3.3 V, V

O

= 1.65 V 33 mA

High-level output voltage for LVCMOSV

OH

VCC = 3 V, I

OH

= – 100 µA VCC – 0.5 Voutputs

Low-level output voltage for LVCMOSV

OL

VCC = 3 V, I

OH

= 100 µA 0.3 Voutputs

C

O

Output capacitance o MISO VCC = 3.3 V; V

O

= 0 V or VCC 3 pF

I

OZH

5µA3-state output current V

O

= V

CC

, V

O

= 0 VI

OZL

– 5 µA

EEPROM

EEcyc Programming cycle of EEPROM 100 1000 Cycles

EEret Data retention 10 Years

VBB ( INPUT BUFFER INTERNAL TERMINATION VOLTAGE REFERENCE)

V

BB

Input termination voltage IBB = – 0.2 mA, Depending on the setting 1.2 1.9 V

INPUT BUFFERS INTERNAL TERMINATION RESISTORS (REF_IN)

Termination resistance Single ended 5 k Ω

PHASE DETECTOR

f

CPmax

Charge pump frequency 0.04 40 MHz

Product Folder Link(s): CDCE62002

ELECTRICAL CHARACTERISTICS (Continued)

5 pF

LVCMOS

CDCE62002

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recommended operating conditions for the CDCE62002 Device for under the specified Industrial temperature range of – 40 ° Cto 85 ° C

PARAMETER TEST CONDITIONS MIN TYP

(1)

MAX UNIT

LVCMOS

f

clk

Output frequency, see Figure below Load = 5 pF to GND 250 MHzV

OH

High-level output voltage for LVCMOS outputs V

CC

= min to max I

OH

= – 100 µA VCC – 0.5 VV

OL

Low-level output voltage for LVCMOS outputs V

CC

= min to max I

OL

= 100 µA 0.3 VI

OH

High-level output current VCC = 3.3 V VO = 1.65 V – 30 mAI

OL

Low-level output current VCC = 3.3 V VO = 1.65 V 33 mAt

sko

Skew, output to output For Y0 to Y1 Both Outputs set at 122.88 MHz, 75 psReference = 30.72 MHzC

O

Output capacitance on Y0 to Y1 VCC = 3.3 V; VO = 0 V or VCC 5 pFI

OZH

Tristate LVCMOS output current VO = VCC 5 µAI

OZL

Tristate LVCMOS output current VO = 0 V -5 µAI

OPDH

Power Down output current VO = VCC 25 µAI

OPDL

Power Down output current VO = 0 V 5 µADuty cycle LVCMOS 45% 55%t

slew-rate

Output rise/fall slew rate 3.6 5.2 V/ns

(1) All typical values are at VCC = 3.3 V, temperature = 25 ° C.

Product Folder Link(s): CDCE62002

ELECTRICAL CHARACTERISTICS (Continued)

LVDSDC Termination Test

Oscilloscope100Ω

CDCE62002

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...................................................................................................................................................................................................... SCAS882 – JUNE 2009

recommended operating conditions for the CDCE62002 Device for under the specified Industrial temperature range of – 40 ° Cto 85 ° C

PARAMETER TEST CONDITIONS MIN TYP

(1)

MAX UNIT

LVDS OUTPUT

f

clk

Output frequency Configuration Load (see Figure below) 0 8006 MHz|VOD| Differential output voltage R

L

= 100 Ω270 550 mV

ΔV

OD

LVDS VOD Magnitude Change 50 mVV

OS

Offset Voltage – 40 ° C to 85 ° C 1.24 V

ΔV

OS

VOS Magnitude Change 40 mVShort Circuit Vout+ to Ground VOUT = 0 27 mAShort Circuit Vout- to Ground VOUT = 0 27 mAt

sk(o)

Skew, output to output For Y0 to Y1 Both Outputs set at 122.88 MHz 10 psReference = 30.72 MHzC

O

Output capacitance on Y0 to Y1 VCC = 3.3 V; VO = 0 V or VCC 5 pFI

OPDH

Power Down output current VO= V

CC

25 µAI

OPDL

Power Down output current VO= 0 V 5 µADuty Cycle 45% 55%t

r

/ t

f

Rise and fall time 20% to 80% of Voutpp 110 160 190 ps

LVCMOS-TO-LVDS

t

skP_C

Output skew between LVCMOS and LVDS outputs VCC/2 to Crosspoint 1.4 1.7 2.0 ns

(1) All typical values are at VCC = 3.3 V, temperature = 25 ° C.

Product Folder Link(s): CDCE62002

ELECTRICAL CHARACTERISTICS (Continued)

LVPECL DC Termination Test

50W50W

Oscilloscope

LVPECL AC Termination Test

50W

Oscilloscope

150W150W

Vcc-2

CDCE62002

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recommended operating conditions for the CDCE62002 Device for under the specified Industrial temperature range of – 40 ° Cto 85 ° C

PARAMETER TEST CONDITIONS MIN TYP

(1)

MAX UNIT

LVPECL OUTPUT

f

clk

Output frequency, Configuration Load (see Figure below) 0 1175 MHz

V

OH

LVPECL high-level output voltage Load VCC – 1.1 VCC – 0.88 V

V

OL

LVPECL low-level output voltage Load VCC – 2.02 VCC – 1.48 V

|VOD| Differential output voltage 510 870 mV

t

sko

Skew, output to output For Y0 to Y1 Both Outputs set at 122.88 MHz 15 ps

CO

Output capacitance on Y0 to Y4 VCC = 3.3 V; VO = 0 V or VCC 5 pF

I

OPDH

Power Down output current VO= V

CC

25 µA

I

OPDL

Power Down output current VO= 0 V 5 µA

Duty Cycle 45% 55%

t

r

/ t

f

Rise and fall time 20% to 80% of Voutpp ps

LVDS-TO- LVPECL

t

skP_C

Output skew between LVDS and LVPECL outputs Crosspoint to Crosspoint 130 200 280 ps

LVCMOS-TO- LVPECL

t

skP_C

Output skew between LVCMOS and LVPECL outputs VCC/2 to Crosspoint 1.6 1.8 2.2 ns

LVPECL Hi-PERFORMANCE OUTPUT

V

OH

LVPECL high-level output voltage Load VCC – 1.11 VCC – 0.91 V

V

OL

LVPECL low-level output voltage Load VCC – 2.06 VCC – 1.84 V

|VOD| Differential output voltage 670 950 mV

t

r

/ t

f

Rise and fall time 20% to 80% of Voutpp 55 75 135 ps

(1) All typical values are at VCC = 3.3 V, temperature = 25 ° C.

Product Folder Link(s): CDCE62002

f − Frequency − MHz

650

700

750

800

850

900

950

1000

1050

1100

1150

1200

0 200 400 600 800 1000 1200

High-Performance LVPECL Output V oltage Swing − mV

G002

TA = 25°C

RL = 50 Ω to VCC − 2 V

VCC = 3.6 V

VCC = 3.3 V

VCC = 3 V

f − Frequency − MHz

450

500

550

600

650

700

750

800

850

900

950

1000

0 200 400 600 800 1000 1200

LVPECL Output Voltage Swing − mV

G001

TA = 25°C

RL = 50 Ω to VCC − 2 V

VCC = 3.6 V

VCC = 3.3 V

VCC = 3 V

f − Frequency − MHz

225

250

275

300

325

350

375

400

425

450

475

500

0 100 200 300 400 500 600 700 800 900

LVDS Output Voltage Swing − mV

G003

TA = 25°C

RL = 100 Ω

VCC = 3.6 V

VCC = 3.3 V

VCC = 3 V

f − Frequency − MHz

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

50 100 150 200 250 300

LVCMOS Output Voltage Swing − V

G004

TA = 25°C

CL = 5 pF

VCC = 3.6 V

VCC = 3.3 V

VCC = 3 V

CDCE62002

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HIGH-PERFORMANCE LVPECLLVPECL OUTPUT VOLTAGE SWING OUTPUT VOLTAGE SWINGvs vsFREQUENCY FREQUENCY

Figure 8. Figure 9.

LVDS OUTPUT VOLTAGE SWING LVCMOS OUTPUT VOLTAGE SWINGvs vsFREQUENCY FREQUENCY

Figure 10. Figure 11.

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TIMING REQUIREMENTS

PHASE NOISE ANALYSIS

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over recommended ranges of supply voltage, load and operating free-air temperature range (unless otherwise noted)

PARAMETER MIN TYP MAX UNIT

REF_IN REQUIREMENTS

f

REF – Diff IN-DIV

Maximum clock frequency applied to reference divider when (Register 0 Bit 9 = 1) 500 MHzf

REF – Diff REF_DIV

Maximum clock frequency applied to reference divider when (Register 0 Bit 9 = 0) 250 MHzf

REF – Single

For Single ended Inputs ( LVCMOS) on REF_IN 250 MHzDuty Cycle Single Duty cycle of REF_IN at V

CC

/ 2 40% 60%Duty Cycle Diff Duty cycle of REF_IN at V

CC

/ 2 40% 60%

AUXILARY_IN REQUIREMENTS

f

REF – Single

For Single ended Inputs (LVCMOS) on AUX_IN 2 75 MHzf

REF – Crystal

For Single ended Inputs (AT-Cut Crystal Input) 2 42 MHz

PD REQUIREMENTS

t

r

/ t

f

Rise and fall time of the PD signal from 20% to 80% of V

CC

4 ns

Table 2. Phase Noise for 30.72MHz External ReferencePhase Noise Specifications under following configuration: VCO = 1966.08 MHz, REF = 30.72MHz,PFD Frequency = 30.72MHz, Charge Pump Current = 1.5mA Loop BW = 400kHz at 3.3V and 25 ° C.

PHASE NOISE Reference LVPECL-HP LVPECL LVDS-HP LVDS LVCMOS-HP LVCMOS UNITAT

30.72MHz 491.52MHz 491.52MHz 491.52MHz 491.52MHz 122.88MHz 122.88MHz

10Hz – 108 – 84 – 84 – 85 – 85 – 97 – 97 dBc/Hz

100Hz – 130 – 98 – 98 – 98 – 97 – 110 – 111 dBc/Hz

1kHz – 134 – 106 – 106 – 106 – 106 – 118 – 118 dBc/Hz

10kHz – 152 – 118 – 118 – 118 – 118 – 130 – 130 dBc/Hz

100kHz – 156 – 121 – 121 – 121 – 121 – 133 – 133 dBc/Hz

1MHz – 157 – 131 – 131 – 130 – 130 – 143 – 142 dBc/Hz

10MHz — – 146 – 146 – 146 – 145 – 152 – 151 dBc/Hz

20MHz — – 146 – 146 – 146 – 145 – 152 – 151 dBc/Hz

Jitter(RMS) 195

319 316 332.4 332.2 366.5 372.1 fs10k~20MHz (10k~20Mhz)

Table 3. Phase Noise for 25MHz Crystal Reference

Phase Noise Specifications under following configuration: VCO = 2000.00 MHz, AUX-REF = 25.00MHz,PFD Frequency = 25.00MHz, Charge Pump Current = 1.5mA Loop BW = 400kHz 3.3V and 25 ° C.

Phase Noise at Reference LVPECL-HP LVDS-HP LVCMOS-HP UNIT25.00MHz 500.00MHz 250.00MHz 125.00MHz

10Hz — – 72 – 72 – 79 dBc/Hz100Hz — – 97 – 97 – 103 dBc/Hz1kHz — – 111 – 111 – 118 dBc/Hz10kHz — – 120 – 120 – 126 dBc/Hz100kHz — – 124 – 124 – 130 dBc/Hz1MHz — – 136 – 136 – 142 dBc/Hz10MHz — – 147 – 147 – 151 dBc/Hz20MHz — – 148 – 148 – 151 dBc/HzJitter(RMS) — 426 426 443 fs10k~20MHz

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OUTPUT TO OUTPUT ISOLATION

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Measurement Method1. Connect output 1 to the phase noise and Spectrum analyzer.2. Measure spurious on Outputs 1.3. Enable aggressor channel 04. Measure spurious on Output 15. The difference between the spurious levels of Outputs 1before and after enabling the aggressor channel determine the output-to-outputisolation performance recorded.

Table 4. Output to Output Isolation

WORST CASE SPUR UNIT

The Output to Output Isolation was tested at 3.3V supply and 25 ° C ambient temperature (Default Configuration):

Output 1 Measured Channel In LVDS Signaling at 125MHz -70 dBOutput 0 Aggressor Channel LVPECL 156.25MHz

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SPI CONTROL INTERFACE TIMING

SPI_CLK

Bit0 Bit1 Bit29 Bit30 Bit31

SPI_LE

SPI_MOSI

t4t5

t2t3

t7

t6

t1

SPI_CLK

SPI_MOSI

SPI_MISO

SPI_LE

Bit 30 Bit 31

Bit 0 Bit 1 Bit 2

t4t5

t2t3

t7

t6t8

t9

CDCE62002

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Figure 12. Timing Diagram for SPI Write Command

Figure 13. Timing Diagram for SPI Read Command

Table 5. SPI Bus Timing Characteristics

SPI BUS TIMINGS

PARAMETER MIN TYP MAX UNIT

f

Clock

Clock Frequency for the SPI_CLK 20 MHzt

1

SPI_LE to SPI_CLK setup time 10 nst

2

SPI_MOSI to SPI_CLK setup time 10 nst

3

SPI_MOSI to SPI_CLK hold time 10 nst

4

SPI_CLK high duration 25 nst

5

SPI_CLK low duration 25 nst

6

SPI_CLK to SPI_LE Setup time 10 nst

7

SPI_LE Pulse Width 20 nst

8

SPI_MISO to SPI_CLK Data Valid (First Valid Bit after LE) 10 ns

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DEVICE CONFIGURATION

Device

Registers

Interface

&

Control

Smart

MUX Frequency

Synthesizer

Output

Channel 1

Output

Channel 0

EEPROM

Input

Block Synthesizer

Block

OutputBlocks

Interface

&

Control

Block

CDCE62002

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The Functional Description Section described four different functional blocks contained within the CDCE62002.Figure 14 depicts these blocks along with a high-level functional block diagram of the circuit elements comprisingeach block. The balance of this section focuses on a detailed discussion of each functional block from theperspective of how to configure them.

Figure 14. CDCE62002 Circuit Blocks

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INTERFACE and CONTROL BLOCK

Device

Hardware

Static RAM DeviceRegisters

Register0

Register1

Register2

EEPROM DeviceRegisters

Register0

Register1

Register2

Interface

&

Control

PD

SPI_ LE

SPI_ CLK

SPI_ MISO

SPI_ MOSI

CDCE62002

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The Interface and Control Block includes a SPI interface, four control pins, a non-volatile memory array in whichthe device stores default configuration data, and an array of device registers implemented in Static RAM. ThisRAM, also called the device registers, configures all hardware within the CDCE62002.

Figure 15. CDCE62002 Interface and Control Block

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SPI (Serial Peripheral Interface)

0123456789101112131415161718192021222324252627 0123

01234567891011121314

1516171819

2021222324252627 0123

Address

Bits

(4)

Lastin /

Lastout

FirstIn/

FirstOut

SPI_LE

SPI_CLK

SPI_MOSI

SPI_MISO

SPI_LE

SPI_CLK

SPI_MOSI

SPI_MISO

SPIMaster (Host)

SPI_LE

SPI_CLK

SPI_MOSI

SPI_MISO

SPISlave (CDCE62005)

DeviceRegisterN

0123456789101112131415161718192021222324252627

SPIRegister

DataBits (28)

CDCE62002

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The serial interface of CDCE62002 is a simple bidirectional SPI interface for writing and reading to and from thedevice registers. It implements a low speed serial communications link in a master/slave topology in which theCDCE62002 is a slave. The SPI consists of four signals:•SPI_CLK: Serial Clock (Output from Master) – the CDCE62002 clocks data in and out on the rising edge of SPI_CLK. Data transitionstherefore occur on the falling edge of the clock.•SPI_MOSI: Master Output Slave Input (Output from Master).•SPI_MISO: Master Input Slave Output (Output from Slave)•SPI_LE: Latch Enable (Output from Master). The falling edge of SPI_LE initiates a transfer. If SPI_LE is high, no data transfer can takeplace.

The CDCE62002 implements data fields that are 28-bits wide. In addition, it contains 3 registers, eachcomprising a 28 bit data field. Therefore, accessing the CDCE62002 requires that the host program append a4-bit address field to the front of the data field as follows:

Figure 16. CDCE62002 SPI Communications Format

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CDCE62002 SPI Command Structure

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The CDCE62002 supports four commands issued by the Master via the SPI:•Write to RAM•Read Command•Copy RAM to EEPROM – unlock•Copy RAM to EEPROM – lock

Table 6 provides a summary of the CDCE62002 SPI command structure. The host (master) constructs a Write toRAM command by specifying the appropriate register address in the address field and appends this value to thebeginning of the data field. Therefore, a valid command stream must include 32 bits, transmitted LSB first. Thehost must issue a Read Command to initiate a data transfer from the CDCE62002 back to the host. Thiscommand specifies the address of the register of interest in the data field.

Table 6. CDCE62002 SPI Command StructureData Field (28 Bits) Addr Field

(4 BIts)

222222221111111111Register Operation NVM 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 3 2 1 0

0 Write to RAM Yes X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0

1 Write to RAM Yes X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 1

2 Status/Control No X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 0

Instruction Read Command No 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A A A A 1 1 1 0

Instruction RAM EEPROM Unlock 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1

Instruction RAM EEPROM Lock

(1)

0000000000000000101000 0 0 0 0 1 1 1 1 1 1

(1) CAUTION: After execution of this command, the EEPROM is permanently locked. After locking the EEPROM, device configuration canonly be changed via Write to RAM after power-up; however, the EEPROM can no longer be changed.

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Writing to the CDCE62002

SPI_CLK

Bit0 Bit1 Bit29 Bit30 Bit31

SPI_LE

SPI_MOSI

Reading from the CDCE62002

SPI_ CLK

SPI_ MOSI

SPI_ MISO

SPI_LE

Bit

Bit0 Bit1 Bit2

Bit30 31

Writing to EEPROM

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Figure 17 illustrates a Write to RAM operation. Notice that the latching of the first data bit in the data stream (Bit0) occurs on the first rising edge of SPI_CLK after SPI_LE transitions from a high to a low. For the CDCE62002,data transitions occur on the falling edge of SPI_CLK. A rising edge on SPI_LE signals to the CDCE62002 thatthe transmission of the last bit in the stream (Bit 31) has occurred.

Figure 17. CDCE62002 SPI Write Operation

Figure 18 shows how the CDCE62002 executes a Read Command. The SPI master first issues a ReadCommand to initiate a data transfer from the CDCE62002 back to the host (see Table 6 ). This commandspecifies the address of the register of interest. By transitioning SPI_LE from a low to a high, the CDCE62002resolves the address specified in the appropriate bits of the data field. The host drives SPI_LE low and theCDCE62002 presents the data present in the register specified in the Read Command on SPI_MISO.

Figure 18. CDCE62002 Read Operation

After the CDCE62002 detects a power-up and completes a reset cycle, it copies the contents of the on-boardEEPROM into the Device Registers. Therefore, the CDCE62002 initializes into a known state predefined by theuser. The host issues one of two special commands shown in Table 6 to copy the contents of Device Registers 0through 1 into EERPOM. They include:•Copy RAM to EEPROM – Unlock, Execution of this command can happen many times.•Copy RAM to EEPROM – Lock: Execution of this command can happen only once; after which the EEPROM is permanently locked.

After either command is initiated, power must remain stable and the host must not access the CDCE62002 for atleast 50 ms to allow the EEPROM to complete the write cycle and to avoid the possibility of EEPROM corruption.

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Device Registers: Register 0

CDCE62002

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Table 7. CDCE62002 Register 0 Bit Definitions

SPI RAM BIT RELATED DESCRIPTION / FUNCTIONBIT BIT NAME BLOCK

0 A0 Address 0 01 A1 Address 1 02 A2 Address 2 03 A3 Address 3 04 0 INBUFSELX INBUFSELX Input Buffer Select (LVPECL,LVDS or LVCMOS) EEPROMXY(00 ) Disabled, (01) LVPECL, (10) LVDS, (11) LVCMOS5 1 INBUFSELY INBUFSELY EEPROMThe VBB internal Biasing will be determined from this setting6 2 REFSEL Smart MUX See specific section for more detailed description and configuration EEPROMBits(2,3) setup.7 3 AUXSEL EEPROM00 – RESERVED

10 – REFERENCE Select01 – AUXILARY Select11 – Auto Select ( Reference then AUX)8 4 ACDCSEL Input Buffers If Set to “ 1 ” DC Termination, If set to “ 0 ” AC Termination EEPROM9 5 TERMSEL Input Buffers If Set to “ 0 ” Input Buffer Internal Termination Enabled EEPROM10 6 REFDIVIDE 0 EEPROMReference Divider Settings.11 7 REFDIVIDE 1 EEPROMSee specific section for more detailed description and configuration12 8 REFDIVIDE 2 EEPROMsetup.13 9 REFDIVIDE 3 EEPROM14 10 EXTFEEDBACK External Feedback to PFD from AUX Input enabled when set to “ 1 ” EEPROM15 11 I70TEST TEST Set to “ 0 ” for Normal Operation. EEPROM16 12 ATETEST TEST Set to “ 0 ” for Normal Operation. EEPROM17 13 LOCKW(0) PLL Lock Lock-detect window Bit 0 EEPROM18 14 LOCKW(1) PLL Lock Lock-detect window Bit 1 EEPROM19 15 OUT0DIVRSEL0 Output 0 Output 0 Divider Settings. EEPROMSee specific section for more detailed description and configuration20 16 OUT0DIVRSEL1 Output 0 EEPROMsetup.21 17 OUT0DIVRSEL2 Output 0 EEPROM22 18 OUT0DIVRSEL3 Output 0 EEPROM23 19 OUT1DIVRSEL0 Output 1 Output 1 Divider Settings. EEPROMSee specific section for more detailed description and configuration24 20 OUT1DIVRSEL1 Output 1 EEPROMsetup.25 21 OUT1DIVRSEL2 Output 1 EEPROM26 22 OUT1DIVRSEL3 Output 1 EEPROM27 23 HIPERORMANCE Output 0 & 1 High Performance, If this Bit is set to “ 1 ” : EEPROM– Increase the Bias in the device to achieve Best Phase Noise on theOutput Divider– It changes the LVPECL Buffer to Hi Swing in LVPECL.– It increases the power consumption by 20mA (Typical)28 24 OUTBUFSEL0X Output 0 Output Buffer mode select for OUTPUT “ 0 ” . EEPROM(X,Y)=00:Diabled, 01:LVCMOS, 10:LVDS, 11:LVPECL29 25 OUTBUFSEL0Y Output 0 EEPROM30 26 OUTBUFSEL1X Output 1 Output Buffer mode select for OUTPUT “ 1 ” . EEPROM(X,Y)=00:Diabled, 01:LVCMOS, 10:LVDS, 11:LVPECL31 27 OUTBUFSEL1Y Output 1 EEPROM

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Table 8. Reference Input AC/DC Input Termination Table

REFERENCE INPUT RAM BITS VBB VOLTAGE REF+ REF – TERMINATIONTERMINATION

INTERNAL 0 1 4 5 GENERATOR 5k Ωto VBB 5k Ωto VBBTERMINATION

External Termination X X X 1 OFF OPEN OPENDisable 0 0 X X OFF OPEN OPENLVCMOS 1 1 X 0 OFF OPEN OPENLVPECL-AC 0 1 0 0 1.9V CLOSED CLOSEDLVPECL-DC 0 1 1 0 1.0V CLOSED CLOSEDLVDS-AC 1 0 0 0 1.2V CLOSED CLOSEDLVDS-DC 1 0 1 0 1.2V CLOSED CLOSED

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Device Registers: Register 1

CDCE62002

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Table 9. CDCE62002 Register 1 Bit Definitions

SPI RAM BIT NAME RELATED DESCRIPTION / FUNCTIONBIT BIT BLOCK

0 A0 Address 0 01 A1 Address 1 12 A2 Address 2 13 A3 Address 3 04 0 SELVCO VCO Core VCO Select EEPROM5 1 SELINDIV0 VCO Core Input Divider Settings. EEPROMSee specific section for more detailed description and configuration6 2 SELINDIV1 VCO Core EEPROMsetup.7 3 SELINDIV2 VCO Core EEPROM8 4 SELINDIV3 VCO Core EEPROM9 5 SELINDIV4 VCO Core EEPROM10 6 SELINDIV5 VCO Core EEPROM11 7 SELINDIV6 VCO Core EEPROM12 8 SELINDIV7 VCO Core EEPROM13 9 SELPRESCA VCO Core PRESCALER Setting. EEPROMSee specific section for more detailed description and configuration14 10 SELPRESCB VCO Core EEPROMsetup.15 11 SELFBDIV0 VCO Core FEEDBACK DIVIDER Setting EEPROMSee specific section for more detailed description and configuration16 12 SELFBDIV1 VCO Core EEPROMsetup.17 13 SELFBDIV2 VCO Core EEPROM18 14 SELFBDIV3 VCO Core EEPROM19 15 SELFBDIV4 VCO Core EEPROM20 16 SELFBDIV5 VCO Core EEPROM21 17 SELFBDIV6 VCO Core EEPROM22 18 SELFBDIV7 VCO Core EEPROM23 19 SELBPDIV0 VCO Core BYPASS DIVIDER Setting ( 6 settings + Disable + Enable) EEPROMSee specific section for more detailed description and configuration24 20 SELBPDIV1 VCO Core EEPROMsetup.25 21 SELBPDIV2 VCO Core EEPROM26 22 LFRCSEL0 VCO Core Loop Filter & Charge Pump Control Setting EEPROMSee specific section for more detailed description and configuration27 23 LFRCSEL1 VCO Core EEPROMsetup.28 24 LFRCSEL2 VCO Core EEPROM29 25 LFRCSEL3 VCO Core EEPROM30 26 EELOCK Status EEPROM31 27 EESTATUS Status EEPROM

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Device Registers: Register 2

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Table 10. CDCE62002 Register 2 Bit Definitions

SPI RAM BIT NAME RELATED DESCRIPTION / FUNCTIONBIT BIT BLOCK

0 A0 Address 0 01 A1 Address 1 02 A2 Address 2 03 A3 Address 3 14 0 CFGIN0 Write Only VCO Calibration Word 0 RAM5 1 CFGIN1 Write Only VCO Calibration Word 1 RAM6 2 CFGIN2 Write Only VCO Calibration Word 2 RAM7 3 CFGIN3 Write Only VCO Calibration Word 3 RAM8 4 CFGIN4 Write Only VCO Calibration Word 4 RAM9 5 CFGIN5 Write Only VCO Calibration Word 5 RAM10 6 PLLLOCKPIN Status Read Only: Status of the PLL Lock Pin Driven by the device. PLL Lock RAM= 111 7 PD Control Power Down mode “ On ” when set to “ 0 ” , Off when set to “ 1 ” is normal RAMoperation ( PD bit does not load the EEPROM into RAM when set to" 1 " ).12 8 SYNC Control If toggled “ 1-0-1 ” this bit forces “ SYNC“ resynchronize the Output RAMDividers.13 9 STATUSREF Status Indicates if the reference is available. RAM14 10 VERSION0 Read Only RAM15 11 VERSION1 Read Only RAM16 12 VERSION2 Read Only RAM17 13 PLLRESET VCO Core If toggled “ 0-1-0 ” it Resets PLL to start calibration. “ 0 ” is normal RAMoperation.18 14 CFGOUT0 Read Only VCO Calibration Word 0 RAM19 15 CFGOUT1 Read Only VCO Calibration Word 1 RAM20 16 CFGOUT2 Read Only VCO Calibration Word 2 RAM21 17 CFGOUT3 Read Only VCO Calibration Word 3 RAM22 18 CFGOUT4 Read Only VCO Calibration Word 4 RAM23 19 CFGOUT5 Read Only VCO Calibration Word 5 RAM24 20 CALBRATE Control Calibrate is initiated when this Bit is Set to “ 0 ” than set to “ 1 ” RAMNormal and default condition is “ 1 ”25 21 TITSTCFG0 Diagnostics TI Test Registers. For TI Use Only RAM26 22 TITSTCFG1 Diagnostics TI Test Registers. For TI Use Only RAM27 23 TITSTCFG2 Diagnostics TI Test Registers. For TI Use Only RAM28 24 TITSTCFG3 Diagnostics TI Test Registers. For TI Use Only RAM29 25 MUXSLECTREF Status Read Only: Status of the Smart Mux selection ( Reference is Selected) RAM30 26 MUXSELAUX Status Read Only: Status of the Smart Mux selection ( Auxiliary is Selected) RAM31 27 RAM

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Device Control

Device

OFF

VCO

CAL

Sleep

ActiveMode

PowerON

Reset

PowerDown Sync

Calibration

Hold

Power

Applied

DelayFinished

CAL_Enabled

Sleep = ON

Sleep = OFF

CAL Done

PowerDown = ON

Power Down = OFF

Sync = ON

Sync = OFF

Power Down = ON

Manual

Recalibration =

ON

CDCE62002

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Figure 19 provides a conceptual explanation of the CDCE62002 Device operation. Table 11 defines how thedevice behaves in each of the operational states.

Figure 19. CDCE62002 Device State Control Diagram

Table 11. CDCE62002 Device State Definitions

Output OutputSPI Port PLLState Device Behavior Entered Via Exited Via Divider BufferStatus Status

Status Status

Power-On After device power supply reaches Power applied to the device or Power On Reset and EEPROM OFF Disabled Disabled OFFReset approximately 2.35V, the contents of upon exit from Power Down State loading delays are finished OR theEEPROM are copied into the Device via the Power_Down pin set HIGH. /Power_Down pin is set LOW.Registers, thereby initializing the devicehardware .

Calibration Hold The device waits until either Delay process in the Power-On The device waits until either ON Enabled Disabled OFFENCAL_MODE (Device Register 6 bit Reset State is finished or Sleep ENCAL_MODE (Device Register 627) is low (Start up calibration enabled) Mode ( Sleep bit is in Register 8 bit bit 27) is low (Start up calibrationor both ENCAL_MODE is high (Manual 7) is turned OFF while in the Sleep enabled) or both ENCAL_MODE isCalibration Enabled) AND ENCAL State. Power Down must be OFF high (Manual Calibration Enabled)(Device Register 6 bit 22) transitions to enter the Calibration Hold State. AND ENCAL (Device Register 6 bitfrom a low to a high signaling the 22) transitions from a low to a highdevice. signaling the device.

VCO CAL The voltage controlled oscillator is Calibration Hold: CAL Enabled Calibration Process in completed ON Enabled Disabled OFFcalibrated based on the PLL settings becomes true when eitherand the incoming reference clock. After ENCAL_MODE (Device Register 6the VCO has been calibrated, the device bit 27) is low or bothenters Active Mode automatically. ENCAL_MODE is high ANDENCAL (Device Register 6 bit 22)transitions from a low to a high.Active Mode: A ManualRecalibration is requested. This isinitiated by setting ENCAL_MODEto HIGH (Manual CalibrationEnabled) AND initiating acalibration sequence by applying aLOW to HIGH transition onENCAL.

Active Mode Normal Operation CAL Done (VCO calibration Sync, Power Down, Sleep, or ON Enabled Disabled Disabled orprocess finished) or Sync = OFF Manual Recalibration activated. or Enabled(from Sync State). Enabled

Power Down Used to shut down all hardware and PD pin is pulled LOW. PD pin is pulled HIGH and SPI_LE ON Disabled Disabled DisabledResets the device after exiting the Pin is HIGH to insure EEPROMPower Down State. Therefore, the Loading.EEPROM contents will eventually becopied into RAM after the Power DownState is exited.

Product Folder Link(s): CDCE62002

External Control Pins

FACTORY DEFAULT PROGRAMMING

XTAL

25Mhz

U0P

U0N

U1P

U1N

LVPECL

156.25Mhz

LVDS

125Mhz

AUTO

25Mhz

CDCE62002

Default Programing

Register 0

Register Content

Register 1

72A000E0

8389A061

EEPROM

CDCE62002

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Power Down ( PD)

When pulled LOW, PD activates the Power Down state which shuts down all hardware and resets the device.Restoring PD high will cause the CDCE62002 to exit the Power Down State. This causes the device to behaveas if it has been powered up including copying the EEPROM contents into RAM. PD pin also has a shadowedPD bit residing in Register 2 Bit 7. When asserted Low it puts the device in Power Down Mode, but it does notload the EEPROM when the bits is disserted.

NOTE:

The SPI_LE signal has to be high in order for the EEPROM to load correctly into RAMon the Rising edge of PD Pin.

The CDCE62002 is factory pre-programmed to work with 25MHz input from the reference input or from theauxiliary input with auto switching enabled. An internal PFD of 6.25MHz and about 400KHz loop bandwidth.Output 0 is pre-programmed as an LCPECL driver to output 156.25MHz and output 1 is pre-programmed asLVDS driver to output 125MHz.

Figure 20. CDCE62002 Default Factory Programming

Product Folder Link(s): CDCE62002

INPUT BLOCK

ReferenceDivider

/1 - /8

PRI_IN

XTAL /

AUX_IN

LVPECL : 500 MHz

LVDS: 500 MHz

LVCMOS : 250 MHz

Crystal : 2 MHz – 42 MHz

SingleEnded : 2 MHz - 75 MHz

Smart

MUX

SmartMUX

Control

2 3

Register 0

8 7 6

Register 0

9

1

Register 0

UniversalInputBuffers

SmartMultiplexer

AuxiliaryInput

Pre-Divider

/1 or /2

0

CDCE62002

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The Input Block includes one Universal Input Buffers, an Auxiliary Input, and a Smart Multiplexer.

Figure 21. CDCE62002 Input Block With References to Registers

The CDCE62002 provides a Reference Divider that divides the clock exiting Reference (REF_IN) input buffer.

Table 12. CDCE62002 Reference Divider Settings

REFERENCE DIVIDER TOTAL

DIVIDEBIT NAME →REFDIVIDE3 REFDIVIDE2 REFDIVIDE1 REFDIVIDE0

RATIOREGISTER BIT →0.9 0.8 0.7 0.6

0 0 0 0 /10 0 0 1 /20 0 1 0 /30 0 1 1 /40 1 0 0 /50 1 0 1 /60 1 1 0 /70 1 1 1 /81 0 0 0 /21 0 0 1 /41 0 1 0 /61 0 1 1 /81 1 0 0 /101 1 0 1 /121 1 1 0 /141 1 1 1 /16

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Reference Input Buffer

UniversalInputControl

PN PP

Register 0

0 1 4

Register 0

0

5

REF_IN

V

bb

1uF

V

bb

0.0 0.1 0.4 0.5

INBUFSELX INBUFSELY ACDCSEL TERMSEL P N VBB

0

X 1 OFF OFF

0 1 1

OFF

1 0

0

0ON ON

0 1 0 ON ON

SWITCHStatus VBB

Settings

1

X X

0ON ON

1

0

1.9V

ON ON 1.2V

1.2V

BitName -->

Register.Bit -->

INBUFSELX INBUFSELY

0.0 0.1

LVDS

0 0 Disable

0 1 LVPECL

1 0

LVCMOS1 1

InputBufferSelect InputBuffer

Mode

5k 5k

Smart Multiplexer Dividers

ReferenceDivider

/1 - /8

PRI_IN

XTAL /

AUX_IN

Smart

MUX

SmartMUX

Control

2 3

Register 0

876

Register 0

9

1

Register 0

SmartMultiplexer

Pre-Divider

/1 or /2

0

PRISEL AUXSEL

0.2 0.3

AUXSelect

0 0 Reserved

1 0 REFSelect

0 1

AutoSelect

1 1

Setting SmartMux

Mode

CDCE62002

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Figure 22 shows the key elements of a Universal Input Buffer (UIB). A UIB supports multiple formats along withdifferent termination and coupling schemes. The CDCE62002 implements the UIB by including on boardswitched termination, a programmable bias voltage generator, and a multiplexer. The CDCE62002 provides ahigh degree of configurability on the UIB to facilitate most existing clock input formats.

Figure 22. CDCE62002 Universal Input Buffer

Figure 23. CDCE62002 Smart Multiplexer

In Auto Select Mode the Smart Mux switches automatically between Reference input and Auxiliary input with apreference to the Reference input. In order for the Smart Mux to function correctly the frequency after thereference divider and the Auxiliary Input signal frequency should be within 20% of each other or one of themshould be zero or ground.

Product Folder Link(s): CDCE62002

Auxiliary Input Port

External Feedback Mode

FB

PFD/

CP

Feedback

Divider

Divby 1

REF

CDCE62002

SCAS882 – JUNE 2009 ......................................................................................................................................................................................................

www.ti.com

The auxiliary input on the CDCE62002 is designed to connect to an AT-Cut Crystal with a total load capacitanceof 8 pF to 18pF. One side of the crystal connects to Ground while the other side connects to the Auxiliary input ofthe device. The circuit accepts crystals from 2 to 42 MHz.

Since the Auxiliary input operates between 0 and 2 Volts with a crystal, it can accept single-ended signals (e.g.,LVCMOS). Electrically, it is equivalent to an LVCMOS input buffer with 8 pF of input capacitance.

Figure 24. CDCE62002 Auxiliary Input Port

The auxiliary input on the CDCE62002 is to serve as an external feedback port if Bit (10) in Register 0 is set to“ 1 ” and input smart Mux setting is set to Reference input. In addition, The Reference Divider and the input dividerhave to be set to divide by 1. This feature is implemented to allow direct access to the PFD of the PLL. Thedelay from Reference input to PFD and from Auxiliary Reference to PFD is not matched. However, in close loopsystem where the device output is fed to close the loop the delay difference between the Reference and Externalfeedback path will cancel out.

Figure 25. CDCE62002 in External Feedback Mode

Product Folder Link(s): CDCE62002

OUTPUT BLOCK

ClockDividerModule 1

UxP

UxN

SYNTH

Sync

Pulse Enable

LVDS

ClockDividerModule 0

LVPECL

OutputBufferControl

Registers 0

18171615

Registers 0

22212019

OUTPUT 0 OUTPUT 1

CDCE62002

www.ti.com

...................................................................................................................................................................................................... SCAS882 – JUNE 2009

The output block includes two identical output channels. Each output channel comprises of a clock dividermodule, and a universal output buffer as shown in Figure 26 .

Figure 26. CDCE62002 Output Channel

Table 13. CDCE62002 Output Divider Settings

OUTPUT DIVIDERS SETTING

DIVIDER 0 →0.18 0.17 0.16 0.15 DIVIDE RATIO

DIVIDER 1 →0.22 0.21 0.20 0.19

0 0 0 0 Disable0 0 0 1 /10 0 1 0 /20 0 1 1 /30 1 0 0 /40 1 0 1 /50 1 1 0 /60 1 1 1 Disable1 0 0 0 /81 0 0 1 Disable1 0 1 0 /101 0 1 1 /201 1 0 0 /121 1 0 1 /241 1 1 0 /161 1 1 1 /32

Product Folder Link(s): CDCE62002

SYNTHESIZER BLOCK

PFD/

CP

Prescaler

/2,/3,/4,/5

InputDivider

/1 - /256

SMART _MUX

SYNTH

70 kHz –

400 kHz

/1,/2,/5,/8,/10,/16,/20

/8 - /1280

FeedbackDivider

1.75 GHz –

2.356 GHz

Register 1

22232425

LoopFilterandChargePump

CurrentSettings

1

Register 1

2345678

InputDividerSettings

Register 1

89

Prescaler

11

Register 1

12131415161718

FeedbackDivider

Register 1

192021

FeedbackBypassDivider

Register 1

0

VCOSelect

Input Divider

CDCE62002

SCAS882 – JUNE 2009 ......................................................................................................................................................................................................

www.ti.com

Figure 27 provides an overview of the CDCE62002 synthesizer block. The Synthesizer Block provides a PhaseLocked Loop, a partially integrated programmable loop filter, and two Voltage Controlled Oscillators (VCO). Thesynthesizer block generates an output clock called “ SYNTH ” and drives it onto the Internal Clock DistributionBus.

Figure 27. CDCE62002 Synthesizer Block

The Input Divider divides the clock signal selected by the Smart Multiplexer and presents the divided signal tothe Phase Frequency Detector / Charge Pump of the frequency synthesizer.

Table 14. CDCE62002 Input Divider Settings

INPUT DIVIDER SETTINGS

DIVIDESELINDIV7 SELINDIV6 SELINDIV5 SELINDIV4 SELINDIV3 SELINDIV2 SELINDIV1 SELINDIV0

RATIO1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1

000000001000000012000000103000000114010001005010001016––––––––––––––––––11111111256

Product Folder Link(s): CDCE62002

Feedback and Feedback Bypass Divider

CDCE62002

www.ti.com

...................................................................................................................................................................................................... SCAS882 – JUNE 2009

Table 15 shows how to configure the Feedback divider for various divide values:

Table 15. CDCE62002 Feedback Divider Settings

FEEDBACK DIVIDER

DIVIDESELFBDIV7 SELFBDIV6 SELFBDIV5 SELFBDIV4 SELFBDIV3 SELFBDIV2 SELFBDIV1 SELFBDIV0

RATIO1.18 1.17 1.16 1.15 1.14 1.13 1.12 1.11

0000000080000000112000000111600000011200000010124000001103200001001360000011140000010104800011000560000101160000011106400010101720000111180000110018400010110960001001110001101001108000110101120001011112000011110128000110111400001010114400011111160001111111680100101118000110110192001100112000101010121600111010224001101112400101100125200111110256001110112800101011028801010011300001111113200101101033601010111360010111103841101100039201110011400

Product Folder Link(s): CDCE62002

CDCE62002

SCAS882 – JUNE 2009 ......................................................................................................................................................................................................

www.ti.com

Table 15. CDCE62002 Feedback Divider Settings (continued)

FEEDBACK DIVIDER

DIVIDESELFBDIV7 SELFBDIV6 SELFBDIV5 SELFBDIV4 SELFBDIV3 SELFBDIV2 SELFBDIV1 SELFBDIV0

RATIO1.18 1.17 1.16 1.15 1.14 1.13 1.12 1.11

01011011420101101014320111101044801011111480100100115001011100150401111110512011110115601011011057611011001588100101116000111111164010111010672100110117001011011172010111110768110110107841001111180010111011840110111108961011111196011011011980111111101024110111111120111111111280

Table 16 shows how to configure the Feedback Bypass Divider.

Product Folder Link(s): CDCE62002

VCO Select

Prescaler

CDCE62002

www.ti.com

...................................................................................................................................................................................................... SCAS882 – JUNE 2009

Table 16. CDCE62002 Feedback Bypass Divider Settings

FEEDBACK BYPASS DIVIDER

SELBPDIV2 SELBPDIV1 SELBPDIV0 DIVIDE RATIO

1.21 1.20 1.19

0002001501080 1 1 101 0 0 161 0 1 201 1 0 RESERVED1 1 1 1(bypass)

Table 17 illustrates how to control the dual voltage controlled oscillators.

Table 17. CDCE62002 VCO Select

VCO SELECT

VCO CHARACTERISTICSBIT NAME →SELVCO

REGISTER NAME →1.0 VCO RANGE Fmin (MHz) Fmax (MHz)

0 Low 1750 20461 High 2040 2356

Table 18 shows how to configure the prescaler.

Table 18. CDCE62002 Prescaler Settings

SETTINGS

SELPRESCB SELPRESCA DIVIDE RATIO

1.10 1.9

005104013112

Product Folder Link(s): CDCE62002

Loop Filter

PFD/

CP

EXT_LFNEXT_LFP

externalinternal externalinternal

+

-

VB

C1

R2 C2

R3

C3

24

Registers 0

2325 22

CDCE62002

SCAS882 – JUNE 2009 ......................................................................................................................................................................................................

www.ti.com

Figure 28 depicts the loop filter topology of the CDCE62002. It facilitates both internal and externalimplementations providing optimal flexibility.

Figure 28. CDCE62002 Loop Filter Topology

Internal Loop Filter Component Configuration

Figure 28 illustrates the switching between four fixed internal loop filter settings and the external loop filtersetting. Table 19 shows that the CDCE62002 has 16 settings different settings for the loop filter. Four of thesettings are internal and twelve are external.

Table 19. CDCE62002 Loop Filter Settings

ChargeLFRCSEL 3 db Corner Pump

3 2 1 0 Loop Filter C1 C2 R2 R3 C3 C3R3 Current

0 0 0 0 Internal 1.5 pF 473.5 pF 4.0k 5k 2.5 pF 12 MHz 1.5 mA0 0 0 1 Internal 1.5 pF 473.5 pF 4.0k 5k 2.5 pF 12 MHz 400 µA0 0 1 0 Internal 1.5 pF 473.5 pF 2.7k 5k 2.5 pF 12 MHz 250 µA0 0 1 1 Internal 1.5 pF 473.5 pF 2.7k 5k 2.5 pF 12 MHz 150 µA0 1 0 0 External X X X 20k 112 pF 70 kHz 1.0 mA0 1 0 1 External X X X 20k 112 pF 70 kHz 2.0 mA0 1 1 0 External X X X 20k 112 pF 70 kHz 3.0 mA0 1 1 1 External X X X 20k 112 pF 70 kHz 3.75 mA1 0 0 0 External X X X 10k 100 pF 150 kHz 1.0 mA1 0 0 1 External X X X 10k 100 pF 150 kHz 2.0 mA1 0 1 0 External X X X 10k 100 pF 150 kHz 3.0 mA1 0 1 1 External X X X 10k 100 pF 150 kHz 3.75 mA1 1 0 0 External X X X 5k 100 pF 300 kHz 1.0 mA1 1 0 1 External X X X 5k 64 pF 500 kHz 2.0 mA1 1 1 0 External X X X 5k 48 pF 700 kHz 3.0 mA1 1 1 1 External X X X 5k 38 pF 800 kHz 3.75 mA

Product Folder Link(s): CDCE62002

Lock Detect

PFD/

CP

FromInputDivider

FromFeedbackDivider

ToLoopFilter

FromInputDivider

FromFeedbackDivider

Locked

Unlocked

FromInputDivider

FromFeedbackDivider

Register 0

LockDetectWindow (Max)

LockDetectWindow Adjust

(a) (b)

13 14

FromLockDetector PLL_LOCK

1 = Locked

O = Unlocked

(c)

CDCE62002

www.ti.com

...................................................................................................................................................................................................... SCAS882 – JUNE 2009

The CDCE62002 provides a lock detect indicator circuit that can be detected on an external Pin PLL_LOCK (Pin32) and internally by reading PLLLOCKPIN bit (6) in Register 2.

Two signals whose phase difference is less than a prescribed amount are ‘ locked ’ otherwise they are ‘ unlocked ’ .The phase frequency detector / charge pump compares the clock provided by the input divider and the feedbackdivider; using the input divider as the phase reference. The lock detect circuit implements a programmable lockdetect window. Table 20 shows an overview of how to configure the lock detect feature. The PLL_LOCK pin willpossibly jitter several times between lock and out of lock until the PLL achieves a stable lock. If desired, choosinga wide loop bandwidth and a high number of successive clock cycles virtually eliminates this characteristic.PLL_LOCK will return to out of lock, if just one cycle is outside the lock detect window or if a cycle slip occurs.

Figure 29. CDCE62002 Lock Detect

Table 20. CDCE62002 Lock Detect Control

LOCK DETECT

LOCK DETECTBIT NAME →LOCKW(1) LOCKW(0)

WINDOWREGISTER NAME →0.13 0.14

0 0 2.1 ns0 1 4.6 ns1 0 7.2 ns1 1 19.9 ns

Product Folder Link(s): CDCE62002

Device Power Calculation and Thermal Management

No Solder Mask

Internal

Power

Plane

Component Side

Back Side

Solder Mask

Thermal Vias

QFN-32 Thermal Slug

(package bottom)

Thermal

Dissipation

Pad (back side)

Internal

Ground

Plane

CDCE62002 Power Supply Bypassing – Recommended Layout

Component & Back Side Component Side

Only

CDCE62002

SCAS882 – JUNE 2009 ......................................................................................................................................................................................................

www.ti.com

The CDCE62002 is a high performance device; therefore careful attention must be paid to device configurationand printed circuit board layout with respect to power consumption. Table 21 provides the power consumption forthe individual blocks within the CDCE62002. To estimate total power consumption, calculate the sum of theproducts of the number of blocks used and the power dissipated of each corresponding block.

Table 21. CDCE62002 Power Consumption

INTERNAL BLOCK POWER DISSIPATED NUMBER OF BLOCKS(Power at 3.3V) PER BLOCK PER DEVICE

Input Circuit 32 1PLL and VCO Core 333 1Output Divider 92 2Output Buffer ( LVPECL) 150 2Output Buffer (LVDS) 95 2Output Buffer (LVCMOS) 62 4

This power estimate determines the degree of thermal management required for a specific design. Observinggood thermal layout practices enables the thermal pad on the backside of the QFN-32 package to provide agood thermal path between the die contained within the package and the ambient air. This thermal pad alsoserves as the ground connection the device; therefore, a low inductance connection to the ground plane isessential.

Figure 30. CDCE62002 Recommended PCB Layout

Figure 31 shows a conceptual layout focusing on power supply bypass capacitor placement. If the capacitors aremounted on the back side, 0402 components can be employed; however, soldering to the Thermal DissipationPad can be difficult. If the capacitors are mounted on the component side, 0201 components must be used tofacilitate signal routing. In either case, the connections between the capacitor and the power supply terminal onthe device must be kept as short as possible.

Figure 31. CDCE62002 Power Supply Bypassing

Product Folder Link(s): CDCE62002

APPLICATION INFORMATION AND GENERAL USAGE HINTS

Clock Generator

XTAL /

AUX_IN Output

Divider 0

U0P

U0N

PFD/

CP Prescaler

Feedback

Divider

Input

Divider

Smart

MUX

Output

Divider 1

U1P

U1N

External Feedback Option

Output

Divider 0

U0P

U0N

Output

Divider 1

U1P

U1N

PFD/

CP

Prescaler

Feedback

Divider

Divby 1

REF

FB

LF

100nF

CDCE62002

www.ti.com

...................................................................................................................................................................................................... SCAS882 – JUNE 2009

The CDCE62002 can generate 1 to 4 low noise clocks from a single crystal or crystal oscillator as follows:

Figure 32. CDCE62002 as a Clock Generator

The CDCE62002 has a limited optional external feedback path that give access to the PFD inside the device.This option enables customers to implement complex or custom PLL designed to control the VCO inside theCDCE62002. In addition, the External feedback allows the device to operate in a deterministic delay mode wherethe reference to output delay is fixed but dependable on the routing path length from the outputs to the auxiliaryinput pin. Figure 33 illustrates how the output is loopback to the Auxiliary Input in bypass mode to put the devicein fixed delay mode.

Figure 33. CDCE62002 External Feedback Example

This function is limited by the output divider divide ratio and scan be implemented when one of the outputs is setfrom 10.94 MHz to 40.00MHz.

Product Folder Link(s): CDCE62002

SERDES Startup and Clock Cleaner

SERDES

CleanedClock

Data

RecoveredClock

Output

Divider 0

U0P

U0N

Output

Divider 1

U1P

U1N

PFD/

CP Prescaler

Feedback

Divider

Input

Divider

Reference

Divider

PRI_IN

XTAL /AUX_IN

EXT_LFP EXT _LFN

CDCE62002

SCAS882 – JUNE 2009 ......................................................................................................................................................................................................

www.ti.com

The CDCE62002 can serve as a SERDES device companion by providing a crystal based reference for theSERDES device to lock to receive data stream and when the SERDES locks to the data and outputs therecovered clock the CDCE62002 can switch and use the recovered clock and serve as a jitter cleaner.

Figure 34. CDCE62002 Clocking SERDES

Since the jitter of the recovered clock can be above 100 ps (RMS) the output jitter from CDCE62002 can be aslow and 6 ps (RMS) depending on the external loop filter configuration.

Product Folder Link(s): CDCE62002

CLOCKING ADCS WITH THE CDCE62002

jitter 10

in total

1

SNR 20log 2 jitter

é ù

=ê ú

ë û

fp

(4)

( ) ( )

2 2

total ADC CLK

jitter jitter jitter= +

(5)

A D C

S N R 6 . 0 2 N 1 .7 6= +

(6)

DataConverterJitterRequirements

0

10

20

30

40

50

60

70

80

90

100

110

120

130

140

1 10 100 1000 10000

InputBandwidth(MHz)

SNR(dB)

0

2

4

6

8

10

12

14

16

18

20

22

24

26

Resolution(bits)

1ps

350fs

100fs

50fs

CDCE62002

www.ti.com

...................................................................................................................................................................................................... SCAS882 – JUNE 2009

High-speed analog to digital converters incorporate high input bandwidth on both the analog port and the sampleclock port. Often the input bandwidth far exceeds the sample rate of the converter. Engineers regularlyimplement receiver chains that take advantage of the characteristics of bandpass sampling. This implementationtrend often causes engineers working in communications system design to encounter the term “ clock limitedperformance ” . Therefore, it is important to understand the impact of clock jitter on ADC performance. Thefollowing equation shows the relationship of data converter signal to noise ratio (SNR) to total jitter:

Total jitter comprises two components: the intrinsic aperture jitter of the converter and the jitter of the sampleclock:

With respect to an ADC with N-bits of resolution, ignoring total jitter, ADC quantization error, and input noise, thefollowing equation shows the relationship between resolution and SNR:

Figure 35 plots Equation 4 and Equation 6 for constant values of total jitter. When used in conjunction with mostADCs, the CDCE62002 supports a total jitter performance value of < 1ps.

Figure 35. Data Converter Jitter Requirements

Product Folder Link(s): CDCE62002

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

CDCE62002RHBR ACTIVE QFN RHB 32 3000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

CDCE62002RHBT ACTIVE QFN RHB 32 250 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 2-Jul-2009

Addendum-Page 1

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm) W

(mm) Pin1

Quadrant

CDCE62002RHBR QFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2

CDCE62002RHBT QFN RHB 32 250 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 1-Jul-2009

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

CDCE62002RHBR QFN RHB 32 3000 340.5 333.0 20.6

CDCE62002RHBT QFN RHB 32 250 340.5 333.0 20.6

PACKAGE MATERIALS INFORMATION

www.ti.com 1-Jul-2009

Pack Materials-Page 2

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