ADF4360-0BCPZ - Analog Devices

Integrated Synthesizer and VCO

Data Sheet

ADF4360-0

Rev. B

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

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Tel: 781.329.4700 www.analog.com

FEATURES

Output frequency range: 2400 MHz to 2725 MHz

Divide-by-2 output

3.0 V to 3.6 V power supply

1.8 V logic compatibility

Integer-N synthesizer

Programmable dual-modulus prescaler 16/17, 32/33

Programmable output power level

3-wire serial interface

Analog and digital lock detect

Hardware and software power-down mode

APPLICATIONS

Wireless handsets (DECT, GSM, PCS, DCS, WCDMA)

Test equipment

Wireless LANs

CATV equipment

GENERAL DESCRIPTION

The ADF4360-0 is a fully integrated integer-N synthesizer and

voltage-controlled oscillator (VCO). The ADF4360-0 is

designed for a center frequency of 2600 MHz. In addition, a

divide-by-2 option is available, whereby the user gets an RF

output of between 1200 MHz and 1360 MHz.

Control of all the on-chip registers is through a simple 3-wire

interface. The device operates with a power supply ranging

from 3.0 V to 3.6 V and can be powered down when not in use.

FUNCTIONAL BLOCK DIAGRAM

MUXOUT

VCO

REF

CLK

DATA

AGND DGND CPGND

SET

TUNE

OUT

VCO

CORE

PHASE

COMPARATOR

MUTE

DIVSEL = 2

DIVSEL = 1

N = (BP + A)

LOAD

CHARGE

PUMP

OUTPUT

STAGE

MULTIPLEXER

INTEGER

13-BIT B

COUNTER

14-BIT R

COUNTER

24-BIT

FUNCTION

LATCH

24-BIT

DATA REGISTER

5-BIT A

COUNTER

PRESCALER

P/P+1

MULTIPLEXER

LOCK

DETECT

÷2

ADF4360-0

04644-001

Figure 1.

ADF4360-0 Data Sheet

Rev. B | Page 2 of 24

TABLE OF CONTENTS

Specifications..................................................................................... 3

Timing Characteristics..................................................................... 5

Absolute Maximum Ratings............................................................ 6

Transistor Count ........................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Circuit Description........................................................................... 9

Reference Input Section............................................................... 9

Prescaler (P/P + 1)........................................................................ 9

A and B Counters ......................................................................... 9

R Counter ...................................................................................... 9

PFD and Charge Pump................................................................ 9

MUXOUT and Lock Detect...................................................... 10

Input Shift Register..................................................................... 10

VCO ............................................................................................. 10

Output Stage................................................................................ 11

Latch Structure ........................................................................... 12

Power-Up..................................................................................... 16

Control Latch.............................................................................. 18

N Counter Latch......................................................................... 19

R Counter Latch ......................................................................... 19

Applications..................................................................................... 20

Fixed Frequency LO................................................................... 20

Interfacing ................................................................................... 20

PCB Design Guidelines for Chip Scale Package........................... 21

Output Matching........................................................................ 21

Outline Dimensions ....................................................................... 22

Ordering Guide .......................................................................... 22

REVISION HISTORY

2/12—Rev. A to Rev. B

Changes to Figure 3 and Table 4..................................................... 7

Updated Outline Dimensions....................................................... 22

Changes to Ordering Guide .......................................................... 22

12/04—Rev. 0 to Rev. A

Updated Format..................................................................Universal

Changes to Timing Characteristics ................................................ 5

Changes to Power-Up Section ...................................................... 16

Added Table 10 ............................................................................... 16

Added Figure 16.............................................................................. 16

Changes to Ordering Guide .......................................................... 22

Updated Outline Dimensions....................................................... 22

7/04—Revision 0: Initial Version

Data Sheet ADF4360-0

Rev. B | Page 3 of 24

SPECIFICATIONS1

AVDD = DVDD = VVCO = 3.3 V ± 10%; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted.

Table 1.

Parameter B Version Unit Conditions/Comments

REFIN CHARACTERISTICS

REFIN Input Frequency 10/250 MHz min/max For f < 10 MHz, use dc-coupled

CMOS-compatible square wave, slew rate > 21 V/μs.

REFIN Input Sensitivity 0.7/AVDD V p-p min/max AC-coupled.

0 to AVDD V max CMOS-compatible.

REFIN Input Capacitance 5.0 pF max

REFIN Input Current ±100 μA max

PHASE DETECTOR

Phase Detector Frequency2 8 MHz max

CHARGE PUMP

ICP Sink/Source3 With RSET = 4.7 kΩ.

High Value 2.5 mA typ

Low Value 0.312 mA typ

RSET Range 2.7/10 kΩ

ICP Three-State Leakage Current 0.2 nA typ

Sink and Source Current Matching 2 % typ 1.25 V ≤ VCP ≤ 2.5 V.

ICP vs. VCP 1.5 % typ 1.25 V ≤ VCP ≤ 2.5 V.

ICP vs. Temperature 2 % typ VCP = 2.0 V.

LOGIC INPUTS

VINH, Input High Voltage 1.5 V min

VINL, Input Low Voltage 0.6 V max

IINH/IINL, Input Current ±1 μA max

CIN, Input Capacitance 3.0 pF max

LOGIC OUTPUTS

VOH, Output High Voltage DVDD – 0.4 V min CMOS output chosen.

IOH, Output High Current 500 μA max

VOL, Output Low Voltage 0.4 V max IOL = 500 μA.

POWER SUPPLIES

AVDD 3.0/3.6 V min/V max

DVDD AVDD

VVCO AVDD

AIDD4 10 mA typ

DIDD4 2.5 mA typ

IVCO4, 5 19.0 mA typ ICORE = 10 mA.

IRFOUT4 3.5 to 11.0 mA typ RF output stage is programmable.

Low Power Sleep Mode4 7 μA typ

RF OUTPUT CHARACTERISTICS5

VCO Output Frequency 2400/2725 MHz min/max ICORE = 15 mA.

VCO Sensitivity 56 MHz/V typ

Lock Time6 250 μs typ To within 10 Hz of final frequency.

Frequency Pushing (Open-Loop) 1 MHz/V typ

Frequency Pulling (Open-Loop) 15 kHz typ Into 2.00 VSWR load.

Harmonic Content (Second) −30 dBc typ

Harmonic Content (Third) −39 dBc typ

Output Power5, 7 −13/−6.5 dBm typ Programmable in 3 dB steps. See Table 7.

Output Power Variation ±3 dB typ For tuned loads, see the Output Matching section.

VCO Tuning Range 1.25/2.50 V min/max

VCO Tuning Port Leakage Current 0.2 nA typ

ADF4360-0 Data Sheet

Rev. B | Page 4 of 24

Parameter B Version Unit Conditions/Comments

NOISE CHARACTERISTICS5

VCO Phase-Noise Performance8 −111 dBc/Hz typ @ 100 kHz offset from carrier.

−133 dBc/Hz typ @ 1 MHz offset from carrier.

−140 dBc/Hz typ @ 3 MHz offset from carrier.

−145 dBc/Hz typ @ 10 MHz offset from carrier.

Synthesizer Phase-Noise Floor9 −172 dBc/Hz typ @ 25 kHz PFD frequency.

−163 dBc/Hz typ @ 200 kHz PFD frequency.

−147 dBc/Hz typ @ 8 MHz PFD frequency.

In-Band Phase Noise10, 11 −80 dBc/Hz typ @ 1 kHz offset from carrier.

RMS Integrated Phase Error12 1.4 Degrees typ 100 Hz to 100 kHz.

Spurious Signals due to PFD Frequency11, 13 −75 dBc typ

Level of Unlocked Signal with MTLD Enabled −45 dBm typ

1 Operating temperature range is: –40°C to +85°C.

2 Guaranteed by design. Sample tested to ensure compliance.

3 ICP is internally modified to maintain constant loop gain over the frequency range.

4 TA = 25°C; AVDD = DVDD = VVCO = 3.3 V; P = 32.

5 These characteristics are guaranteed for VCO core power = 10 mA.

6 Jumping from 2.4 GHz to 2.725 GHz. PFD frequency = 200 kHz; loop bandwidth = 10 kHz.

7 Using 50 Ω resistors to VVCO into a 50 Ω load. For tuned loads, see the Output Matching section.

8 The noise of the VCO is measured in open-loop conditions.

9 The synthesizer phase-noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value).

10 The phase noise is measured with the EVAL-ADF4360-xEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the

synthesizer; offset frequency = 1 kHz.

11 fREFIN = 10 MHz; fPFD = 200 kHz; N = 2600; Loop B/W = 10 kHz.

12 fREFIN = 10 MHz; fPFD = 1 MHz; N = 2600; Loop B/W = 25 kHz.

13 The spurious signals are measured with the EVAL-ADF4360-xEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for

the synthesizer; fREFOUT = 10 MHz @ 0 dBm.

Data Sheet ADF4360-0

Rev. B | Page 5 of 24

TIMING CHARACTERISTICS1

AVDD = DVDD = VVCO = 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; TA = TMIN to TMAX, unless otherwise noted.

Table 2.

Parameter Limit at TMIN to TMAX (B Version) Unit Test Conditions/Comments

t1 20 ns min LE Setup Time

t2 10 ns min DATA to CLOCK Setup Time

t3 10 ns min DATA to CLOCK Hold Time

t4 25 ns min CLOCK High Duration

t5 25 ns min CLOCK Low Duration

t6 10 ns min CLOCK to LE Setup Time

t7 20 ns min LE Pulse Width

1 See the section for the recommended power-up procedure for this device. Power-Up

CLOC

DATA

DB23 (MSB) DB22 DB2 DB1

(CONTROL BIT C2) DB0 (LSB)

(CONTROL BIT C1)

04644-002

Figure 2. Timing Diagram

ADF4360-0 Data Sheet

Rev. B | Page 6 of 24

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

AVDD to GND1 −0.3 V to +3.9 V

AVDD to DVDD −0.3 V to +0.3 V

VVCO to GND −0.3 V to +3.9 V

VVCO to AVDD −0.3 V to +0.3 V

Digital I/O Voltage to GND −0.3 V to VDD + 0.3 V

Analog I/O Voltage to GND −0.3 V to VDD + 0.3 V

REFIN to GND −0.3 V to VDD + 0.3 V

Operating Temperature Range −40°C to + 85°C

Storage Temperature Range −65°C to +150°C

Maximum Junction Temperature 150°C

CSP θJA Thermal Impedance

Paddle Soldered 50°C/W

Paddle Not Soldered 88°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C

1 GND = AGND = DGND = 0 V.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those included in the operational

sections of this specification is not implied. Exposure to

absolute maximum rating conditions for extended periods may

affect device reliability.

This device is a high performance RF integrated circuit with an

ESD rating of <1 kV and it is ESD sensitive. Proper precautions

should be taken for handling and assembly.

TRANSISTOR COUNT

12543 (CMOS) and 700 (Bipolar).

ESD CAUTION

Data Sheet ADF4360-0

Rev. B | Page 7 of 24

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

ADF4360-0

TOP VI EW

(Not to Scale)

CPGND

NOTES

1. THE EXPOSED PAD MUST BE CONNECTED TO AGND.

AVDD 2

AGND 3

RFOUTA4

RFOUTB5

VVCO 6

DATA18

CLK

REFIN

DGND15

RSET

VTUNE 7

AGND 8

AGND 9

AGND 10

AGND 11

CC12

CP24

AGND22

DVDD

MUXOUT

LE19

04644-003

PIN 1

IDENTIFIER

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Function

1 CPGND Charge Pump Ground. This is the ground return path for the charge pump.

2 AVDD Analog Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane should be

placed as close as possible to this pin. AVDD must have the same value as DVDD.

3, 8 to 11, 22 AGND Analog Ground. This is the ground return path of the prescaler and VCO.

4 RFOUTA VCO Output. The output level is programmable from −6.5 dBm to −13 dBm. See the Output Matching section for a

description of the various output stages.

5 RFOUTB VCO Complementary Output. The output level is programmable from −6.5 dBm to −13 dBm. See the Output

Matching section for a description of the various output stages.

6 VVCO Power Supply for the VCO. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane should

be placed as close as possible to this pin. VVCO must have the same value as AVDD.

7 VTUNE Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP output

voltage.

12 CC Internal Compensation Node. This pin must be decoupled to ground with a 10 nF capacitor.

13 RSET Connecting a resistor between this pin and CPGND sets the maximum charge pump output current for the synthesizer.

The nominal voltage potential at the RSET pin is 0.6 V. The relationship between ICP and RSET is

SET

CPmax R

I75.11

where RSET = 4.7 kΩ, ICPmax = 2.5 mA.

14 CN Internal Compensation Node. This pin must be decoupled to VVCO with a 10 μF capacitor.

15 DGND Digital Ground.

16 REFIN Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of 100

kΩ. See Figure 10. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled.

17 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit

shift register on the CLK rising edge. This input is a high impedance CMOS input.

18 DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high

impedance CMOS input.

19 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four

latches, and the relevant latch is selected using the control bits.

20 MUXOUT This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be accessed

externally.

21 DVDD Digital Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the digital ground plane should be

placed as close as possible to this pin. DVDD must have the same value as AVDD.

23 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode.

Taking the pin high powers up the device depending on the status of the power-down bits.

24 CP Charge Pump Output. When enabled, this provides ± ICP to the external loop filter, which in turn, drives the internal

VCO.

EP Exposed Pad. The exposed pad must be connected to AGND.

ADF4360-0 Data Sheet

Rev. B | Page 8 of 24

TYPICAL PERFORMANCE CHARACTERISTICS

04644-004

–150

–160

–170

–140

–130

–120

–110

–100

–90

–80

–70

–40

–50

–60

–30

–20

–10

1k 10M1M100k10k FREQUENCY OFFSET (Hz)

OUTPUT POWER (dB)

Figure 4. Open-Loop VCO Phase Noise

04644-005

–145

–150

–140

–135

–130

–125

–120

–115

–110

–105

–90

–95

–100

–85

–80

–75

–70

100 10M1M100k10k1000 FREQUENCY OFFSET (Hz)

OUTPUT POWER (dB)

Figure 5. VCO Phase Noise, 2600 MHz, 200 kHz PFD, 10 kHz Loop Bandwidth

04644-006

–145

–150

–140

–135

–130

–125

–120

–115

–110

–105

–90

–95

–100

–85

–80

–75

–70

100 10M1M100k10k1000 FREQUENCY OFFSET (Hz)

OUTPUT POWER (dB)

Figure 6. VCO Phase Noise, 1300 MHz,

Divide-by-2 Enabled, 200 kHz PFD, 10 kHz Loop Bandwidth

04644-007

OUTPUT POWER (dB)

–90

–80

–70

–60

–50

–40

–30

–20

–10

–2kHz –1kHz 2600MHz 1kHz 2kHz

–80.4dBc/Hz

= 3.3V, V

VCO

= 3.3V

= 2.5mA

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 10kHz

RES. BANDWIDTH = 30Hz

VIDEO BANDWIDTH = 30Hz

SWEEP = 1.9 SECONDS

AVERAGES = 20

REFERENCE

LEVEL = –3.5dBm

Figure 7. Close-In Phase Noise at 2600 MHz (200 kHz Channel Spacing)

04644-008

OUTPUT POWER (dB)

–90

–80

–70

–60

–50

–40

–30

–20

–10

–0.25MHz –0.1MHz 2600MHz 0.1MHz 0.25MHz

–77dBc

REFERENCE

LEVEL = –6dBm

= 3.3V, V

VCO

= 3.3V

= 2.5mA

PFD FREQUENCY = 200kHz

LOOP BANDWIDTH = 10kHz

RES. BANDWIDTH = 1kHz

VIDEO BANDWIDTH = 1kHz

AVERAGES = 20

Figure 8. Reference Spurs at 2600 MHz

(200 kHz Channel Spacing, 10 kHz Loop Bandwidth)

04644-009

OUTPUT POWER (dB)

–90

–80

–70

–60

–50

–40

–30

–20

–10

–1MHz –0.5MHz 2250MHz 0.5MHz 1MHz

–86dBc/Hz

= 3V, V

VCO

= 3V

= 2.5mA

PFD FREQUENCY = 1MHz

LOOP BANDWIDTH = 25kHz

RES. BANDWIDTH = 10kHz

VIDEO BANDWIDTH = 10kHz

SWEEP = 1.9 SECONDS

AVERAGES = 10

Figure 9. Reference Spurs at 2600 MHz

(1 MHz Channel Spacing, 25 kHz Loop Bandwidth)

Data Sheet ADF4360-0

Rev. B | Page 9 of 24

CIRCUIT DESCRIPTION

REFERENCE INPUT SECTION

The reference input stage is shown in Figure 10. SW1 and SW2

are normally closed switches. SW3 is normally open. When

power-down is initiated, SW3 is closed, and SW1 and SW2 are

opened. This ensures that there is no loading of the REFIN pin

on power-down.

04644-010

BUFFER TO R COUNTER

REF

100kΩ

SW2

SW3

SW1

POWER-DOWN

CONTROL

Figure 10. Reference Input Stage

PRESCALER (P/P + 1)

The dual-modulus prescaler (P/P + 1), along with the A and B

counters, enables the large division ratio, N, to be realized

(N = BP + A). The dual-modulus prescaler, operating at CML

levels, takes the clock from the VCO and divides it down to a

manageable frequency for the CMOS A and B counters. The

prescaler is programmable. It can be set in software to 8/9,

16/17, or 32/33 and is based on a synchronous 4/5 core. There is

a minimum divide ratio possible for fully contiguous output

frequencies; this minimum is determined by P, the prescaler

value, and is given by (P2 − P).

A AND B COUNTERS

The A and B CMOS counters combine with the dual-modulus

prescaler to allow a wide range division ratio in the PLL

feedback counter. The counters are specified to work when the

prescaler output is 300 MHz or less. Thus, with a VCO

frequency of 2.5 GHz, a prescaler value of 16/17 is valid, but a

value of 8/9 is not valid.

Pulse Swallow Function

The A and B counters, in conjunction with the dual-modulus

prescaler, make it possible to generate output frequencies that

are spaced only by the reference frequency divided by R. The

VCO frequency equation is

()

RfABPf REFIN

VCO /×]+×[=

where:

fVCO is the output frequency of the VCO.

P is the preset modulus of the dual-modulus prescaler (8/9,

16/17, and so on).

B is the preset divide ratio of the binary 13-bit counter (3 to 8191).

A is the preset divide ratio of the binary 5-bit swallow counter (0 to 31).

fREFIN is the external reference frequency oscillator.

N = BP + A

TO PFD

FROM VCO

N DIVIDER

MODULUS

CONTROL

LOAD

13-BIT B

COUNTER

5-BIT A

COUNTER

PRESCALER

P/P+1

04644-011

Figure 11. A and B Counters

R COUNTER

The 14-bit R counter allows the input reference frequency to

be divided down to produce the reference clock to the phase

frequency detector (PFD). Division ratios from 1 to 16,383 are

allowed.

PFD AND CHARGE PUMP

The PFD takes inputs from the R counter and N counter

(N = BP + A) and produces an output proportional to the phase

and frequency difference between them. Figure 12 is a

simplified schematic. The PFD includes a programmable delay

element that controls the width of the antibacklash pulse. This

pulse ensures that there is no dead zone in the PFD transfer

function and minimizes phase noise and reference spurs. Two

bits in the R counter latch, ABP2 and ABP1, control the width

of the pulse (see Table 9).

04644-012

PROGRAMMABLE

DELAY U3

CLR2 Q2D2

CLR1

Q1D1

CHARGE

PUMP

DOWN

ABP1 ABP2

R DIVIDER

N DIVIDER

P OUTPUT

R DIVIDER

N DIVIDER

CPGND

Figure 12. PFD Simplified Schematic and Timing (In Lock)

ADF4360-0 Data Sheet

Rev. B | Page 10 of 24

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF4360 family allows the user

to access various internal points on the chip. The state of

MUXOUT is controlled by M3, M2, and M1 in the function

latch. The full truth table is shown in Table 7. Figure 13 shows

the MUXOUT section in block diagram form.

Lock Detect

MUXOUT can be programmed for two types of lock detect:

digital and analog. Digital lock detect is active high. When LDP

in the R counter latch is set to 0, digital lock detect is set high

when the phase error on three consecutive phase detector cycles

is less than 15 ns.

With LDP set to 1, five consecutive cycles of less than 15 ns

phase error are required to set the lock detect. It stays set high

until a phase error of greater than 25 ns is detected on any

subsequent PD cycle.

The N-channel open-drain analog lock detect should be

operated with an external pull-up resistor of 10 kΩ nominal.

When a lock has been detected, this output is high with narrow

low-going pulses.

R COUNTER OUTPUT

N COUNTER OUTPUT

DIGITAL LOCK DETECT

DGND

CONTROLMUX MUXOUT

DVDD

ANALOG LOCK DETECT

SDOUT

04644-013

Figure 13. MUXOUT Circuit

INPUT SHIFT REGISTER

The ADF4360 family’s digital section includes a 24-bit input

shift register, a 14-bit R counter, and an 18-bit N counter,

comprised of a 5-bit A counter and a 13-bit B counter. Data is

clocked into the 24-bit shift register on each rising edge of CLK.

The data is clocked in MSB first. Data is transferred from the

shift register to one of four latches on the rising edge of LE. The

destination latch is determined by the state of the two control

bits (C2, C1) in the shift register. These are the two LSBs, DB1

and DB0, as shown in Figure 2.

The truth table for these bits is shown in Table 5. Table 6 shows

a summary of how the latches are programmed. Note that the

test mode latch is used for factory testing and should not be

programmed by the user.

Table 5. C2 and C1 Truth Table

Control Bits

C2 C1

Data Latch

0 0 Control Latch

0 1 R Counter

1 0 N Counter (A and B)

1 1 Test Mode Latch

VCO

The VCO core in the ADF4360 family uses eight overlapping

bands, as shown in Figure 14, to allow a wide frequency range

to be covered without a large VCO sensitivity (KV) and resultant

poor phase noise and spurious performance.

The correct band is chosen automatically by the band select

logic at power-up or whenever the N counter latch is updated. It

is important that the correct write sequence be followed at

power-up. This sequence is

1. R counter latch

2. Control latch

3. N counter latch

During band select, which takes five PFD cycles, the VCO VTUNE

is disconnected from the output of the loop filter and connected

to an internal reference voltage.

04644-014

0.5

0.7

0.9

1.1

1.3

1.5

1.9

2.1

2.3

1.7

2.5

VOLTAGE (V)

FREQUENCY (MHz)

2200 2400 2600 2800 3000

Figure 14. Frequency vs. VTUNE, ADF4360-0

The R counter output is used as the clock for the band select logic

and should not exceed 1 MHz. A programmable divider is

provided at the R counter input to allow division by 1, 2, 4, or 8 and

is controlled by Bits BSC1 and BSC2 in the R counter latch. Where

the required PFD frequency exceeds 1 MHz, the divide ratio should

be set to allow enough time for correct band selection.

After band select, normal PLL action resumes. The nominal

value of KV is 56 MHz/V or 28 MHz/V, if divide-by-2 operation

has been selected (by programming DIV2 [DB22] high in the N

counter latch). The ADF4360 family contains linearization

circuitry to minimize any variation of the product of ICP and KV.

Data Sheet ADF4360-0

Rev. B | Page 11 of 24

The operating current in the VCO core is programmable in four

steps: 5 mA, 10 mA, 15 mA, and 20 mA. This is controlled by

Bits PC1 and PC2 in the control latch.

If the outputs are used individually, the optimum output stage

consists of a shunt inductor to VDD.

Another feature of the ADF4360 family is that the supply current

to the RF output stage is shut down until the part achieves lock as

measured by the digital lock detect circuitry. This is enabled by the

mute-till-lock detect (MTLD) bit in the control latch.

OUTPUT STAGE

The RFOUTA and RFOUTB pins of the ADF4360 family are

connected to the collectors of an NPN differential pair driven

by buffered outputs of the VCO, as shown in Figure 15. To allow

the user to optimize the power dissipation vs. the output power

requirements, the tail current of the differential pair is

programmable via Bits PL1 and PL2 in the control latch. Four

current levels may be set: +3.5 mA, +5 mA, +7.5 mA, and

+11 mA. These levels give output power levels of −13 dBm,

−11 dBm, −8.5 dBm, and −6.5 dBm, respectively, using a 50 Ω

resistor to VDD and ac coupling into a 50 Ω load. Alternatively,

both outputs can be combined in a 1 + 1:1 transformer or a 180°

microstrip coupler (see the Output Matching section).

VCO

OUT

ARF

OUT

BUFFER/

DIVIDE BY 2

04644-015

Figure 15. Output Stage ADF4360-0

ADF4360-0 Data Sheet

Rev. B | Page 12 of 24

LATCH STRUCTURE

Table 6 shows the three on-chip latches for the ADF4360 family. The two LSBs determine which latch is programmed.

Table 6. Latch Structure

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C2 (0) C1 (0)

PC1PC2CRM1M2PDPCPCPGMTLDPL1PL2CPI1CPI2CPI3CPI4CPI5CPI6PD1 M3

CONTROL

BITS

MUXOUT

CONTROL

CURRENT

SETTING 2 CURRENT

SETTING 1

PRESCALER

VALUE

CORE

POWER

LEVEL

OUTPUT

POWER

LEVEL

DB21DB22DB23

POWER-

DOWN 2

POWER-

DOWN 1

COUNTER

RESET

MUTE-TILL-

CP GAIN

THREE-

STATE

PHASE

DETECTOR

POLARITY

PD2P1P2

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C2 (0) C1 (1)

R1R2R3R4R5R7R8R9R10R11R12R13R14ABP1ABP2LDPTMBBSC1 R6

CONTROL

BITS

BAND

SELECT

CLOCK

ANTI-

BACKLASH

PULSE

WIDTH

14-BIT REFERENCE COUNTER

DB21DB22DB23

LOCK

DETECT

PRECISION

TEST

MODE

BIT

RESERVED

DIVIDE-

BY-2

DIVIDE-BY-

2 SELECT

BSC2RSVRSV

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C2 (1) C1 (0)

A1A2A3A4A5B1B2B3B4B5B6B7B8B9B10B11B12B13 RSV

CONTROL

BITS

5-BIT A COUNTER

13-BIT B COUNTER

CONTROL LATCH

N COUNTER LATCH

R COUNTER LATCH

DB21DB22DB23

CP GAIN

RESERVED

CPGDIV2DIVSEL

04644-016

Data Sheet ADF4360-0

Rev. B | Page 13 of 24

Table 7. Control Latch

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C2 (0) C1 (0)

PC1PC2CRM1M2PDPCPCPGMTLDPL1PL2CPI1CPI2CPI3CPI4CPI5CPI6PD1 M3

CONTROL

BITS

MUXOUT

CONTROL

CURRENT

SETTING 2 CURRENT

SETTING 1

PRESCALER

VALUE

CORE

POWER

LEVEL

OUTPUT

POWER

LEVEL

DB21DB22DB23

POWER-

DOWN 2

POWER-

DOWN 1

COUNTER

RESET

MUTE-TILL-

CP GAIN

THREE-

STATE

PHASE

DETECTOR

POLARITY

PD2P1P2

COUNTER

OPERATION

NORMAL

R, A, B COUNTERS

HELD IN RESET

PC2

CORE POWER LEVEL

5mA

10mA

15mA

PC1

1120mA

CHARGE PUMP

OUTPUT

NORMAL

THREE-STATE

PDP

PHASE DETECTOR

POLARITY

NEGATIVE

POSITIVE

CPG

CP GAIN

CURRENT SETTING 1

CURRENT SETTING 2

MTLD

MUTE-TILL-LOCK DETECT

DISABLED

ENABLED

M3 M2 M1 OUTPUT

THREE-STATE OUTPUT000

001

010

011

100

101

110

111

DIGITAL LOCK DETECT

(ACTIVE HIGH)

N DIVIDER OUTPUT

R DIVIDER OUTPUT

N-CHANNEL OPEN-DRAIN

LOCK DETECT

SERIAL DATA OUTPUT

DGND

P2 P1 PRESCALER VALUE

0 0 8/9

0 1 16/17

1 0 32/33

1 1 32/33

CE PIN PD2 PD1 MODE

0 X X ASYNCHRONOUS POWER-DOWN

1 X 0 NORMAL OPERATION

1 0 1 ASYNCHRONOUS POWER-DOWN

1 1 1 SYNCHRONOUS POWER-DOWN

CPI6 CPI5 CPI4 I

(mA)

CPI3 CPI2 CPI1 4.7kΩ

0.31

0.62

0.93

1.25

1.56

1.87

2.18

2.50

PL2 PL1 OUTPUT POWER LEVEL

CURRENT POWER INTO 50Ω(USING 50Ω TO V

VCC

)

–13dBm

–11dBm

–8dBm

–6dBm

3.5mA

5.0mA

7.5mA

11.0mA

04644-017

ADF4360-0 Data Sheet

Rev. B | Page 14 of 24

Table 8. N Counter Latch

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C2 (1) C1 (0)

A1A2A3A4A5B1B2B3B4B5B6B7B8B9B10B11B12B13 RSV

CONTROL

BITS

5-BIT A COUNTER

13-BIT B COUNTER

DB21DB22DB23

CP GAIN

DIVIDE-BY-

2 SELECT

DIVIDE-

BY-2

RESERVED

CPGDIV2

DIVSEL

THIS BIT IS NOT USED

BY THE DEVICE AND

IS A DON'T CARE BIT.

A5 A4 .......... A2 A1 A COUNTER

DIVIDE RATIO

0 0 .......... 0 0 0

0 0 .......... 0 1 1

0 0 .......... 1 0 2

0 0 .......... 1 1 3

. . .......... . . .

1 1 .......... 0 0 28

1 1 .......... 0 1 29

1 1 .......... 1 0 30

1 1 .......... 1 1 31

F4 (FUNCTION LATCH)

FASTLOCK ENABLE CP GAIN OPERATION

CHARGE PUMP CURRENT SETTING 1

IS PERMANENTLY USED

CHARGE PUMP CURRENT SETTING 2

IS PERMANENTLY USED

N = BP + A; P IS PRESCALER VALUE SET IN THE CONTROL LATCH.

B MUST BE GREATER THAN OR EQUAL TO A. FOR CONTINUOUSLY

ADJACENT VALUES OF (N

REF

), AT THE OUTPUT, N

MIN

IS (P

–P).

B13 B12 B11 B3 B2 B1 B COUNTER DIVIDE RATIO

.......... 0000

000

0 0 NOT ALLOWED

.......... 0 0 1 NOT ALLOWED

.......... 0 1 0 NOT ALLOWED

.......... 1 1 1 3

.......... ... .

.. .

.......... . . . .

.......... 1111

111

0 0 8188

.......... 1 0 1 8189

.......... 1 1 0 8190

.......... 1 1 1 8191

04644-018

DIV2

DIVIDE-BY-2

FUNDAMENTAL OUTPUT

DIVIDE-BY-2

DIVSEL

DIVIDE-BY-2 SELECT (PRESCALER INPUT)

FUNDAMENTAL OUTPUT SELECTED

DIVIDE-BY-2 SELECTED

Data Sheet ADF4360-0

Rev. B | Page 15 of 24

Table 9. R Counter Latch

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C2 (0) C1 (1)R1R2R3R4R5R7R8R9R10R11R12R13R14ABP1ABP2LDPTMBBSC1 R6

CONTROL

BITS

BAND

SELECT

CLOCK

ANTI-

BACKLASH

PULSE

WIDTH

14-BIT REFERENCE COUNTER

DB21DB22DB23

LOCK

DETECT

PRECISION

TEST

MODE

BIT

RESERVED

BSC2RSVRSV

TEST MODE

BIT SHOULD

BE SET TO 0

FOR NORMAL

OPERATION.

R14 R13 R12 R3 R2 R1 DIVIDE RATIO

.......... 0000

000

00 1

.......... 0 1 1 2

.......... 0 1 0 3

.......... 1 0 1 4

.......... ....

...

.. .

.......... . . . .

.......... 1111

111

0 0 16380

.......... 1 0 1 16381

.......... 1 1 0 16382

.......... 1 1 1 16383

THESE BITS ARE NOT

USED BY THE DEVICE

AND ARE DON'T CARE

BITS.

04644-019

LDP LOCK DETECT PRECISION

0 THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN

15ns MUST OCCUR BEFORE LOCK DETECT IS SET.

1 FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN

15ns MUST OCCUR BEFORE LOCK DETECT IS SET.

ABP2 ABP1 ANTIBACKLASH PULSE WIDTH

0 0 3.0ns

0 1 1.3ns

1 0 6.0ns

1 1 3.0ns

BSC2 BSC1 BAND SELECT CLOCK DIVIDER

001

012

104

118

ADF4360-0 Data Sheet

Rev. B | Page 16 of 24

POWER-UP

Power-Up Sequence

The correct programming sequence for the ADF4360-0 after

power-up is:

1. R counter latch

2. Control latch

3. N counter latch

Initial Power-Up

Initial power-up refers to programming the part after the

application of voltage to the AVDD, DVDD, VVCO, and CE pins. On

initial power-up, an interval is required between programming

the control latch and programming the N counter latch.

This interval is necessary to allow the transient behavior of the

ADF4360-0 during initial power-up to have settled. During

initial power-up, a write to the control latch powers up the part

and the bias currents of the VCO begin to settle. If these

currents have not settled to within 10% of their steady-state

value and if the N counter latch is then programmed, the VCO

may not be able to oscillate at the desired frequency, which does

not allow the band select logic to choose the correct frequency

band and the ADF4360-0 may not achieve lock. If the

recommended interval is inserted and the N counter latch is

programmed, the band select logic can choose the correct

frequency band and the part locks to the correct frequency.

This duration of this interval is affected by the value of the

capacitor on the CN pin (Pin 14). This capacitor is used to

reduce the close-in noise of the ADF4360-0 VCO. The

recommended value of this capacitor is 10 μF. Using this value

requires an interval of ≥ 5 ms between the latching in of the

control latch bits and latching in of the N counter latch bits. If a

shorter delay is required, this capacitor can be reduced. A slight

phase noise penalty is incurred by this change, which is

explained further in Table 10.

Table 10. CN Capacitance vs. Interval and Phase Noise

CN value Recommended Interval between Control Latch and N Counter Latch Open Loop Phase Noise @ 10 kHz Offset

10 μF ≥ 5 ms −84 dBc

440 nF ≥ 600 μs −82 dBc

CLOCK

POWER-UP

DATA

R COUNTER

LATCH DATA CONTROL

LATCH DATA N COUNTER

LATCH DATA

REQUIRED INTERVAL

CONTROL LATCH WRITE TO

N COUNTER LATCH WRITE

04644-020

Figure 16. ADF4360-0 Power-Up Timing

Data Sheet ADF4360-0

Rev. B | Page 17 of 24

Hardware Power-Up/Power-Down

If the ADF4360-0 is powered down via the hardware (using the

CE pin) and powered up again without any change to the N

counter register during power-down, it locks at the correct

frequency because the part is already in the correct frequency

band. The lock time depends on the value of capacitance on the

CN pin, which is <5 ms for 10 μF capacitance. The smaller

capacitance of 440 nF on this pin enables lock times of <600 μs.

The N counter value cannot be changed while it is in power-

down because the part may not lock to the correct frequency on

power-up. If it is updated, the correct programming sequence

for it after power-up is to the R counter latch, followed by the

control latch, and finally the N counter latch, with the required

interval between the control latch and N counter latch, as

described in the Initial Power-Up section.

Software Power-Up/Power-Down

If the ADF4360-0 is powered down via the software (using the

control latch) and powered up again without any change to the

N counter latch during power-down, it locks at the correct

frequency because it is already in the correct frequency band.

The lock time depends on the value of capacitance on the CN

pin, which is <5 ms for 10 μF capacitance. The smaller

capacitance of 440 nF on this pin enables lock times of <600 μs.

The N counter value cannot be changed while it is in power-

down because the part may not lock to the correct frequency on

power-up. If it is updated, the correct programming sequence

for it after power-up is to the R counter latch, followed by the

control latch, and finally the N counter latch, with the required

interval between the control latch and N counter latch, as

described in the Initial Power-Up section.

ADF4360-0 Data Sheet

Rev. B | Page 18 of 24

CONTROL LATCH

With (C2, C1) = (0, 0), the control latch is programmed. Table 7

shows the input data format for programming the control latch.

Prescaler Value

In the ADF4360 family, P2 and P1 in the control latch set the

prescaler values.

Power-Down

DB21 (PD2) and DB20 (PD1) provide programmable power-

down modes.

In the programmed asynchronous power-down, the device

powers down immediately after latching a 1 into Bit PD1, with

the condition that PD2 has been loaded with a 0. In the

programmed synchronous power-down, the device power-

down is gated by the charge pump to prevent unwanted

frequency jumps. Once the power-down is enabled by writing a

1 into

Bit PD1 (on the condition that a 1 has also been loaded to PD2),

the device goes into power-down on the second rising edge of

the R counter output, after LE goes high. When the CE pin is

low, the device is immediately disabled regardless of the state of

PD1 or PD2.

When a power-down is activated (either synchronous or

asynchronous mode), the following events occur:

• All active dc current paths are removed.

• The R, N, and timeout counters are forced to their load

state conditions.

• The charge pump is forced into three-state mode.

• The digital lock detect circuitry is reset.

• The RF outputs are debiased to a high impedance state.

• The reference input buffer circuitry is disabled.

• The input register remains active and capable of loading and

latching data.

Charge Pump Currents

CPI3, CPI2, and CPI1 in the ADF4360 family determine

Current Setting 1.

CPI6, CPI5, and CPI4 determine Current Setting 2. See the

truth table in Table 7.

Output Power Level

Bits PL1 and PL2 set the output power level of the VCO. See the

truth table in Table 7.

Mute-Till-Lock Detect

DB11 of the control latch in the ADF4360 family is the mute-till-

lock detect bit. This function, when enabled, ensures that the RF

outputs are not switched on until the PLL is locked.

CP Gain

DB10 of the control latch in the ADF4360 family is the charge

pump gain bit. When it is programmed to a 1, Current Setting 2

is used. When it is programmed to a 0, Current Setting 1 is

used.

Charge Pump Three-State

This bit puts the charge pump into three-state mode when

programmed to a 1. It should be set to 0 for normal operation.

Phase Detector Polarity

The PDP bit in the ADF4360 family sets the phase detector

polarity. The positive setting enabled by programming a 1 is

used when using the on-chip VCO with a passive loop filter or

with an active non-inverting filter. It can also be set to 0. This is

required, if an active inverting loop filter is used.

MUXOUT Control

The on-chip multiplexer is controlled by M3, M2, and M1. See

the truth table in Table 7.

Counter Reset

DB4 is the counter reset bit for the ADF4360 family. When this

is 1, the R counter and the A, B counters are reset. For normal

operation, this bit should be 0.

Core Power Level

PC1 and PC2 set the power level in the VCO core. The

recommended setting is 10 mA. See the truth table in Table 7.

Data Sheet ADF4360-0

Rev. B | Page 19 of 24

N COUNTER LATCH

With (C2, C1) = (1, 0), the N counter latch is programmed.

Table 8 shows the input data format for programming the

N counter latch.

A Counter Latch

A5 to A1 program the 5-bit A counter. The divide range is 0

(00000) to 31 (11111).

Reserved Bits

DB7 is a spare bit that is reserved. It should be programmed to 0.

B Counter Latch

B13 to B1 program the B counter. The divide range is 3

(00.....0011) to 8191 (11....111).

Overall Divide Range

The overall divide range is defined by ((P × B) + A), where P is

the prescaler value.

CP Gain

DB21 of the N counter latch in the ADF4360 family is the

charge pump gain bit. When this is programmed to 1, Current

Setting 2 is used. When programmed to 0, Current Setting 1 is

used. This bit can also be programmed through DB10 of the con-

trol latch. The bit always reflects the latest value written to it,

whether this is through the control latch or the N counter latch.

Divide-by-2

DB22 is the divide-by-2 bit. When set to 1, the output divide-by-2

function is chosen. When it is set to 0, normal operation occurs.

Divide-by-2 Select

DB23 is the divide-by-2 select bit. When programmed to 1, the

divide-by-2 output is selected as the prescaler input. When set

to 0, the fundamental is used as the prescaler input. For exam-

ple, using the output divide-by-2 feature and a PFD frequency

of 200 kHz, the user needs a value of N = 13,000 to generate

1,500 MHz. With the divide-by-2 select bit high, the user may

keep N = 6,500.

R COUNTER LATCH

With (C2, C1) = (0, 1), the R counter latch is programmed.

Table 9 shows the input data format for programming the

R counter latch.

R Counter

R1 to R14 set the counter divide ratio. The divide range is 1

(00......001) to 16383 (111......111).

Antibacklash Pulse Width

DB16 and DB17 set the antibacklash pulse width.

Lock Detect Precision

DB18 is the lock detect precision bit. This bit sets the number of

reference cycles with less than 15 ns phase error for entering the

locked state. With LDP at 1, five cycles are taken; with LDP at 0,

three cycles are taken.

Test Mode Bit

DB19 is the test mode bit (TMB) and should be set to 0. With

TMB = 0, the contents of the test mode latch are ignored and

normal operation occurs as determined by the contents of the

control latch, R counter latch, and N counter latch. Note that

test modes are for factory testing only and should not be pro-

grammed by the user.

Band Select Clock

These bits set a divider for the band select logic clock input. The

output of the R counter is by default the value used to clock the

band select logic, but, if this value is too high (>1 MHz), a

divider can be switched on to divide the R counter output to a

smaller value (see Table 9).

Reserved Bits

DB23 to DB22 are spare bits that are reserved. They should be

programmed to 0.

ADF4360-0 Data Sheet

Rev. B | Page 20 of 24

APPLICATIONS

FIXED FREQUENCY LO

Figure 17 shows the ADF4360-0 used as a fixed frequency LO at 2.6

GHz. The low-pass filter was designed using ADIsimPLL for a

channel spacing of 8 MHz and an open-loop bandwidth of 40 kHz.

The maximum PFD frequency of the ADF4360-0 is 8 MHz.

Because using a larger PFD frequency allows users to use a smaller

N, the in-band phase noise is reduced to as low as possible,

–100 dBc/Hz. The 40 kHz bandwidth is chosen to be just greater

than the point at which the open-loop phase noise of the VCO is

–100 dBc/Hz, thus giving the best possible integrated noise. The

typical rms phase noise (100 Hz to 100 kHz) of the LO in this

configuration is 0.35°. The reference frequency is from a 16 MHz

TCXO from Fox; thus, an R value of 2 is programmed. Taking into

account the high PFD frequency and its effect on the band select

logic, the band select clock divider is enabled. In this case, a value of

8 is chosen. A very simple pull-up resistor and dc blocking

capacitor complete the RF output stage.

SPI COMPATIBLE SERIAL BUS

ADF4360-0

VCO

FOX

801BE-160

16MHz

VCO

CPGND AGND DGND RF

OUT

1nF

560pF 270pF

8.2nF

51Ω

100pF

1nF1nF

10μF

4.7kΩ

1.5kΩ

3kΩ

SET

DATA

CLK

REF

TUNE

CE MUXOUT

2023221

VDD

LOCK

DETECT

04644-021

3 8 9 10 11 22 15

Figure 17. Fixed Frequency LO

INTERFACING

The ADF4360 family has a simple SPI®-compatible serial

interface for writing to the device. CLK, DATA, and LE control

the data transfer. When LE goes high, the 24 bits that have been

clocked into the appropriate register on each rising edge of CLK

are transferred to the appropriate latch. See Figure 2 for the

timing diagram and Table 5 for the latch truth table.

The maximum allowable serial clock rate is 20 MHz. This

means that the maximum update rate possible is 833 kHz or

one update every 1.2 μs. This is more than adequate for systems

that have typical lock times in hundreds of microseconds.

ADuC812 Interface

Figure 18 shows the interface between the ADF4360 family and

the ADuC812 MicroConverter®. Because the ADuC812 is based

on an 8051 core, this interface can be used with any 8051 based

microcontroller. The MicroConverter is set up for SPI master

mode with CPHA = 0. To initiate the operation, the I/O port

driving LE is brought low. Each latch of the ADF4360 family

needs a 24-bit word, which is accomplished by writing three 8-

bit bytes from the MicroConverter to the device. When the

third byte has been written, the LE input should be brought

high to complete the transfer.

04644-022

ADuC812

ADF4360-x

SCLK

SDATA

MUXOUT

(LOCK DETECT)

SCLOCK

MOSI

I/O PORTS

Figure 18. ADuC812 to ADF4360-x Interface

I/O port lines on the ADuC812 are also used to control power-

down (CE input) and detect lock (MUXOUT configured as lock

detect and polled by the port input). When operating in the

described mode, the maximum SCLOCK rate of the ADuC812

is 4 MHz. This means that the maximum rate at which the

output frequency can be changed is 166 kHz.

ADSP-21xx Interface

Figure 19 shows the interface between the ADF4360 family and

the ADSP-21xx digital signal processor. The ADF4360 family

needs a 24-bit serial word for each latch write. The easiest way

to accomplish this using the ADSP-21xx family is to use the

autobuffered transmit mode of operation with alternate

framing. This provides a means for transmitting an entire block

of serial data before an interrupt is generated.

04644-023

ADSP-21xx

ADF4360-x

SCLK

SDATA

MUXOUT

(LOCK DETECT)

SCLOCK

MOSI

TFS

I/O PORTS

Figure 19. ADSP-21xx to ADF4360-x Interface

Set up the word length for 8 bits and use three memory

locations for each 24-bit word. To program each 24-bit latch,

store the 8-bit bytes, enable the autobuffered mode, and write to

the transmit register of the DSP. This last operation initiates the

autobuffer transfer.

Data Sheet ADF4360-0

Rev. B | Page 21 of 24

PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE

The leads on the chip scale package (CP-24) are rectangular.

The printed circuit board pad for these should be 0.1 mm

longer than the package lead length and 0.05 mm wider than

the package lead width. The lead should be centered on the pad

to ensure that the solder joint size is maximized.

The bottom of the chip scale package has a central thermal pad.

The thermal pad on the printed circuit board should be at least

as large as this exposed pad. On the printed circuit board, there

should be a clearance of at least 0.25 mm between the thermal

pad and the inner edges of the pad pattern to ensure that

shorting is avoided.

Thermal vias may be used on the printed circuit board thermal

pad to improve thermal performance of the package. If vias are

used, they should be incorporated in the thermal pad at a

1.2 mm pitch grid. The via diameter should be between 0.3 mm

and 0.33 mm, and the via barrel should be plated with 1 ounce

of copper to plug the via.

The user should connect the printed circuit thermal pad to

AGND. This is internally connected to AGND.

OUTPUT MATCHING

There are a number of ways to match the output of the

ADF4360-0 for optimum operation; the most basic is to use a

50 Ω resistor to VVCO. A dc bypass capacitor of 100 pF is

connected in series, as shown in Figure 20. Because the resistor

is not frequency dependent, this provides a good broadband

match. The output power in this circuit typically gives −6.5

dBm output power into a 50 Ω load.

100pF

04644-024

OUT

VCO

50Ω

51Ω

Figure 20. Simple ADF4360-1 Output Stage

A better solution is to use a shunt inductor (acting as an RF

choke) to VVCO. This gives a better match than a resistor and,

therefore, more output power. Additionally, a series inductor is

added after the dc bypass capacitor to provide a resonant LC

circuit. This tunes the oscillator output and provides

approximately 10 dB additional rejection of the second

harmonic. The shunt inductor needs to be a relatively low value

(<10 nH).

Experiments have shown that the circuit shown in Figure 21

provides an excellent match to 50 Ω over the operating range of

the ADF4360-0. This gives approximately −4 dBm output power

across the frequency range of the ADF4360-0. Both single-ended

architectures can be examined using the EV-ADF4360-0EB1

evaluation board.

3.9nH

47nH

1.5pF

04644-025

OUT

VCO

50Ω

Figure 21. Differential ADF4360-0 Output Stage

If the user does not need the differential outputs available on

the ADF4360-0, the user may either terminate the unused

output or combine both outputs using a balun. The circuit in

Figure 22 shows how best to combine the outputs.

1nH 3.6nH 47nH

3.6nH

1.5pF 10pF

1.5pF

50Ω

1nH

OUT

VCO

OUT

04644-026

Figure 22. Balun for Combining ADF4360-0 RF Outputs

The circuit in Figure 22 is a lumped-lattice-type LC balun. It is

designed for a center frequency of 2.6 GHz and outputs −1 dBm

at this frequency. The series 1 nH inductor is used to tune out

any parasitic capacitance due to the board layout from each

input, and the remainder of the circuit is used to shift the

output of one RF input by +90° and the second by −90°, thus

combining the two. The action of the 3.6 nH inductor and the

1.5 pF capacitor accomplishes this. The 12 nH is used to

provide an RF choke to feed the supply voltage, and the 10 pF

capacitor provides the necessary dc block. To ensure good RF

performance, the circuits in Figure 20 and Figure 22 are

implemented with Coilcraft 0402/0603 inductors and AVX 0402

thin-film capacitors.

Alternatively, instead of the LC balun shown in Figure 22, both

outputs may be combined using a 180° rat-race coupler.

ADF4360-0 Data Sheet

Rev. B | Page 22 of 24

OUTLINE DIMENSIONS

COMPLIANT

JEDEC STANDARDS MO-220-VGGD-2

08-18-2010-A

0.50

BSC

PIN1

INDICATOR

2.50 BCS

0.50

0.40

0.30

TOP VIEW

12° MAX 0.70 MAX

0.65 TYP

SEATING

PLANE

COPLANARITY

0.08

1.00

0.85

0.80

0.30

0.23

0.18

0.05 MAX

0.02 NOM

0.20 REF

0.20 MIN

2.45

2.30 SQ

2.15

(BOTTOM VIEW)

0.60 MAX

PIN 1

INDICATOR

4.10

4.00 SQ

3.90

3.75 BSC

EXPOSED

PAD

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

Figure 23. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm × 4 mm Body, Very Thin Quad

(CP-24-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Frequency Range Package Description Package Option

ADF4360-0BCPZ −40°C to +85°C 2400 MHz to 2725 MHz 24-Lead LFCSP_VQ CP-24-2

ADF4360-0BCPZRL −40°C to +85°C 2400 MHz to 2725 MHz 24-Lead LFCSP_VQ CP-24-2

ADF4360-0BCPZRL7 −40°C to +85°C 2400 MHz to 2725 MHz 24-Lead LFCSP_VQ CP-24-2

EV-ADF4360-0EB1Z Evaluation Board

1 Z = RoHS Compliant Part.

Data Sheet ADF4360-0

Rev. B | Page 23 of 24

NOTES

ADF4360-0 Data Sheet

Rev. B | Page 24 of 24

NOTES

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

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D04644-0-2/12(B)