SLCS115E − DECEMBER 1986 − REVISED JULY 2003
1
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
DVery Low Power ...110 µW Typ at 5 V
DFast Response Time ...t
PLH = 2.5 µs Typ
With 5-mV Overdrive
DSingle Supply Operation:
TLC393C ...3 V to 16 V
TLC393I ...3 V to 16 V
TLC393Q ...4 V to 16 V
TLC393M ...4 V to 16 V
TLC193M ...4 V to 16 V
DOn-Chip ESD Protection
description
The TLC193 and TLC393 consist of dual
independent micropower voltage comparators
designed to operate from a single supply. They
are functionally similar to the LM393 but uses
one-twentieth the power for similar response
times. The open-drain MOS output stage
interfaces to a variety of loads and supplies. For
a similar device with a push-pull output
configuration (see the TLC3702 data sheet).
Texas Instruments LinCMOS process offers
superior analog performance to standard CMOS
processes. Along with the standard CMOS
advantages of low power without sacrificing
speed, high input impedance, and low bias
currents, the LinCMOS process offers ex-
tremely stable input offset voltages, even with
differential input stresses of several volts. This
characteristic makes it possible to build reliable
CMOS comparators.
The TLC393C is characterized for operation over the commercial temperature range of TA = 0°C to 70°C. The
TLC393I is characterized for operation over the extended industrial temperature range of TA = −40°C to 85°C.
The TLC393Q is characterized for operation over the full automotive temperature range of TA = −40°C to 125°C.
The TLC193M and TLC393M are characterized for operation over the full military temperature range of
TA = −55°C to 125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1986-2003, Texas Instruments Incorporated
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
NC
2OUT
NC
2IN−
NC
NC
1IN−
NC
1IN+
NC
NC
1OUT
NC
2IN+
NC V
NC
GND
NC
NC
DD
D, JG, P, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
1OUT
1IN−
1IN+
GND
VDD
2OUT
2IN−
2IN+
NC − No internal connection
OUT
symbol (each comparator)
IN+
IN−
FK PACKAGE
(TOP VIEW)
LinCMOS is a trademark of Texas Instruments Incorporated. All other trademarks are the property of their respective owners.
SLCS115D − DECEMBER 1986 − REVISED JULY 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
AVAILABLE OPTIONS
V max
PACKAGES
TAVIOmax
at 25°CSMALL OUTLINE
(D) CHIP CARRIER
(FK) CERAMIC DIP
(JG) PLASTIC DIP
(P) TSSOP
(PW)
0°C to 70°C5 mV TLC393CD — — TLC393CP TLC393CPWLE
−40°C to 85°C5 mV TLC393ID — — TLC393IP TLC393IPWLE
−40°C to 125°C5 mV TLC393QD — — — —
−55°C to 125°C5 mV TLC393MD TLC193MFK TLC193MJG TLC393MP —
The D package is available taped and reeled. Add the suffix R to the device type (e.g., TLC393CDR).
schematic
OUT
OPEN-DRAIN CMOS OUTPUT
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VDD (see Note 1) − 0.3 V to 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, VID (see Note 2) ±18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI − 0.3 V to VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO − 0.3 V to 16 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current, II ±5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current, IO (each output) 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total supply current into VDD 40 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Total current out of GND 40 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range: TLC393C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLC393I − 40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLC393Q − 40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLC393M − 55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLC193M − 55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range − 65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Case temperature for 60 seconds: FK package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or P package 260°C. . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package 300°C. . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to network ground.
2. Differential voltages are at IN+ with respect to IN−.
DISSIPATION RATING TABLE
PACKAGE TA ≤ 25°C
POWER RATING DERATING FACTOR
ABOVE TA = 25°CTA = 70°C
POWER RATING TA = 85°C
POWER RATING TA = 125°C
POWER RATING
D725 mW 5.8 mW/°C464 mW 377 mW 145 mW
FK 1375 mW 11.0 mW/°C880 mW 715 mW 275 mW
JG 1050 mW 8.4 mW/°C672 mW 546 mW 210 mW
P1000 mW 8.0 mW/°C640 mW 520 mW —
PW 525 mW 4.2 mW/°C336 mW 273 mW —
SLCS115E − DECEMBER 1986 − REVISED JULY 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
recommended operating conditions
TLC393C
UNIT
MIN NOM MAX UNIT
Supply voltage, VDD 3 5 16 V
Common-mode input voltage, VIC −0.2 VDD − 1.5 V
Low-level output current, IOL 20 mA
Operating free-air temperature, TA0 70 °C
electrical characteristics at specified operating free-air temperature, VDD = 5 V (unless otherwise
noted)
PARAMETER
TEST CONDITIONS†
T
TLC393C
UNIT
PARAMETER TEST CONDITIONS†TAMIN TYP MAX UNIT
V
Inp t offset oltage
VIC = VICRmin,
VDD 5Vto10V
25°C 1.4 5
mV
VIO Input offset voltage VDD = 5 V to 10 V,
See Note 3 0°C to 70°C 6.5 mV
I
Inp t offset c rrent
V 25V
25°C 1 pA
IIO Input offset current VIC = 2.5 V 70°C 0.3 nA
I
Inp t bias c rrent
V 25V
25°C 5 pA
IIB Input bias current VIC = 2.5 V 70°C 0.6 nA
V
Common mode inp t oltage range
25°C0 to VDD − 1
V
VICR Common-mode input voltage range 0°C to 70°C0 to VDD − 1.5 V
25°C 84
CMMR Common-mode rejection ratio VIC = VICRmin 70°C 84 dB
CMMR
Common mode
rejection
ratio
VIC
VICRmin
0°C 84
dB
25°C 85
kSVR Supply-voltage rejection ratio VDD = 5 V to 10 V 70°C 85 dB
kSVR
Su ly voltage
rejection
ratio
VDD
5
V
to
10
V
0°C 85
dB
V
Lo le el o tp t oltage
V1V I 6mA
25°C 300 400
mV
VOL Low-level output voltage VID = −1 V, IOL = 6 mA 70°C 650 mV
I
High le el o tp t c rrent
V1VV5V
25°C 0.8 40 nA
IOH High-level output current VID = 1 V, VO = 5 V 70°C 1 µA
IDD
Su
pp
ly current (both com
p
arators)
Out
p
uts low No load
25°C 22 40
µA
IDD Supply current (both comparators) Outputs low, No load 0°C to 70°C 50 µA
†All characteristics are measured with zero common-mode voltage unless otherwise noted.
NOTE 3: The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V.
SLCS115D − DECEMBER 1986 − REVISED JULY 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
recommended operating conditions
TLC393I
UNIT
MIN NOM MAX UNIT
Supply voltage, VDD 3 5 16 V
Common-mode input voltage, VIC − 0.2 VDD − 1.5 V
Low-level output current, IOL 20 mA
Operating free-air temperature, TA− 40 85 °C
electrical characteristics at specified operating free-air temperature, VDD = 5 V (unless otherwise
noted)
PARAMETER
TEST CONDITIONS†
T
TLC393I
UNIT
PARAMETER TEST CONDITIONS†TAMIN TYP MAX UNIT
V
Inp t offset oltage
VIC = VICRmin,
VDD 5Vto10V
25°C 1.4 5
mV
VIO Input offset voltage VDD = 5 V to 10 V,
See Note 3 −40°C to 85°C 7 mV
I
Inp t offset c rrent
V 25V
25°C 1 pA
IIO Input offset current VIC = 2.5 V 85°C 1 nA
I
Inp t bias c rrent
V 25V
25°C 5 pA
IIB Input bias current VIC = 2.5 V 85°C 2 nA
V
Common mode inp t oltage range
25°C0 to VDD − 1
V
VICR Common-mode input voltage range −40°C to 85°C0 to VDD − 1.5 V
25°C 84
CMMR Common-mode rejection ratio VIC = VICRmin 85°C 84 dB
CMMR
Common mode
rejection
ratio
VIC
VICRmin
− 40°C 84
dB
25°C 85
kSVR Supply-voltage rejection ratio VDD = 5 V to 10 V 85°C 85 dB
kSVR
Su ly voltage
rejection
ratio
VDD
5
V
to
10
V
− 40°C 84
dB
V
Lo le el o tp t oltage
V1V I 6mA
25°C 300 400
mV
VOL Low-level output voltage VID = −1 V, IOL = 6 mA 85°C 700 mV
I
High le el o tp t c rrent
V1VV5V
25°C 0.8 40 nA
IOH High-level output current VID = 1 V, VO = 5 V 85°C 1 µA
IDD
Su
pp
ly current (both com
p
arators)
Out
p
uts low No load
25°C 22 40
µA
IDD Supply current (both comparators) Outputs low, No load −40°C to 85°C 65 µA
†All characteristics are measured with zero common-mode voltage unless otherwise noted.
NOTE 3: The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V.
SLCS115E − DECEMBER 1986 − REVISED JULY 2003
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
recommended operating conditions
TLC393Q
UNIT
MIN NOM MAX UNIT
Supply voltage, VDD 4 5 16 V
Common-mode input voltage, VIC 0 VDD − 1.5 V
Low-level output current, IOL 20 mA
Operating free-air temperature, TA−40 125 °C
electrical characteristics at specified operating free-air temperature, VDD = 5 V (unless otherwise
noted)
PARAMETER
TEST CONDITIONS†
T
TLC393Q
UNIT
PARAMETER TEST CONDITIONS†TAMIN TYP MAX UNIT
V
Inp t offset oltage
VIC = VICRmin,
VDD 5Vto10V
25°C 1.4 5
mV
VIO Input offset voltage VDD = 5 V to 10 V,
See Note 4 −40°C to 125°C 10 mV
I
Inp t offset c rrent
V 25V
25°C 1 pA
IIO Input offset current VIC = 2.5 V 125°C 15 nA
I
Inp t bias c rrent
V 25V
25°C 5 pA
IIB Input bias current VIC = 2.5 V 125°C 30 nA
V
Common mode inp t oltage range
25°C0 to VDD − 1
V
VICR Common-mode input voltage range −40°C to 125°C0 to VDD − 1.5 V
25°C 84
CMMR Common-mode rejection ratio VIC = VICRmin 125°C 84 dB
CMMR
Common mode
rejection
ratio
VIC
VICRmin
−40°C 84
dB
25°C 85
kSVR Supply-voltage rejection ratio VDD = 5 V to 10 V 125°C 84 dB
kSVR
Su ly voltage
rejection
ratio
VDD
5
V
to
10
V
−40°C 84
dB
V
Lo le el o tp t oltage
V1V I 6mA
25°C 300 400
mV
VOL Low-level output voltage VID = −1 V, IOL = 6 mA 125°C 800 mV
I
High le el o tp t c rrent
V1VV5V
25°C 0.8 40 nA
IOH High-level output current VID = 1 V, VO = 5 V 125°C 1 µA
IDD
Su
pp
ly current (both com
p
arators)
Out
p
uts low No load
25°C 22 40
µA
IDD Supply current (both comparators) Outputs low, No load −40°C to 125°C 90 µA
†All characteristics are measured with zero common-mode voltage unless otherwise noted.
NOTE 4: The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V (with a 2.5-kΩ load to
VDD).
SLCS115D − DECEMBER 1986 − REVISED JULY 2003
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
recommended operating conditions
TLC193M, TLC393M
UNIT
MIN NOM MAX UNIT
Supply voltage, VDD 4 5 16 V
Common-mode input voltage, VIC 0 VDD − 1.5 V
Low-level output current, IOL 20 mA
Operating free-air temperature, TA−55 125 °C
electrical characteristics at specified operating free-air temperature, VDD = 5 V (unless otherwise
noted)
PARAMETER
TEST CONDITIONS†
T
TLC193M, TLC393M
UNIT
PARAMETER TEST CONDITIONS†TAMIN TYP MAX UNIT
V
Inp t offset oltage
VIC = VICRmin,
VDD 5Vto10V
25°C 1.4 5
mV
VIO Input offset voltage VDD = 5 V to 10 V,
See Note 4 −55°C to 125°C 10 mV
I
Inp t offset c rrent
V 25V
25°C 1 pA
IIO Input offset current VIC = 2.5 V 125°C 15 nA
I
Inp t bias c rrent
V 25V
25°C 5 pA
IIB Input bias current VIC = 2.5 V 125°C 30 nA
V
Common mode inp t oltage range
25°C0 to VDD − 1
V
VICR Common-mode input voltage range −55°C to 125°C0 to VDD − 1.5 V
25°C 84
CMMR Common-mode rejection ratio VIC = VICRmin 125°C 84 dB
CMMR
Common mode
rejection
ratio
VIC
VICRmin
−55°C 84
dB
25°C 85
kSVR Supply-voltage rejection ratio VDD = 5 V to 10 V 125°C 84 dB
kSVR
Su ly voltage
rejection
ratio
VDD
5
V
to
10
V
−55°C 84
dB
V
Lo le el o tp t oltage
V1V I 6mA
25°C 300 400
mV
VOL Low-level output voltage VID = −1 V, IOL = 6 mA 125°C 800 mV
I
High le el o tp t c rrent
V1VV5V
25°C 0.8 40 nA
IOH High-level output current VID = 1 V, VO = 5 V 125°C 1 µA
IDD
Su
pp
ly current (both com
p
arators)
Out
p
uts low No load
25°C 22 40
µA
IDD Supply current (both comparators) Outputs low, No load −55°C to 125°C 90 µA
†All characteristics are measured with zero common-mode voltage unless otherwise noted.
NOTE 4: The offset voltage limits given are the maximum values required to drive the output up to 4.5 V or down to 0.3 V (with a 2.5-kΩ load to
VDD).
SLCS115E − DECEMBER 1986 − REVISED JULY 2003
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
switching characteristics, VDD = 5 V, TA = 25°C (see Figure 3)
PARAMETER TEST CONDITIONS
TLC393C, TLC393I
TLC393Q, TLC193M,
TLC393M UNIT
MIN TYP MAX
Overdrive = 2 mV 4.5
f10kH
Overdrive = 5 mV 2.5
tPLH Propagation delay time, low-to-high-level output f = 10 kHz,
CL=15
p
F
Overdrive = 10 mV 1.7 µs
tPLH
Pro agation
delay
time,
low to high level
out ut
C
L =
15
p
F
Overdrive = 20 mV 1.2
µs
Overdrive = 40 mV 1.1
VI = 1.4-V step at IN+ 1.1
Overdrive = 2 mV 3.6
f10kH
Overdrive = 5 mV 2.1
tPHL Propagation delay time, high-to-low-level output f = 10 kHz,
CL=15
p
F
Overdrive = 10 mV 1.3 µs
tPHL
Pro agation
delay
time,
high to low level
out ut
C
L =
15
p
F
Overdrive = 20 mV 0.85
µs
Overdrive = 40 mV 0.55
VI = 1.4-V step at IN+ 0.10
tfFall time, output f = 10 kHz,
CL = 15 pF Overdrive = 50 mV 22 ns
PARAMETER MEASUREMENT INFORMATION
The TLC393 contains a digital output stage which, if held in the linear region of the transfer curve, can cause
damage to the device. Conventional operational amplifier/comparator testing incorporates the use of a servo
loop that is designed to force the device output to a level within this linear region. Since the servo-loop method
of testing cannot be used, the following alternatives for testing parameters such as input offset voltage,
common-mode rejection ratio, etc., are suggested.
To verify that the input of fset voltage falls within the limits specified, the limit value is applied to the input as shown
in Figure 1(a). With the noninverting input positive with respect to the inverting input, the output should be high.
With the input polarity reversed, the output should be low.
A similar test can be made to verify the input offset voltage at the common-mode extremes. The supply voltages
can be slewed as shown in Figure 1(b) for the VICR test, rather than changing the input voltages, to provide
greater accuracy.
+
−
5 V
Applied VIO
Limit VO
+
−
1 V
Applied VIO
Limit VO
− 4 V
(a) VIO WITH VIC = 0 V (b) VIO WITH VIC = 4 V
5.1 kΩ5.1 kΩ
Figure 1. Method for Verifying That Input Offset Voltage Is Within Specified Limits
SLCS115D − DECEMBER 1986 − REVISED JULY 2003
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PARAMETER MEASUREMENT INFORMATION
A close approximation of the input offset voltage can be obtained by using a binary search method to vary the
differential input voltage while monitoring the output state. When the applied input voltage differential is equal,
but opposite in polarity, to the input offset voltage, the output changes states.
Figure 2 illustrates a practical circuit for direct dc measurement of input offset voltage that does not bias the
comparator in the linear region. The circuit consists of a switching-mode servo loop in which U1A generates
a triangular waveform of approximately 20-mV amplitude. U1B acts as a buffer, with C2 and R4 removing any
residual dc offset. The signal is then applied to the inverting input of the comparator under test, while the
noninverting input is driven by the output of the integrator formed by U1C through the voltage divider formed
by R9 and R10. The loop reaches a stable operating point when the output of the comparator under test has
a duty cycle of exactly 50%, which can only occur when the incoming triangle wave is sliced symmetrically or
when the voltage at the noninverting input exactly equals the input offset voltage.
The voltage divider formed by R9 and R10 provides an increase in input offset voltage by a factor of 100 to
make measurement easier. The values of R5, R8, R9, and R10 can significantly influence the accuracy of the
reading; therefore, it is suggested that their tolerance level be 1% or lower.
Measuring the e xtremely low values of input current requires isolation from all other sources of leakage current
and compensation for the leakage of the test socket and board. With a good picoammeter , the socket and board
leakage can be measured with no device in the socket. Subsequently, this open-socket leakage value can be
subtracted from the measurement obtained with a device in the socket to obtain the actual input current of the
device.
−
+
DUT
VDD
+
−
−
+
−
+
C2
1 µF
R4
47 kΩ
R5
1.8 kΩ, 1%
C3
0.68 µF
U1C
1/4 TLC274CN
U1B
1/4 TLC274CN
U1A
1/4 TLC274CN
R7
1 MΩ
R8
1.8 kΩ, 1%
R9
10 kΩ, 1%
R1
240 kΩ
R2
10 kΩ
C1
0.1 µF
R3
100 kΩ
C4
0.1 µF
Integrator
R10
100 Ω, 1%
Buffer
Triangle
Generator
VIO
(X100)
R6
5.1 kΩ
Figure 2. Circuit for Input Offset Voltage Measurement
SLCS115E − DECEMBER 1986 − REVISED JULY 2003
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PARAMETER MEASUREMENT INFORMATION
Propagation delay time is defined as the interval between the application of an input step function and the instant
when the output reaches 50% of its maximum value. Propagation delay time, low-to-high-level output, is
measured from the leading edge of the input pulse, while propagation delay time, high-to-low-level output, is
measured from the trailing edge of the input pulse. Propagation delay time measurement at low input signal
levels can be greatly affected by the input offset voltage. The offset voltage should be balanced by the
adjustment at the inverting input (as shown in Figure 3) so that the circuit is just at the transition point. Then a
low signal, for example, 105 mV or 5 mV overdrive, causes the output to change state.
DUT
VDD
CL
(see Note A)
Pulse
Generator
10 Ω
10 Turn
1 V
− 1 V1 kΩ
50 Ω
1 µF
0.1 µF
TEST CIRCUIT
100 mV
Input
Overdrive
50%
tPLH
100 mVInput
Overdrive
90%
50%
10%
tf
tPHL
Low-to-High-
Level Output High-to-Low-
Level Output
VOLTAGE WAVEFORMS
5.1 kΩ
Input Offset Voltage
Compensation
Adjustment
90%
tr
10%
NOTE A: CL includes probe and jig capacitance.
Figure 3. Propagation Delay, Rise Time, and Fall Time Circuit and Voltage Waveforms
SLCS115D − DECEMBER 1986 − REVISED JULY 2003
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO Input offset voltage Distribution 4
IIB Input bias current vs Free-air temperature 5
CMRR Common-mode rejection ratio vs Free-air temperature 6
kSVR Supply-voltage rejection ratio vs Free-air temperature 7
V
Lo le el o tp t oltage
vs Low-level output current 8
VOL Low-level output voltage
vs
Low level
out ut
current
vs Free-air temperature
8
9
I
Lo le el o tp t c rrent
vs High-level output voltage 10
IOH Low-level output current
vs
High level
out ut
voltage
vs Free-air temperature
10
11
I
S ppl c rrent
vs Supply voltage 12
IDD Supply current
vs
Su ly
voltage
vs Free-air temperature
12
13
tPLH Low-to-high level output propagation delay time vs Supply voltage 14
tPHL High-to-low level output propagation delay time vs Supply voltage 15
Low-to-high-level output response Low-to-high level output propagation delay time 16
High-to-low level output response High-to-low level output propagation delay time 17
tfFall time vs Supply voltage 18
Figure 4
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Ç
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Ç
Number of Units
VDD = 5 V
VIC = 2.5 V
TA = 25°C
−5−4−3−2−10 1 2 3 4 5
VIO − Input Offset Voltage − mV
DISTRIBUTION OF INPUT
OFFSET VOLTAGE†
100
90
80
70
60
50
40
30
20
10
0
Ç
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
Figure 5
I
TA − Free-Air Temperature − °C
IB
− Input Bias Current − nA
25 50 75 100 125
10
1
0.1
0.01
0.001
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE†
VDD = 5 V
VIC = 2.5 V
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
SLCS115E − DECEMBER 1986 − REVISED JULY 2003
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TYPICAL CHARACTERISTICS†
Figure 6
CMRR − Common-Mode
TA − Free-Air Temperature − °C
COMMON-MODE REJECTION RATIO
vs
FREE-AIR TEMPERATURE
Rejection Ratio − dB
−75 −50 −25 0 25 50 75 100 125
90
89
88
87
86
85
84
83
82
81
80
VDD = 5 V
Figure 7
− Supply Voltage Rejection Ratio − dB
TA − Free-Air Temperature − °C
SUPPLY VOLTAGE REJECTION RATIO
vs
FREE-AIR TEMPERATURE
−75 −50 −25 0 25 50 75 100 125
90
89
88
87
86
85
84
83
82
81
80
VDD = 5 V to 10 V
SVR
k
Figure 8
IOL − Low-Level Output Current − mA
0 2 4 6 81012141618 20
VOL − Low-Level Output Voltage − V
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
4 V
10 V
VDD = 16 V
5 V
1.5
1.25
1
0.75
0.5
0.25
0
TA = 25°C
VDD = 3 V
Figure 9
−75 −50 −25 0 25 50 75 100 125
TA − Free-Air Temperature − °C
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
VOL − Low-Level Output Voltage − mV
600
500
400
300
200
100
0
VDD = 5 V
IOL = 6 mA
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
SLCS115D − DECEMBER 1986 − REVISED JULY 2003
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TYPICAL CHARACTERISTICS†
Figure 10
IOH − High-Level Output Current − nA
024 6810121416
VOH − High-Level Output Voltage − V
HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
1000
100
10
1
0.1
TA = 25°C
TA = 125°C
TA = 85°C
TA = 70°C
VOH = VDD
Figure 11
TA − Free-Air Temperature − °C
IOH − High-Level Output Current − nA
25 50 75 100 125
HIGH-LEVEL OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
1000
100
10
1
0.1
VDD = VOH = 5 V
Figure 12
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
VDD − Supply Voltage − V
40
35
30
25
20
15
10
5
00246810121416
I − Supply Current − µ
DD A
TA = − 55°C
TA = 125°C
TA = 85°C
TA = − 40°C
Outputs Low
No Loads
TA = 25°C
50
45
Figure 13
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
30
25
20
15
10
5
0
−75 −50 −25 0 25 50 75 100 125
TA − Free-Air Temperature − °C
IDD − Supply Current −µA
40
35
Outputs High
Outputs Low
VDD = 5 V
No Load
†Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
SLCS115E − DECEMBER 1986 − REVISED JULY 2003
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TYPICAL CHARACTERISTICS
Figure 14
LOW-TO-HIGH-LEVEL
OUTPUT RESPONSE TIME
vs
SUPPLY VOLTAGE
Overdrive = 2 mV
5 mV
10 mV
40 mV
6
5
4
3
2
1
00 2 4 6 810121416
VDD − Supply Voltage − V
CL = 15 pF
RL = 5.1 kΩ (pullup to VDD)
TA = 25°C
tPLH − Low-to-High-Level
20 mV
Output Propagation Delay Time −µs
Figure 15
HIGH-TO-LOW-LEVEL
OUTPUT RESPONSE TIME
vs
SUPPLY VOLTAGE
3
2.5
2
1.5
1
0.5
00246810121416
VDD − Supply Voltage − V
tPHL − High-to-Low Level
Output Propagation Delay Time −µs
Overdrive = 2 mV
CL = 15 pF
RL = 5.1 kΩ (pullup to VDD)
TA = 25°C
5
4.5
4
3.5
5 mV
10 mV
20 mV
40 mV
Figure 16
012345
VO − Output
Voltage − V
Voltage − mV
Differential Input
LOW-TO-HIGH-LEVEL OUTPUT
PROPAGATION DELAY
FOR VARIOUS INPUT OVERDRIVES
tPLH − Low-to-High-Level Output
Propagation Delay Time − µs
VDD = 5 V
CL = 15 pF
RL = 5.1 kΩ (pullup to VDD)
TA = 25°C
5
0
100
0
40 mV
20 mV
10 mV
5 mV
2 mV
Figure 17
40 mV
20 mV
10 mV
5 mV
2 mV
HIGH-TO-LOW-LEVEL OUTPUT
PROPAGATION DELAY
FOR VARIOUS INPUT OVERDRIVES
tPHL − High-to-Low-Level Output
Propagation Delay Time − µs
VO − Output
Voltage − V
Voltage − mV
Differential Input
5
0
100
0
012 345
VDD = 5 V
CL = 15 pF
RL = 5.1 kΩ (pullup to VDD)
TA = 25°C
SLCS115D − DECEMBER 1986 − REVISED JULY 2003
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
TYPICAL CHARACTERISTICS
0246810
VDD − Supply Voltage − V
tf − Fall Time −ns
OUTPUT FALL TIME
vs
SUPPLY VOLTAGE
60
50
40
30
20
0
10 50-mV Overdrive
RL = 5.1 kΩ (pullup to VDD)
TA = 25°C
12 14 16
CL = 100 pF
15 pF
50 pF
Figure 18
APPLICATION INFORMATION
The input should always remain within the supply rails in order to avoid forward biasing the diodes in the electrostatic
discharge (ESD) protection structure. If either input exceeds this range, the device will not be damaged as long as
the input current is limited to less than 5 mA. To maintain the expected output state, the inputs must remain within
the common-mode range. For example, at 25°C with VDD = 5 V, both inputs must remain between −0.2 V and 4 V
to assure proper device operation.
To assure reliable operation, the supply should be decoupled with a capacitor (0.1-µF) positioned as close to the
device as possible.
The TLC393 has internal ESD-protection circuits that prevent functional failures at voltages up to 2000 V as tested
under MIL-STD-883C, Method 3015.2; however, care should be exercised in handling these devices, as exposure
to ESD may result in the degradation of the device parametric performance.
Table of Applications
FIGURE
Pulse-width-modulated motor speed controller 19
Enhanced supply supervisor 20
Two-phase nonoverlapping clock generator 21
Micropower switching regulator 28
SLCS115E − DECEMBER 1986 − REVISED JULY 2003
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
APPLICATION INFORMATION
C1
0.01 µF
(see Note B)
5 V
1/2 TLC393
Motor Speed Control
Potentiometer
+
−
+
−10 kΩ
100 kΩ
10 kΩ
10 kΩ
1/2 TLC393
10 kΩ
5 V
DIR
EN
SN75603
Half-H Driver
12 V
Motor
DIR
EN
12 V
Direction
Control S1
SPDT
5 V
5 V
C2
(see Note A)
5.1 kΩ
5.1 kΩ
12 V
SN75604
Half-H Driver
NOTES: A. The recommended minimum capacitance is 10 µF to eliminate common ground switching noise.
B. Adjust C1 for change in oscillator frequency.
Figure 19. Pulse-Width-Modulated Motor Speed Controller
SLCS115D − DECEMBER 1986 − REVISED JULY 2003
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
APPLICATION INFORMATION
1/2 TLC393
To µP Interrupt
Early Power Fail
+
−
+
−
1 kΩ
3.3 kΩ
CT
(see Note B)
1/2 TLC393
10 kΩ
5 V
5 V
12-V
Sense
R2
R1
VUNREG
(see Note A)
1 µF
12 V
RESIN
REF CTGND
RESET
SENSEVCC
To µP
Reset
Monitors 5-VDC Rail
Monitors 12-VDC Rail
Early Power Fail Warning
TL7705A
2.5 V
5.1 kΩ
5.1 kΩ
12 V
NOTES: A. VUNREG +2.5(R1 +R2)
R2
B. The value of CT determines the time delay of reset.
Figure 20. Enhanced Supply Supervisor
SLCS115E − DECEMBER 1986 − REVISED JULY 2003
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
APPLICATION INFORMATION
−
+22 kΩC1
0.01 µF
(see Note A)
1/2 TLC393
R1
100 Ω
(see Note B)
100 kΩ
1/2 TLC393
2OUT
−
+
−
+
1/2 TLC393
100 kΩ100 kΩ
12 V
1OUT
12 V
R2
5 kΩ
(see Note C)
R3
100 kΩ
(see Note B)
2OUT
1OUT
12 V
5.1 kΩ
12 V
5.1 kΩ
12 V
5.1 kΩ
NOTES: A. Adjust C1 for a change in oscillator frequency where:
1/f = 1.85(100 kΩ)C1
B. Adjust R1 and R3 to change duty cycle
C. Adjust R2 to change deadtime
Figure 21. Two-Phase Nonoverlapping Clock Generator
PACKAGE OPTION ADDENDUM
www.ti.com 29-Sep-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
5962-9555101NXD ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
5962-9555101NXDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
5962-9555101QPA ACTIVE CDIP JG 8 1 TBD Call TI Call TI
TLC193MFKB OBSOLETE LCCC FK 20 TBD Call TI Call TI
TLC193MJGB ACTIVE CDIP JG 8 1 TBD A42 N / A for Pkg Type
TLC393CD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC393CDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC393CDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC393CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC393CP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC393CPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC393CPSR ACTIVE SO PS 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC393CPSRG4 ACTIVE SO PS 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC393CPW ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC393CPWG4 ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC393CPWLE OBSOLETE TSSOP PW 8 TBD Call TI Call TI
TLC393CPWR ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC393CPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC393ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 29-Sep-2011
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLC393IDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC393IDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC393IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC393IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC393IPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC393IPW ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC393IPWG4 ACTIVE TSSOP PW 8 150 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC393IPWLE OBSOLETE TSSOP PW 8 TBD Call TI Call TI
TLC393IPWR ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC393IPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC393MD OBSOLETE SOIC D 8 TBD Call TI Call TI
TLC393MP OBSOLETE PDIP P 8 TBD Call TI Call TI
TLC393QDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC393QDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
PACKAGE OPTION ADDENDUM
www.ti.com 29-Sep-2011
Addendum-Page 3
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLC393 :
•Automotive: TLC393-Q1
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
5962-9555101NXDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC393CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC393CPSR SO PS 8 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
TLC393CPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TLC393IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC393IPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TLC393QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
5962-9555101NXDR SOIC D 8 2500 367.0 367.0 35.0
TLC393CDR SOIC D 8 2500 340.5 338.1 20.6
TLC393CPSR SO PS 8 2000 367.0 367.0 38.0
TLC393CPWR TSSOP PW 8 2000 367.0 367.0 35.0
TLC393IDR SOIC D 8 2500 340.5 338.1 20.6
TLC393IPWR TSSOP PW 8 2000 367.0 367.0 35.0
TLC393QDR SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUAR Y 1997
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE
0.310 (7,87)
0.290 (7,37)
0.014 (0,36)
0.008 (0,20)
Seating Plane
4040107/C 08/96
5
4
0.065 (1,65)
0.045 (1,14)
8
1
0.020 (0,51) MIN
0.400 (10,16)
0.355 (9,00)
0.015 (0,38)
0.023 (0,58)
0.063 (1,60)
0.015 (0,38)
0.200 (5,08) MAX
0.130 (3,30) MIN
0.245 (6,22)
0.280 (7,11)
0.100 (2,54)
0°–15°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
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