UCC27323, UCC27324, UCC27325
UCC37323, UCC37324, UCC37325
SLUS492G -- JUNE 2001 -- REVISED MARCH 2010
DUAL 4-A PEAK HIGH SPEED LOW- SIDE POWER MOSFET DRIVERS
1
www.ti.com
FEATURES
DIndustry-Standard Pin-Out
DHigh Current Drive Capability of ±4Aatthe
Miller Plateau Region
DEfficient Constant Current Sourcing Even at
Low Supply Voltages
DTTL/CMOS Compatible Inputs Independent
of Supply Voltage
D20-ns Typical Rise and 15-ns Typical Fall
Times with 1.8-nF Load
DTypical Propagation Delay Times of 25 ns
with Input Falling and 35 ns with Input Rising
D4.5-V to 15-V Supply Voltage
DSupply Current of 0.3 mA
DDual Outputs Can Be Paralleled for Higher
Drive Current
DAvailable in Thermally Enhanced MSOP
PowerPADTM Package with 4.7°C/W θjc
DRated From –40°C to 125°C
DTrueDrive Output Architecture Using Bipolar
and CMOS Transistors in Parallel
APPLICATIONS
DSwitch Mode Power Supplies
DDC/DC Converters
DMotor Controllers
DLine Drivers
DClass D Switching Amplifiers
DESCRIPTION
The UCC37323/4/5 family of high-speed dual
MOSFET drivers can deliver large peak currents
into capacitive loads.Three standard logic options
are offered – dual-inverting, dual-noninverting
and one-inverting and one-noninverting driver.
The thermally enhanced 8-pin PowerPADTM
MSOP package (DGN) drastically lowers the
thermal resistance to improve long-term reliability.
It is also offered in the standard SOIC-8 (D) or
PDIP-8 (P) packages.
Using a design that inherently minimizes
shoot-through current, these drivers deliver 4-A of
current where it is needed most at the Miller
plateau region during the MOSFET switching
transition. A unique BiPolar and MOSFET hybrid
output stage in parallel also allows efficient current
sourcing and sinking at low supply voltages.
BLOCK DIAGRAM
1
OUTA
N/C
2INA
3GND
7
N/C8
INVERTING
NON--INVERTING
OUTB
45
INVERTING
NON--INVERTING
INB
6VDD
UDG--01063
PowerPADtis a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright ©2010, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
f
Te
x
as Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
UCC27323, UCC27324, UCC27325
UCC37323, UCC37324, UCC37325
SLUS492G -- JUNE 2001 -- REVISED MARCH 2010
2www.ti.com
ORDERING INFORMATION
O
U
T
P
U
T
T
E
M
P
E
R
A
T
U
R
E
R
A
N
G
E
PACKAGED DEVICES
OUTPUT
CONFIGURATION
TEMPER
A
TURE R
A
NGE
TA=T
JSOIC-8 (D) MSOP-8 PowerPAD
(DGN)}PDIP-8 (P)
D
u
a
n
v
e
r
t
n
g
-- 4 0 °C to +125°C UCC27323D UCC27323DGN UCC27323P
Dual inverting 0°Cto+70°C UCC37323D UCC37323DGN UCC37323P
D
u
a
n
o
n
I
n
v
e
r
t
n
g
-- 4 0 °C to +125°C UCC27324D UCC27324DGN UCC27324P
Dual nonInverting 0°Cto+70°C UCC37324D UCC37324DGN UCC37324P
One invertin
g
,
-- 4 0 °C to +125°C UCC27325D UCC27325DGN UCC27325P
O
n
e
n
v
e
r
t
n
g
,
one noninverting 0°Cto+70°C UCC37325D UCC37325DGN UCC37325P
†D (SOIC--8) and DGN (PowerPAD--MSOP) packages are available taped and reeled. Add R suffix to device type (e.g. UCC27323DR,
UCC27324DGNR) to order quantities of 2,500 devices per reel for D or 1,000 devices per reel for DGN package.
‡The PowerPAD™is not directly connected to any leads of the package. However, it is electrically and thermally connected to the substrate which
is the ground of the device.
D, DGN, OR P PACKAGE
(TOP VIEW)
VDD
OUTA
N/A
OUTB
INA
N/A
GND
INB
1
2
3
4
8
7
6
5
D, DGN, OR P PACKAGE
(TOP VIEW)
VDD
OUTA
N/A
OUTB
INA
N/A
GND
INB
1
2
3
4
8
7
6
5
D, DGN, OR P PACKAGE
(TOP VIEW)
VDD
OUTA
N/A
OUTB
INA
N/A
GND
INB
1
2
3
4
8
7
6
5
(DUAL INVERTING) (DUAL NONINVERTING)
(ONE INVERTING,
ONE NONINVERTING)
power dissipation rating table
PACKAGE SUFFIX Θjc (°C/W) Θja (°C/W) Power Rating (mW)
TA=70°CSeeNote1
Derating Factor Above
70°C(mW/°C) See
Note 1
SOIC-8 D42 84 – 160}344--655 See Note 2 6.25 -- 11.9 See Note 2
PDIP-8 P49 110 500 9
MSOP PowerPAD-8
SeeNote3 DGN 4.7 50 -- 59}1370 17.1
Notes: 1. 125°C operating junction temperature is used for power rating calculations
2. The range of values indicates the effect of pc--board. These values are intended to give the system designer an indication of the
best and worst case conditions. In general, the system designer should attempt to use larger traces on the pc--board where possible
in order to spread the heat away form the device more effectively. For information on the PowerPADtpackage, refer to Technical
Brief, PowerPad Thermally Enhanced Package, Texas Instrument s Literature No. SLMA002 and Application Brief, PowerPad Made
Easy, Texas Instruments Literature No. SLMA004.
3. The PowerPAD™is not directly connected to any leads of the package. However, it is electrically and thermally connected to the
substrate which is the ground of the device.
Table 1. Input/Output Table
INPUTS (VIN_L, VIN_H) UCC37323 UCC37324 UCC37325
INA INB OUTA OUTB OUTA OUTB OUTA OUTB
L L H H L L H L
L H H L L H H H
H L L H H L L L
H H L L H H L H
UCC27323, UCC27324, UCC27325
UCC37323, UCC37324, UCC37325
SLUS492G -- JUNE 2001 -- REVISED MARCH 2010
3
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absolute maximum ratings over operating free-air temperature (unless otherwise noted)†}
Supply voltage, VDD --0.3 V to 16 V...............................................................
Analog input voltage (INA, INB) --0.3 V to VDD + 0.3 V, not to exceed 16 V.............................
Output voltage, (OUTA, OUTB) 16 V..............................................................
Output body diode DC current, (OUTA, OUTB) 0.2 A...............................................
Output current (OUTA, OUTB) DC, IOUT_DC 0.2 A.................................................
Pulsed, (0.5 μs), IOUT_PULSED 4.5 A..................................
Power dissipation at TA=25°C (DGN package) 2.12 W.............................................
(D package) 1.14 W.................................................
(P package) 780 mW................................................
Junction operating temperature, TJ-- 5 5 °C to 150°C.................................................
Storage temperature, Tstg -- 6 5 °C to 150°C.........................................................
Lead temperature (soldering, 10 sec.), 300°C......................................................
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal.
electrical characteristics, VDD =4.5Vto15V,T
A=T
J, (unless otherwise noted)
input (INA, INB)
PARAMETER TEST CONDITION MIN TYP MAX UNITS
VIN_H, logic 1 input threshold 2 V
VIN_L, logic 0 input threshold 1 V
Input current 0V<=VIN <= VDD -- 1 0 010 μA
output (OUTA, OUTB)
PARAMETER TEST CONDITION MIN TYP MAX UNITS
Output current VDD =14V, SeeNote1 4 A
VOH, high-level output voltage VOH =VDD –VOUT,IOUT =--10mA 300 450 mV
VOL, low-level output level IOUT =10mA 22 45 mV
Output resistance high TA=25°C, IOUT =--10mA, VDD =14V,
SeeNote2
25 30 35 Ω
TA= full range, IOUT =--10mA, VDD =14V,
SeeNote2
18 42 Ω
Output resistance low TA=25°C, IOUT =10mA, VDD =14V,
SeeNote2
1.9 2.2 2.5 Ω
TA= full range IOUT =10mA, VDD =14V,
SeeNote2
1.2 4.0 Ω
Latch-up protection 500 mA
NOTES: 1 The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The pulsed output current rating is the
combined current from the bipolar and MOSFET transistors.
2 The pullup / pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The output resistance is the RDS(ON) of
the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor.
UCC27323, UCC27324, UCC27325
UCC37323, UCC37324, UCC37325
SLUS492G -- JUNE 2001 -- REVISED MARCH 2010
4www.ti.com
electrical characteristics, VDD =4.5Vto15V,T
A=--40°C to 125°C for the UCC2732x, TA=0°Cto70°C
for the UCC3732x, TA=T
J, (unless otherwise noted)
switching time
PARAMETER TEST CONDITION MIN TYP MAX UNITS
tR, rise time (OUTA, OUTB) CLOAD = 1.8 nF, See Figure 1 20 40 ns
tF
,falltime(OUTA,OUTB) CLOAD = 1.8 nF, See Figure 1 15 40 ns
tD1, delay, IN rising (IN to OUT) CLOAD = 1.8 nF, See Figure 1 25 40 ns
tD2, delay, IN falling (IN to OUT) CLOAD = 1.8 nF, See Figure 1 35 50 ns
overall
PARAMETER TEST CONDITION MIN TYP MAX UNITS
INA = 0 V, INB = 0 V 300 450
U
C
C
x
7
3
2
3
INA = 0 V, INB = HIGH 300 450
UCCx7323 INA = HIGH, INB = 0 V 300 450
INA = HIGH, INB = HIGH 300 450
INA = 0 V, INB = 0 V 250
I
s
t
a
t
c
o
p
e
r
a
t
n
g
c
u
r
r
e
n
t
U
C
C
x
7
3
2
4
INA = 0 V, INB = HIGH 300 450
A
IDD, static operating current UCCx7324 INA = HIGH, INB = 0 V 300 450 μ
A
INA = HIGH, INB = HIGH 600 750
INA = 0 V, INB = 0 V 150 300
U
C
C
x
7
3
2
5
INA = 0 V, INB = HIGH 450 600
UCCx7325 INA = HIGH, INB = 0 V 150 300
INA = HIGH, INB = HIGH 450 600
+5V
INPUT
16V
OUTPUT
0V
0V
10%
90%
10%
90%
(a)
90%
90%
10%
90%
(b)
INPUT
OUTPUT
10%
tD1 tD2
tFtf
tD1
tF
tF
tD2
Figure 1. Switching Waveforms for (a) Inverting Driver and (b) Noninverting Driver
UCC27323, UCC27324, UCC27325
UCC37323, UCC37324, UCC37325
SLUS492G -- JUNE 2001 -- REVISED MARCH 2010
5
www.ti.com
Terminal Functions
TERMINAL
F
U
N
C
T
I
O
N
NO. NAME I/O FUNCTION
1 N/C -- No connection. Should be grounded.
2 INA I Input A. Input signal of the A driver which has logic compatible threshold and hysteresis.
If not used, this input should be tied to either VDD or GND. It should not be left floating.
3GND -- Common ground. This ground should be connected very closely to the source of the
power MOSFET which the driver is driving.
4 INB I Input B. Input signal of the A driver which has logic compatible threshold and hysteresis.
If not used, this input should be tied to either VDD or GND. It should not be left floating.
5OUTB ODriver output B. The output stage is capable of providing 4-A drive current to the gate of
a power MOSFET.
6VDD ISupply. Supply voltage and the power input connection for this device.
7OUTA ODriver output A. The output stage is capable of providing 4-A drive current to the gate of
a power MOSFET.
8 N/C -- No Connection. Should be grounded.
APPLICATION INFORMATION
general information
High frequency power supplies often require high-speed,high-current drivers such as the UCC37323/4/5 family.
A leading application is the need to provide a high power buffer stage between the PWM output of the control
IC and the gates of the primary power MOSFET or IGBT switching devices. In other cases, the driver IC is
utilized to drive the power device gates through a drive transformer. Synchronous rectification supplies also
have the need to simultaneously drive multiple devices which can present an extremely large load to the control
circuitry.
Driver ICs are utilized when it is not feasible to have the primary PWM regulator IC directly drive the switching
devices for one or more reasons. The PWM IC may not have the brute drive capability required for the intended
switching MOSFET, limiting the switching performance in the application. In other cases there may be a desire
to minimize the effect of high frequency switching noise by placing the high current driver physically close to
the load. Also, newer ICs that target the highest operating frequencies may not incorporate onboard gate drivers
at all. Their PWM outputs are only intended to drive the high impedance input to a driver such as the
UCC37323/4/5. Finally, the control IC may be under thermal stress due to power dissipation, and an external
driver can help by moving the heat from the controller to an external package.
UCC27323, UCC27324, UCC27325
UCC37323, UCC37324, UCC37325
SLUS492G -- JUNE 2001 -- REVISED MARCH 2010
6www.ti.com
APPLICATION INFORMATION
input stage
The input thresholds have a 3.3--V logic sensitivity over the full range of VDD voltage; yet it is equally compatable
with0VtoV
DD signals.
The inputs of UCC37323/4/5 family of drivers are designed to withstand 500-mA reverse current without either
damage to the IC for logic upset. The input stage of each driver should be driven by a signal with a short rise
or fall time. This condition is satisfied in typical power supply applications, where the input signals are provided
by a PWM controller or logic gates with fast transition times (<200 ns). The input stages to the drivers function
as a digital gate, and they are not intended for applications where a slow changing input voltage is used to
generate a switching output when the logic threshold of the input section is reached. While this may not be
harmful to the driver, the output of the driver may switch repeatedly at a high frequency.
Users should not attempt to shape the input signals to the driver in an attempt to slow down (or delay) the signal
at the output. If limiting the rise or fall times to the power device is desired, limit the rise or fall times to the power
device, then an external resistance can be added between the output of the driver and the load device, which
is generally a power MOSFET gate. The external resistor may also help remove power dissipation from the IC
package, as discussed in the section on Thermal Considerations.
output stage
Inverting outputs of the UCC37323 and OUTA of the UCC37325 are intended to drive external P-channel
MOSFETs. Noninverting outputs of the UCC37324 and OUTB of the UCC37325 are intended to drive external
N-channel MOSFETs.
Each output stage is capable of supplying ±4-A peak current pulses and swings to both VDD and GND. The
pullup/ pulldown circuits of the driver are constructed of bipolar and MOSFET transistors in parallel. The peak
output current rating is the combined current from the bipolar and MOSFET transistors. The output resistance
is the RDS(on) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage
of the bipolar transistor. Each output stage also provides a very low impedance to overshoot and undershoot
due to the body diode of the internal MOSFET. This means that in many cases, external-schottky-clamp diodes
are not required.
The UCC37323 family delivers 4-A of gate drive where it is most needed during the MOSFET switching
transition – at the Miller plateau region – providing improved efficiency gains. A unique BiPolar and MOSFET
hybrid output stage in parallel also allows efficient current sourcing at low supply voltages.
UCC27323, UCC27324, UCC27325
UCC37323, UCC37324, UCC37325
SLUS492G -- JUNE 2001 -- REVISED MARCH 2010
7
www.ti.com
APPLICATION INFORMATION
source/sink capabilities during Miller plateau
Large power MOSFETs present a large load to the control circuitry. Proper drive is required for efficient, reliable
operation. The UCC37323/4/5 drivers have been optimized to provide maximum drive to a power MOSFET
during the Miller plateau region of the switching transition. This interval occurs while the drain voltage is swinging
between the voltage levels dictated by the power topology, requiring the charging/discharging of the drain-gate
capacitance with current supplied or removed by the driver IC. [1]
Two circuits are used to test the current capabilities of the UCC37323 driver. In each case external circuitry is
added to clamp the output near 5 V while the IC is sinking or sourcing current. An input pulse of 250 ns is applied
at a frequency of 1 kHz in the proper polarity for the respective test. In each test there is a transient period where
the current peaked up and then settled down to a steady-state value. The noted current measurements are
made at a time of 200 ns after the input pulse is applied, after the initial transient.
The first circuit in Figure 2 is used to verify the current sink capability when the output of the driver is clamped
around 5 V, a typical value of gate-source voltage during the Miller plateau region. The UCC37323 is found to
sink 4.5 A at VDD = 15 V and 4.28 A at VDD =12V.
UDG--01065
UCC27323
GND
1
2
3
4INB
INA 7
6
5
8
OUTA
VDD
OUTB
1μF
CER
100 μF
AL EL
DSCHOTTKY
VDD
C2
1μF
VSNS
RSNS
0.1 Ω
C3
100 μF
10 Ω
+DADJ
5.5 V
ENBA ENBB
Signal generator
producing 250 ns
wide pulse
Figure 2.
UCC27323, UCC27324, UCC27325
UCC37323, UCC37324, UCC37325
SLUS492G -- JUNE 2001 -- REVISED MARCH 2010
8www.ti.com
APPLICATION INFORMATION
The circuit shown in Figure 3 is used to test the current source capability with the output clamped to around 5 V
with a string of Zener diodes. The UCC37323 is found to source 4.8 A at VDD = 15 V and 3.7 A at VDD =12V.
UDG--01066
UCC27323
GND
1
2
3
4INB
INA 7
6
5
8
OUTA
VDD
OUTB
1μF
CER
100 μF
AL EL
DSCHOTTKY
VDD
C2
1μF
VSNS
RSNS
0.1 Ω
C3
100 μF
10 Ω
ENBA ENBB
5.5 V
Signal
Generator
250 ns
Figure 3.
It should be noted that the current sink capability is slightly stronger than the current source capability at lower
VDD. This is due to the differences in the structure of the bipolar-MOSFET power output section, where the
current source is a P-channel MOSFET and the current sink has an N-channel MOSFET.
In a large majority of applications it is advantageous that the turn-off capability of a driver is stronger than the
turn-on capability. This helps to ensure that the MOSFET is held OFF during common power supply transients
which may turn the device back ON.
UCC27323, UCC27324, UCC27325
UCC37323, UCC37324, UCC37325
SLUS492G -- JUNE 2001 -- REVISED MARCH 2010
9
www.ti.com
parallel outputs
The A and B drivers may be combined into a single driver by connecting the INA/INB inputs together and the
OUTA/OUTB outputs together. Then, a single signal can control the paralleled combination as shown in
Figure 4.
UDG--01067
UCC37323
GND
1
2
3
4INB
INA 7
6
5
8
OUTA
VDD
OUTB
INPUT
0.1 μF
CER 2.2 μF
VDD = 12 V
CLOAD
Figure 4.
UCC27323, UCC27324, UCC27325
UCC37323, UCC37324, UCC37325
SLUS492G -- JUNE 2001 -- REVISED MARCH 2010
10 www.ti.com
APPLICATION INFORMATION
operational waveforms and circuit layout
Figure 5 shows the circuit performance achievable with a single driver (1/2 of the 8-pin IC) driving a 10-nF load.
The input pulsewidth (not shown) is set to 300 ns to show both transitions in the output waveform. Note the linear
rise and fall edges of the switching waveforms. This is due to the constant output current characteristic of the
driver as opposed to the resistive output impedance of traditional MOSFET-based gate drivers.
Figure 5.
In a power driver operating at high frequency, it is a significant challenge to get clean waveforms without much
overshoot/undershoot and ringing. The low output impedance of these drivers produces waveforms with high
di/dt. This tends to induce ringing in the parasitic inductances. Utmost care must be used in the circuit layout.
It is advantageous to connect the driver IC as close as possible to the leads. The driver IC layout has ground
on the opposite side of the output, so the ground should be connected to the bypass capacitors and the load
with copper trace as wide as possible. These connections should also be made with a small enclosed loop area
to minimize the inductance.
VDD
Although quiescent VDD current is very low, total supply current will be higher, depending on OUTA and OUTB
current and the programmed oscillator frequency. Total VDD current is the sum of quiescent VDD current and
the average OUT current. Knowing the operating frequency and the MOSFET gate charge (Qg), average OUT
current can be calculated from:
IOUT = Qg x f, where f is frequency
For the best high-speed circuit performance, two VDD bypass capacitors are recommended tp prevent noise
problems. The use of surface mount components is highly recommended. A 0.1-μF ceramic capacitor should
be located closest to the VDD to ground connection. In addition, a larger capacitor (such as 1-μF) with relatively
low ESR should be connected in parallel, to help deliver the high current peaks to the load. The parallel
combination of capacitors should present a low impedance characteristic for the expected current levels in the
driver application.
UCC27323, UCC27324, UCC27325
UCC37323, UCC37324, UCC37325
SLUS492G -- JUNE 2001 -- REVISED MARCH 2010
11
www.ti.com
APPLICATION INFORMATION
drive current and power requirements
The UCC37323/4/5 family of drivers are capable of delivering 4-A of current to a MOSFET gate for a period of
several hundred nanoseconds. High peak current is required to turn the device ON quickly. Then, to turn the
device OFF, the driver is required to sink a similar amount of current to ground. This repeats at the operating
frequency of the power device. A MOSFET is used in this discussion because it is the most common type of
switching device used in high frequency power conversion equipment.
References 1 and 2 discuss the current required to drive a power MOSFET and other capacitive-input switching
devices. Reference 2 includes information on the previous generation of bipolar IC gate drivers.
When a driver IC is tested with a discrete, capacitive load it is a fairly simple matter to calculate the power that
is required from the bias supply. The energy that must be transferred from the bias supply to charge the capacitor
is given by:
E=1
2CV2, where C is the load capacitor and V is the bias voltage feeding the driver.
There is an equal amount of energy transferred to ground when the capacitor is discharged. This leads to a
power loss given by the following:
P=2×1
2CV2f, where f is the switching frequency.
This power is dissipated in the resistive elements of the circuit. Thus, with no external resistor between the driver
and gate, this power is dissipated inside the driver. Half of the total power is dissipated when the capacitor is
charged, and the other half is dissipated when the capacitor is discharged. An actual example using the
conditions of the previous gate drive waveform should help clarify this.
With VDD =12V,C
LOAD = 10 nF, and f = 300 kHz, the power loss can be calculated as:
P = 10 nF x (12)2x (300 kHz) = 0.432 W
With a 12-V supply, this would equate to a current of:
I=P
V=0.432 W
12 V =0.036 A
The actual current measured from the supply was 0.037 A, and is very close to the predicted value. But, the
IDD current that is due to the IC internal consumption should be considered. With no load the IC current draw
is 0.0027 A. Under this condition the output rise and fall times are faster than with a load. This could lead to an
almost insignificant, yet measurable current due to cross-conduction in the output stages of the driver. However,
these small current differences are buried in the high frequency switching spikes, and are beyond the
measurement capabilities of a basic lab setup. The measured current with 10-nF load is reasonably close to
that expected.
UCC27323, UCC27324, UCC27325
UCC37323, UCC37324, UCC37325
SLUS492G -- JUNE 2001 -- REVISED MARCH 2010
12 www.ti.com
APPLICATION INFORMATION
The switching load presented by a power MOSFET can be converted to an equivalent capacitance by examining
the gate charge required to switch the device. This gate charge includes the effects of the input capacitance
plus the added charge needed to swing the drain of the device between the ON and OFF states. Most
manufacturers provide specifications that provide the typical and maximum gate charge, in nC, to switch the
device under specified conditions. Using the gate charge Qg, one can determine the power that must be
dissipated when charging a capacitor. This is done by using the equivalence Qg = CeffV to provide the following
equation for power:
P=C×V2×f=Qg×f
This equation allows a power designer to calculate the bias power required to drive a specific MOSFET gate
at a specific bias voltage.
THERMAL INFORMATION
The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal
characteristics of the IC package. In order for a power driver to be useful over a particular temperature range
the package must allow for the efficient removal of the heat produced while keeping the junction temperature
within rated limits. The UCC37323/4/5 family of drivers is available in three different packages to cover a range
of application requirements.
As shown in the power dissipation rating table, the SOIC-8 (D) and PDIP-8 (P) packages each have a power
rating of around 0.5 W with TA=70°C. This limit is imposed in conjunction with the power derating factor also
given in the table. Note that the power dissipation in our earlier example is 0.432 W with a 10-nF load, 12 VDD,
switched at 300 kHz. Thus, only one load of this size could be driven using the D or P package, even if the two
onboard drivers are paralleled. The difficulties with heat removal limit the drive available in the older packages.
The MSOP PowerPAD-8 (DGN) package significantly relieves this concern by offering an effective means of
removing the heat from the semiconductor junction. As illustrated in Reference 3, the PowerPAD packages offer
a leadframe die pad that is exposed at the base of the package. This pad is soldered to the copper on the PC
board directly underneath the IC package, reducing the Θjcdownto4.7°C/W. Data is presented in Reference 3
to show that the power dissipation can be quadrupled in the PowerPAD configuration when compared to the
standard packages. The PC board must be designed with thermal lands and thermal vias to complete the heat
removal subsystem, as summarized in Reference 4. This allows a significant improvement in heatsinking over
that available in the D or P packages, and is shown to more than double the power capability of the D and P
packages.
NOTE:
The PowerPAD™is not directly connected to any leads of the package. However, it is
electrically and thermally connected to the substrate which is the ground of the device.
references
1. Power Supply Seminar SEM--1400 Topic 2: Design And Application Guide For High Speed MOSFET
Gate Drive Circuits, by Laszlo Balogh, Texas Instruments Literature No. SLUP133.
2. Application Note, Practical Considerations in High Performance MOSFET, IGBT and MCT Gate Drive
Circuits, by Bill Andreycak, Texas Instruments Literature No. SLUA105
3. Technical Brief, PowerPad Thermally Enhanced Package, Texas Instruments Literature No. SLMA002
4. Application Brief, PowerPAD Made Easy, Texas Instruments Literature No. SLMA004
PACKAGE OPTION ADDENDUM
www.ti.com 11-Jan-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
UCC27323D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC27323DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC27323DGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
UCC27323DGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
UCC27323DGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
UCC27323DGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
UCC27323DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC27323DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC27323P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
UCC27323PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
UCC27324D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC27324DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC27324DGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
UCC27324DGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
UCC27324DGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
UCC27324DGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
UCC27324DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC27324DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 11-Jan-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
UCC27324P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
UCC27324PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
UCC27325D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC27325DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC27325DGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
UCC27325DGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
UCC27325DGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
UCC27325DGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
UCC27325DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC27325DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC27325P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
UCC27325PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
UCC37323D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC37323DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC37323DGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
UCC37323DGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
UCC37323DGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
UCC37323DGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
UCC37323DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 11-Jan-2012
Addendum-Page 3
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
UCC37323DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC37323P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
UCC37323PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
UCC37324D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC37324DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC37324DGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
UCC37324DGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
UCC37324DGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
UCC37324DGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
UCC37324DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC37324DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC37324P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
UCC37324PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
UCC37325D ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC37325DG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC37325DGN ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
UCC37325DGNG4 ACTIVE MSOP-
PowerPAD DGN 8 80 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
UCC37325DGNR ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
UCC37325DGNRG4 ACTIVE MSOP-
PowerPAD DGN 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAUAGLevel-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 11-Jan-2012
Addendum-Page 4
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
UCC37325DR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC37325DRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
UCC37325P ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
UCC37325PE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UCC27324 :
•Automotive: UCC27324-Q1
PACKAGE OPTION ADDENDUM
www.ti.com 11-Jan-2012
Addendum-Page 5
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
UCC27323DGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
UCC27323DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UCC27324DGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
UCC27324DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UCC27325DGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
UCC27325DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UCC37323DGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
UCC37323DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UCC37324DGNR MSOP-
Power
PAD
DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
UCC37324DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UCC37325DGNR MSOP- DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Jan-2012
Pack Materials-Page 1
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
Power
PAD
UCC37325DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UCC27323DGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0
UCC27323DR SOIC D 8 2500 340.5 338.1 20.6
UCC27324DGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0
UCC27324DR SOIC D 8 2500 340.5 338.1 20.6
UCC27325DGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0
UCC27325DR SOIC D 8 2500 340.5 338.1 20.6
UCC37323DGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0
UCC37323DR SOIC D 8 2500 340.5 338.1 20.6
UCC37324DGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0
UCC37324DR SOIC D 8 2500 340.5 338.1 20.6
UCC37325DGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0
UCC37325DR SOIC D 8 2500 340.5 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Jan-2012
Pack Materials-Page 2
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