P0109-01
D1
D1
D1
G1
G2
SS
D2D2
D2
−VGS − Gate to Source V oltage − V
0
50
100
150
200
250
300
0 1 2 3 4 5 6
RD1D2(on) − On-State Resistance − mΩ
G006
ID1D2 = −1A
TJ = 125°CTJ = 25°C
Qg − Gate Charge − nC
0
1
2
3
4
5
6
0.0 0.5 1.0 1.5 2.0 2.5 3.0
−VGS − Gate to Source V oltage − V
G003
ID1D2 = −1A
VD1D2 = −10V
CSD75204W15
www.ti.com
SLPS221A –OCTOBER 2009–REVISED OCTOBER 2010
Dual P-Channel NexFET™ Power MOSFET
Check for Samples: CSD75204W15
1FEATURES PRODUCT SUMMARY
• Dual P-Ch MOSFETs VD1D2 Drain to Drain Voltage –20 V
• Common Source Configuration QgGate Charge Total (-4.5V) 2.8 nC
• Small Footprint 1.5-mm × 1.5-mm Qgd Gate Charge Gate to Drain 0.6 nC
• Gate-Source Voltage Clamp VGS = –1.8V 140 mΩ
RD1D2(on) Drain to Drain On Resistance VGS = –2.5V 105 mΩ
• Gate ESD Protection –3kV VGS = –4.5V 80 mΩ
• Pb Free VGS(th) Threshold Voltage –0.7 V
• RoHS Compliant
• Halogen Free ORDERING INFORMATION
Device Package Media Qty Ship
APPLICATIONS 1.5-mm × 1.5-mm 7-Inch Tape and
CSD75204W15 3000
• Battery Management Wafer Level Package Reel Reel
• Battery Protection ABSOLUTE MAXIMUM RATINGS
DESCRIPTION TA= 25°C unless otherwise stated VALUE UNIT
VD1D2 Drain to Drain Voltage –20 V
The device has been designed to deliver the lowest VGS Gate to Source Voltage -6 V
on resistance and gate charge in the smallest outline Continuous Drain to Drain Current,
possible with excellent thermal characteristics in an –3 A
TC= 25°C(1)
ultra low profile. Low on resistance coupled with the ID1D2 Pulsed Drain to Drain Current,
small footprint and low profile make the device ideal -28 A
TC= 25°C(2)
for battery operated space constrained applications. Continuous Source Pin Current -1.2 A
ISPulsed Source Pin Current(2) -15 A
Top View Continuous Gate Clamp Current -0.5 A
IGPulsed Gate Clamp Current(2) -7 A
PDPower Dissipation(1) 0.7 W
TJ, Operating Junction and Storage –55 to 150 °C
TSTG Temperature Range
(1) Per device, both sides in conduction
(2) Pulse duration 10ms, duty cycle ≤2%
RD1D2(on) vs VGS Gate Charge (Per MOSFET)
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2009–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
CSD75204W15
SLPS221A –OCTOBER 2009–REVISED OCTOBER 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ELECTRICAL CHARACTERISTICS
(TA= 25°C unless otherwise stated). Specifications and graphs are Per MOSFET unless otherwise stated. Drain to Drain
measurements are done with both MOSFETs in series (common source configuration.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Static Characteristics
BVD1D2 Drain to Drain Voltage VGS = 0V, ID1D2 = –250mA –20 V
BVGSS Gate to Source Voltage VD1D2 = 0V, IG= -250mA -6.1 -7.2 V
IDDS Drain to Drain Leakage Current VGS = 0V, VD1D2 = –16V –1 mA
IGSS Gate to Source Leakage Current VD1D2 = 0V, VGS = -6V –100 nA
VGS(th) Gate to Source Threshold Voltage VD1D2 = VGS, IDS = –250mA –0.5 –0.7 –0.9 V
VGS = –1.8V, ID1D2 = –1A 140 175 mΩ
RD1D2(on) Drain to Drain On Resistance VGS = –2.5V, ID1D2 = –1A 105 130 mΩ
VGS = –4.5V, ID1D2 = –1A 80 100 mΩ
gfs Transconductance VD1D2 = –10V, ID1D2 = –1A 5.3 S
Dynamic Characteristics
CISS Input Capacitance 315 410 pF
VGS = 0V, VD1D2 = –10V,
COSS Output Capacitance 128 165 pF
f = 1MHz
CRSS Reverse Transfer Capacitance 43 55 pF
QgGate Charge Total (–4.5V) 2.8 3.9 nC
Qgd Gate Charge - Gate to Drain 0.6 nC
VD1D2 = –10V,
ID1D2 = –1A
Qgs Gate Charge - Gate to Source 0.5 nC
Qg(th) Gate Charge at Vth 0.2 nC
QOSS Output Charge VD1D2 = –9.5V, VGS = 0V 2.2 nC
td(on) Turn On Delay Time 7.8 ns
trRise Time 6.7 ns
VD1D2 = –10V, VGS = –4.5V,
ID1D2 = –1A, RG= 30Ω
td(off) Turn Off Delay Time 45 ns
tfFall Time 26 ns
Diode Characteristics
VSD Diode Forward Voltage ID1D2 = –1A, VGS = 0V 0.75 1 V
Qrr Reverse Recovery Charge Vdd = –9.5V, IF= –1A, di/dt = 200A/ms 10.5 nC
trr Reverse Recovery Time Vdd = –9.5V, IF= –1A, di/dt = 200A/ms 23 ns
THERMAL CHARACTERISTICS
(TA= 25°C unless otherwise stated) PARAMETER MIN TYP MAX UNIT
Thermal Resistance Junction to Ambient(1) (2) 200 °C/W
RqJA Thermal Resistance Junction to Ambient (3) (2) 94 °C/W
(1) Device mounted on FR4 material with Minimum Cu mounting area.
(2) Measured with both devices biased in a parallel condition.
(3) Device mounted on FR4 material with 1-inch2of Cu (2oz).
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M0169-01
G1 S G2 D2 D1
M0170-01
G1 S G2 D2 D1
tP− PulseDuration − s
ZθJA−Normalized ThermalImpedance
0.0001 0.01 10 1k
0.0001
1
10
0.1
0.001
0.1 1001
G012
SinglePulse
0.01
0.02
0.05
0.1
0.3
0.5
0.01
0.001
DutyCycle=t1/t2
TypicalR =161 C/W(minCu)
T =P xZ xR
q
q q
JA
J JA JA
o
P
t1
t2
CSD75204W15
www.ti.com
SLPS221A –OCTOBER 2009–REVISED OCTOBER 2010
Max RqJA = 94°C/W Max RqJA = 200°C/W
when mounted on when mounted on
1 inch2(6.45 cm2) of minimum pad area of
2-oz. (0.071-mm thick) 2-oz. (0.071-mm thick)
Cu. Cu.
TYPICAL MOSFET CHARACTERISTICS
Graphs are Per MOSFET at TA= 25°C, unless stated otherwise. Drain to Drain measurements are done with both MOSFETs
in series (common source configuration).
Figure 1. Transient Thermal Impedance
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Product Folder Link(s): CSD75204W15
−VD1D2 − DraintoDrainVoltage − V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0
−ID1D2 − DraintoDrainCurrent − A
G001
VGS = −4.5V
VGS = −2V
VGS = −1.5V
VGS = −1.8V
VGS = −2.5V
−VGS − Gate to Source Voltage − V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.50 0.75 1.00 1.25 1.50 1.75
−ID1D2 − Drain to Drain Current − A
G002
VD1D2 = −5V
TJ = −55°C
TJ = 25°C
TJ = 125°C
Qg − Gate Charge − nC
0
1
2
3
4
5
6
0.0 0.5 1.0 1.5 2.0 2.5 3.0
−VGS − Gate to Source Voltage − V
G003
ID1D2 = −1A
VD1D2 = −10V
−VD1D2 − Drain to Drain Voltage − V
0
50
100
150
200
250
300
350
400
0 5 10 15 20
C − Capacitance − pF
G004
f = 1MHz
VGS = 0V
CRSS = CGD
COSS = CDS + CGD CISS = CGD + CGS
TJ − Junction Temperature − °C
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
−75 −25 25 75 125 175
−VGS(th) − Threshold V oltage − V
G005
ID1D2 = −250µA
−VGS − Gate to Source Voltage − V
0
50
100
150
200
250
300
0 1 2 3 4 5 6
RD1D2(on) − On-State Resistance − mΩ
G006
ID1D2 = −1A
TJ = 125°CTJ = 25°C
CSD75204W15
SLPS221A –OCTOBER 2009–REVISED OCTOBER 2010
www.ti.com
TYPICAL MOSFET CHARACTERISTICS (continued)
Graphs are Per MOSFET at TA= 25°C, unless stated otherwise. Drain to Drain measurements are done with both MOSFETs
in series (common source configuration).
Figure 2. Saturation Characteristics Figure 3. Transfer Characteristics
Figure 4. Gate Charge Figure 5. Capacitance
Figure 6. Threshold Voltage vs. Temperature Figure 7. On-State Resistance vs. Gate to Source Voltage
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TJ − Case Temperature − °C
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
−75 −25 25 75 125 175
Normalized On-State Resistance
G007
ID1D2 = −1A
VGS = −4.5V
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
−VSD − Source to Drain Voltage − V
−ISD − Source to Drain Current − A
G008
10
0.1
0.001
0.0001
0.01
1
TJ = 25°C
TJ = 125°C
−VD1D2 − DraintoDrainVoltage − V G009
100
10
0.01
1
−ID1D2−DraintoDrainCurrent −A
0.1
0.1 10 1001
AreaLimited
byRD1D2(on)
1ms
10ms
100ms
DC
SinglePulse
TypicalR =161 C/W(minCu)
qJA
o
TJ − Junction Temperature − °C
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
−50 −25 0 25 50 75 100 125 150 175
−ID1D2 − Drain to Drain Current − A
G011
CSD75204W15
www.ti.com
SLPS221A –OCTOBER 2009–REVISED OCTOBER 2010
TYPICAL MOSFET CHARACTERISTICS (continued)
Graphs are Per MOSFET at TA= 25°C, unless stated otherwise. Drain to Drain measurements are done with both MOSFETs
in series (common source configuration).
Figure 8. Normalized On-State Resistance vs. Temperature Figure 9. Typical Diode Forward Voltage
Figure 10. Maximum Safe Operating Area Figure 11. Maximum Drain Current vs. Temperature
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): CSD75204W15
M0171-01
SideView
0.62Max
Pin1
Mark
SeatingPlate
0.50
0.50
1.00
0.04
0.62Max
0.35 ±0.10
SolderBall
±0.075
Ø0.31
11
3 3
BottomViewTopView
FrontView
A
C
A
C
22
B B
1.50 +0.00
–0.08
1.50 +0.00
–0.08
CSD75204W15
SLPS221A –OCTOBER 2009–REVISED OCTOBER 2010
www.ti.com
MECHANICAL DATA
CSD75204W15 Package Dimensions
NOTE: All dimensions are in mm (unless otherwise specified)
Pinout
POSITION DESIGNATION
A1 Gate1
A2, A3, B3 Drain1
C1 Gate2
C2, C3, B2 Drain2
B1 Source Sense
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2.00±0.05 Ø1.50±0.10
1.75±0.10
Ø0.50±0.05
M0173-01
8.00 +0.30
–0.10
4.00±0.10
4.00±0.10
3.50±0.05
5°Max
5°Max
0.254±0.02
0.86±0.05
1.60±0.05
1.60±0.05
CSD75204W15
www.ti.com
SLPS221A –OCTOBER 2009–REVISED OCTOBER 2010
Land Pattern Recommendation
NOTE: All dimensions are in mm (unless otherwise specified)
Tape and Reel Information
NOTE: All dimensions are in mm (unless otherwise specified)
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): CSD75204W15
CSD75204W15
SLPS221A –OCTOBER 2009–REVISED OCTOBER 2010
www.ti.com
REVISION HISTORY
Changes from Original (October 2009) to Revision A Page
• Deleted the Package Marking Information sectiom .............................................................................................................. 7
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Product Folder Link(s): CSD75204W15
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