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FSA9285 -- MCPC-Compliant, USB-Port, Multimedia Switch with Auto-Detection Features Switch Type Switch Mechanism Accessory Detection USB USB Charging Audio VBAT Programmability ESD Package Ordering Information Description Audio, FS/HS-USB, Charging Programmable Switching with Available Interrupt Headsets with MIC and Send/End USB Data Cable USB Chargers (Car, CDP, DCP) USB On-The-Go (OTG) MCPC Specification Compliant Programmable Modes FS and HS 2.0 Compliant Battery Charging 1.2 Compliant Integrated FET, Charger Detect, OCP (1.45 A), OVP (6.5 V - 28.0 V) Left, Right, MIC (Negative Swing) Built-in Termination Resistors for Audio Pop Reduction 2.7 to 4.4 V 2 IC 15 kV IEC 61000-4-2 Air Gap 20-Lead, WLCSP (2.010 x 1.672 x 0.625 mm, 0.4 mm Pitch) FSA9285UCX Figure 1. (c) 2011 Fairchild Semiconductor Corporation FSA9285 * Rev 1.0.3 The FSA9285 is a high-performance multimedia switch featuring automatic switching and accessory detection for a USB port. The FSA9285 allows sharing of a common USB port to pass audio and USB data while simultaneously charging. In addition, the FSA9285 integrates detection of accessories such as headphones, headsets Mobile Computing Promotion Consortium (MCPC) with MIC and Send/End, car chargers, USB chargers, USB On-The-Go (OTG), and Accessory Charging Adapters (ACA) to use a common USB connector. The FSA9285 can be programmed for manual or automatic switching of USB data paths based on the accessory detected. With an integrated 28 V over-voltage and 1.45 A over-current protected FET, the FSA9285 integrates common USB protection functions for VBUS. Applications Mobile Phones, Portable Media Players Typical Application www.fairchildsemi.com FSA9285 -- MCPC Compliant USB Port Multimedia Switch with Auto-Detection September 2014 Phone Power Charger IC V BAT FSA9285 V BUS_OUT CHG_DETB USB Port MIC Audio Codec HS -USB Audio_R Audio_L DP_HOST2 DM_HOST2 DP_HOST1 HS -USB V BUS_IN Detection OCP, OVP 3:1 MUX and Charge Pump DM_CON Interrupt I2C Baseband Processor V DDIO DM_CON DP_CON DP_CON ID_CON DM_HOST1 INTB I2C_SCL I2C_SDA VBUS_IN Charger Detect Switch Control and I2C Slave GND ID_CON GND Float / Short Detect Resistance Detection Figure 2. Block Diagram Pin Configuration 1 2 3 4 GND DP_HOST2 DM_HOST2 VBAT A GND1 MIC I2C_SDA VDDIO B DM_HOST1 CHG_DETB I2C_SCL INTB C DP_HOST1 AUDIO_R AUDIO_L VBUS_OUT D ID_CON DP_CON DM_CON VBUS_IN E Figure 3. (c) 2011 Fairchild Semiconductor Corporation FSA9285 * Rev 1.0.3 Pin Assignments (Top-Through View) www.fairchildsemi.com 2 FSA9285-- MCPC Compliant USB Port Multimedia Switch with Auto-Detection Block Diagram Pin # Type Default State DP_HOST1 D1 Signal Path Open D+ signal switch path, dedicated USB port to be connected to the resident USB transceiver on the phone DM_HOST1 C1 Signal Path Open D- signal switch path, dedicated USB port to be connected to the resident USB transceiver on the phone DP_HOST2 A2 Signal Path Open D+ signal switch path, dedicated USB port to be connected to the resident USB transceiver on the phone DM_HOST2 A3 Signal Path Open D- signal switch path, dedicated USB port to be connected to the resident USB transceiver on the phone VBUS_IN E4 Power Path N/A Input voltage supply pin to be connected to the VBUS pin of the USB connector VBUS_OUT D4 Power Path N/A Output voltage supply pin to be connected to the source voltage pin on the charger IC CHG_DETB C2 Open-Drain Output Hi-Z Open-drain active LOW output, used to signal the charger IC that a charger has been attached Audio_R D2 Signal Path Open Right audio channel switch path from mobile phone audio CODEC Audio_L D3 Signal Path Open Left audio channel switch path from mobile phone audio CODEC MIC B2 Signal Path Open Connected to the mobile phone audio CODEC MIC input pin to complete the MIC switch path Name Description USB Interface Audio Interface Connector Interface ID_CON E1 Signal Path Open Connected to the USB connector ID pin and used for detecting accessories or button presses DP_CON E2 Signal Path Open Connected to the USB connector D+ pin; depending on the signaling mode, can be switched to DP_HOST1, DP_HOST2, or Audio_R pins DM_CON E3 Signal Path Open Connected to the USB connector D- pin; depending on the signaling mode, can switched to DM_HOST1, DM_HOST2, or Audio_L pins VBAT A4 Power Path N/A Input voltage supply pin to be connected to the mobile phone battery output or to an internal regulator on the phone VDDIO B4 Power Path N/A Baseband processor interface I/O supply pin GND1 B1 Ground N/A Ground GND A1 Ground N/A Ground I2C_SCL C3 Input Hi-Z I C serial clock signal to be connected to the phone-based I C master I2C_SDA B3 Open-Drain I/O Hi-Z I C serial data signal to be connected to the phone-based I C master INTB C4 CMOS Output LOW Interrupt active LOW output used to prompt the phone baseband 2 processor to read the I C register bits, indicates a change in ID_CON or VBUS_IN pin status or accessories' attach status Power Interface 2 I C Interface (c) 2011 Fairchild Semiconductor Corporation FSA9285 * Rev 1.0.3 2 2 2 2 www.fairchildsemi.com 3 FSA9285-- MCPC Compliant USB Port Multimedia Switch with Auto-Detection Pin Descriptions The FSA9285 is a USB port accessory-detection switch with integrated 28 V over-voltage and 1.45 A over-current protected 2 FET. Fully controlled using I C protocols, the FSA9285 enables all of the following to use a common connector (micro / mini USB 2.0 port): high-speed USB 2.0 standard downstream data port, stereo and mono audio headphones / headsets with or without a microphone, wired remote controller with optional send / end button, USB Charging Downstream Port (CDP) battery charger, USB Dedicated Charging Port (DCP) charger, and ANSI/CEA-936-A USB Car Kit charger. Detection of USB accessories utilizing a USB micro-B or microA/B connector is made possible by the presence of a standard resistor between the ID pin and ground of the accessory. Advanced modes manage wired remote-control sensing for audio accessories. The FSA9285 is designed to allow audio signals to swing below ground on the USB 2.0 port data lines. Internal power for the FSA9285 is automatically derived from either the battery voltage (VBAT) or the USB supply (VBUS_IN) for simplicity and long battery life. 2. I2C and Digital Core The FSA9285 enables factory-mode testing by defaulting to manual mode (EN_MAN_SW = 1) and defaulting the MANUAL SW register to USB switches DP_HOST1 / DM_HOST1 closed and the VBUS FET closed. In manual configuration, USB switches DP_HOST1 / DM_HOST1 only close when an accessory is attached that has an ID_CON resistance (ID_CON not floating) and / or valid VBUS voltage is present. The VBUS FET only closes when VBUS is valid. All switches remain open to protect the system when there is no accessory attached. This 2 default switch condition can be overridden with I C commands. Table 1. 2 2 The FSA9285 includes a full I C slave controller. The I C slave 2 fully complies with version 2.1 of the I C specifications. This block is designed for fast-mode, 400 kHz signals. The slave addresses are shown in Table 1. This block also includes the chip master controller. The chip controller monitors commands 2 sent to the FSA9285 via I C from the baseband processor and takes action. The digital core takes inputs from the various 2 functional blocks and the I C commands received from the mobile phone baseband processor and relays relevant status updates to the phone. 2 I C Slave Address Name Size (Bits) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Slave Address 8 0 1 0 0 1 0 1 Read / Write 2 Examples of I C write and read sequences are shown in Figure 4 and Figure 5, respectively. 8bits 8bits 8bits S Slave Address WR A Register Address K A Write Data A Write Data K+1 A Write Data K+2 A Note: A P Single byte read is initiated by master with P immediately following first data byte. Figure 4. 8bits S Slave Address 8bits 2 I C Write Sequence 8bits WR A Register Address K 8bits A S Slave Address RD A Read Data K A Read Data K+1 A Read Data K+N-1 NA P Single- or multi byte read executed from current register location (single-byte read is initiated by master with NA immediately following first data byte) Register address to read specified Note: Write Data K+N-1 If register is not specified, master begins reading from current register. In this case, only red bracketed sequence is needed. Figure 5. From Master to Slave From Slave to Master (c) 2011 Fairchild Semiconductor Corporation FSA9285 * Rev 1.0.3 S A 2 I C Read Sequence Start Condition Acknowledge (SDA Low) NA NOT Acknowledge (SDA High) WR Write=0 RD P Read =1 Stop Condition www.fairchildsemi.com 4 FSA9285-- MCPC Compliant USB Port Multimedia Switch with Auto-Detection 1. Functional Description 2 FSA9285 operates correctly without special power sequencing. When power is first applied, the device undergoes a hardware reset and all the registers are initialized to the default values shown in Table 6. All of the combinations of valid VBUS_IN and VBAT are shown in Table 2. When the device is reset, all I C registers are initialized to the default values shown in Table 6 (see Section 4 - Configuration). After reset or power up, the FSA9285 enters Standby Mode and is ready to detect accessories sensed on its V BUS_IN or ID_CON pins. As shown in Table 2, VBAT is used as the primary power supply. VDDIO is the dedicated baseband IO voltage and is only used for 2 I C interface and interrupt processing within the FSA9285. The device has three hardware reset mechanisms: Power-on reset caused by the initial rising edge of VBUS (if VBAT < 1.0 V) or rising edge of VBAT (If not VBUS_VALID) When VBAT is not valid, but VBUS_IN is; the FSA9285 powers off VBUS_IN. In this condition, the FSA9285 operates in its default state and is able to detect USB accessories and all chargers. The FSA9285 always turns on the VBUS FET upon any attach state with VBUS_Valid (unless Manual Mode is enabled with the VBUS FET switch state configured open). This allows charging of a dead battery when the rest of the system is not powered to configure the FSA9285. The falling edge of VDDIO I C reset: holding I2C_SDA and I2C_SCL LOW for 30ms Table 2. 2 The device has one software reset mechanism: Writing the ResetB bit (bit 6) in the Control register (02h) Power States Summary Valid VBUS_IN Valid VBAT NO NO Enabled Functionality Valid (1) VDDIO Power State Charging through FET NO NO Power Down NO NO YES NO YES NO Powered Off VBAT NO NO YES NO YES YES Powered Off VBAT NO YES YES YES NO NO Powered Off VBUS_IN Yes NO YES YES YES NO Powered Off VBAT YES NO YES YES NO YES Powered Off VBUS_IN YES YES YES YES YES Powered Off VBAT YES YES YES (2) (2) YES Processor Communication 2 (I C & Interrupts) Detection NO NO ILLEGAL STATE Notes: 1. VDDIO is expected to be the same supply used by the baseband I/Os. 2. This is not a typical state. Both VBAT and VDDIO are typically provided from the same regulator. 4. Configuration The FSA9285 must be configured for operation upon reset. There are several options to note about reset configuration: 1. The Interrupt Mask bit is set and must be cleared for the FSA9285 to interrupt the host processor. 2. Upon hardware reset, the USB Path DP_HOST1 / DM_HOST1 switches are configured to close when an accessory is attached (with an ID_CON resistance or valid VBUS voltage) to support production programming. These 2 switches may be opened using I C commands. 3. 4. To enable manual configuration of the USB switches, the EN_MAN_SW bit must be set to 1. The switch settings then override any automatic settings (this assumes that the USB discovery state machine has completed its operations and a device is attached). For the weak (or dead) battery case to work reliably, VDDIO must be removed (to reset the FSA9285 state) whenever the battery is too low for reliable 2 I C communication. 5. Performing a software reset sets all I C Register Map (Table 6) registers to default, with the exception of the Control register, Manual SW register, and the Manual CHG_CTRL register. These registers are only reset to default on a hardware reset. If MIC Mode is going to be used, it is recommended that MIC_OVP_EN bit be set to 1 at reset. (c) 2011 Fairchild Semiconductor Corporation FSA9285 * Rev 1.0.3 2 www.fairchildsemi.com 5 FSA9285-- MCPC Compliant USB Port Multimedia Switch with Auto-Detection 3. Power-Up Initialization and Reset The baseband processor recognizes interrupt signals by observing the INTB signal, which is active LOW. Interrupts are masked upon reset via the INT Mask register bit (bit 0 of 2 Control register, address 02h in Table 6 of the I C register map) and INTB pin defaults HIGH. After the INT Mask bit is cleared by the baseband processor, the INTB pin is generally driven HIGH (INTB is not an open-drain output) in preparation for a future interrupt. The INTB remains HIGH until the INTB mask is 2 cleared. If the Interrupt Mask bit in the I C Control register is written LOW when an interruptible event occurs, INTB transitions LOW and returns HIGH when the processor reads the Interrupt register at addresses 03h. 6. Analog Switch Descriptions The FSA9285 has a three-port data switch, providing routing capability to two data ports and one audio port. The two data switches are high bandwidth to provide high-speed USB 2.0 "eye" compliance. These switches also operate full-swing for full-speed USB and UART signals up to 4.4 V. The high-performance negative-swing-capable audio switch utilizes a termination resistor for audio pop reduction. The audio configuration also provides for routing a microphone signal from a headset. The MIC signals can be routed to either the VBUS_IN pin for stereo audio configurations or the DP_CON pin for mono audio configurations that also allow simultaneous charging over the VBUS line. 7. Accessory Detection In Standby Mode, after power-up or reset, the FSA9285 monitors the VBUS_IN and ID_CON pins for any connectivity using very low power (see "Battery Supply Standby Mode Current" in the Switch Path DC Electrical Characteristics section). To minimize standby power, many functional blocks are powered down until an accessory attach is detected. The VBUS_IN detection recognizes if the voltage on VBUS_IN is within the valid range (>4.0 V). For resistance to GND on the ID_CON pin, the FSA9285 measures voltage with an injected current to determine this resistance. All accessories attached or detached are reported to the processor via the Interrupt register. Any changes of resistance on the ID_CON pin are reported as a Resistor_Change interrupt. Additional information about the accessory is reported in the Device Type, Resistor Code, and Status registers. For USB accessories without an ID_CON resistance, a VBUS_Valid Change interrupt is reported to signal an attach or detach condition. Status of VBUS_Valid and ID_CON resistance is always available after any interrupt. The USB detection flow is show in Figure 6. Note that the INTB Mask bit in the Control register must be cleared after a reset or (c) 2011 Fairchild Semiconductor Corporation FSA9285 * Rev 1.0.3 power-up before interrupts can be signaled by the FSA9285. Individual Interrupt Masks bits can be enabled by writing the Interrupt Mask register (see Table 6). ID_CON resistor detection is accomplished in a little more than three times the "Resistor Detection Time," where Resistor Detection Time bits are programmable in the Timing Set register. The FSA9285 is designed to allow up to 1nF capacitance on the ID_CON pin. ID_CON is short-circuit protected from a faulty resistor or an accidental short where the current is limited to 5mA sourced by the FSA9285. The detection of a VBUS_IN goes through the USB detection flow only once. VBUS_IN must be removed before the USB detection state machine reverts to its initial state. After an initial attach, the FSA9285 continuously monitors the ID pin for changes and reports those changes to the baseband processor. To provide the fastest response for changes in button checking after initial attach, the FSA9285 indicates a change in ID_CON resistor after two samples are taken instead of the three consecutive samples taken on initial attach. To save power, the resistor detection block can be disabled after an initial attach with the ID_DIS bit in the Control register. The resistor detection block is normally disabled when no ID_CON resistance is present (ID_CON floating) to save power. The condition of ID_FLOAT continues to be monitored regardless of the ID_DIS setting. Whenever a resistance is measured on ID_CON, the USB discovery state machine halts after completion of its current state and the ID_CON state machine continues for accessory detection. The only exception is when an ACA RID-A accessory is detected. In this case, the USB discovery state machine is used to differentiate between a docking station and a powered A-device attached to a docking station (per USB Battery Charging Specification 1.2). If the EN_MAN_SW bit is set on attach, FSA9285 configures the switches to the state in the MANUAL SW register. Upon the removal of any accessory, the FSA9285 detects and indicates a change in ID_CON resistance (regardless of ID_DIS bit setting), a removal of VBUS_IN, or both. The FSA9285 automatically opens all switches (and VBUS FET) on detach (ID_FLOAT and VBUS not valid), even if the FSA9285 is set to Manual Switching Mode. For the weak battery case, the FSA9285 needs to be in Automatic Switching Mode. Should the processor NOT be able to respond to INTB, FSA9285 must be placed in Automatic Switching Mode explicitly or VDDIO must be removed, resetting the FSA9285 state to its default values. Note: If the FSA9285 is to be used in automatic switching mode (EN_MAN_SW = 0) then the Manual SW register must be configured for all switches OPEN). www.fairchildsemi.com 6 FSA9285-- MCPC Compliant USB Port Multimedia Switch with Auto-Detection 5. Interrupt Operation Check ID No Yes VBUS Valid? ID Float? Yes No Perform DCD ADC Change ID =RID_A ? Yes Charger? No Yes ID =200k /442 k ACA_A Dock Car Kit1/2 Yes No No DCP CDP SDP No ID =ACA RID-B ID =ACA RID-C ACA_B ACA_C Other Charger? Yes DP/DM Shorted? Figure 6. Accessory Discovery State Machine Flow Diagram Note: 3. Figure 6 illustrates operation with a valid VDDIO supply voltage. Figure 6 does not illustrate Dead Battery Provision (DBP) See Section 9 for details. (c) 2011 Fairchild Semiconductor Corporation FSA9285 * Rev 1.0.3 www.fairchildsemi.com 7 FSA9285-- MCPC Compliant USB Port Multimedia Switch with Auto-Detection VBUS and ID Detection State Machines Operate in Parallel Check VBUS ID_CON Resistor Identification ID_CON Resistance to GND Resistor (4) Code Min. 22 0 20 19000 19 18 Auto Switch USB Switches Unit Accessory Detected 18 OTG 20000 21000 Resistor 20 k 22800 24000 25200 Resistor 24 k 27265 28700 30135 Resistor 28.7 k 17 34675 36500 36865 16 39798 40200 40602 Resistor 40.2 k 15 44650 47000 49350 MCPC Send/End 14 55638 56200 56762 Resistor 56.2 k 13 64600 68000 71400 12 80275 84500 88725 Resistor 84.5 k 11 96900 102000 107100 Phone Power Device 10 117800 124000 130200 9 148500 150000 151500 Resistor 150 k 8 171000 180000 183600 MCPC Maintenance 7 198000 200000 202000 Car Kit Type-1 Charger 6 229680 232000 234320 5 272650 287000 301350 MCPC Mode 1 4 370500 390000 401700 MCPC Reserved 3 437580 442000 446420 2 529150 557000 584850 MCPC Mode 3 1 757150 797000 836850 MCPC Mode 2 0 970000 Open Typ. Max. YES YES YES (5) ACA RID-C (5) ACA RID-B (5) ACA RID-A (5) Resistor 232 k Car Kit Type-2 Charger (5) (6) Float Notes: 4. The resistor code values are reported in the Resistor Code register whenever a valid resistor code value changes. 5. See Table 4 for details, additional requirements may be applicable for detection. 6. Resistance 970 k status bit /ID_FLOAT=0. (c) 2011 Fairchild Semiconductor Corporation FSA9285 * Rev 1.0.3 www.fairchildsemi.com 8 FSA9285-- MCPC Compliant USB Port Multimedia Switch with Auto-Detection Table 3. The FSA9285 can detect the USB 2.0 port types summarized in Table 4. VBUS must be present to detect these accessories. For SDP, CDP, and ACA USB accessories; the following pin mapping is automatically configured: DP_HOST1 = DP_CON (If EN_MAN_SW = 0) DM_HOST1 = DM_CON (If EN_MAN_SW = 0) VBUS_OUT = VBUS_IN The FSA9285 allows factory testing or programming through the DP_HOST1 and DM_HOST1 switches by closing these switches when a USB cable with an ID resistance or VBUS voltage is detected. Table 4. For USB chargers that do not automatically close USB switches, the switches can be closed manually through the Manual Switch register when EN_MAN_SW is enabled. Whenever VBUS_IN becomes valid, the integrated 28 V charger FET is closed (unless EN_MAN_SW = 1 and Manual SW[1:0]11) and VBUS_IN voltage is continuously monitored to incorporate Over-Voltage Protection (OVP). If the attached device is recognized as one of the chargers in Table 4 (excluding SDP), the CHG_DETB pin goes LOW to send a signal to the charger IC, external to the FSA9285, to increase the charging current to the maximum allowed level by the OverCurrent Protection (OCP) trigger (see the Switch Path DC Electrical Characteristics section). VBUS_OUT must be valid 10ms before sourcing greater than 100 mA. ID_CON and VBUS Detection for USB and Car Kit Devices Resistor (7) Code USB (8) CHG_DETB (8) Switches VBUS_IN 00111 5V Open 00011 5V 00000 ID_CON Resistance to GND (k) Accessory Detected Min. Typ. Max. Asserted 198 200 202 Car Kit Type-1 Charger Open Asserted 437.58 442.00 446.42 Car Kit Type-2 Charger 5V Open Asserted 3 M Open Open USB Dedicated Charging Port, Travel (9) Adapter or Dedicated Charger (DCP) 00000 5V Auto_close Asserted 3 M Open Open USB Charging Downstream Port (CDP) 00000 5V Auto_close Not Asserted 3 M Open Open USB Standard Downstream Port (SDP) 10001 5V Auto_close Asserted 34.675 36.500 36.865 ACA RID-C 01101 5V Auto_close Asserted 64.6 68.0 71.4 ACA RID-B 01010 5V Auto_close Asserted 117.8 124.0 130.2 ACA RID-A (9) (9) Notes: 7. The resistor code values are reported in the Resistor Code register, independent of the state of USB switches or VBUS_IN. 8. In Table 4, switches auto-close and CHG_DETB are asserted only if VBUS_VALID. 9. The FSA9285 follows the Battery Charging 1.2 specification, which uses DP_CON and DM_CON to determine the USB accessory attached. Refer to Battery Charging 1.2 Specification for details. (c) 2011 Fairchild Semiconductor Corporation FSA9285 * Rev 1.0.3 www.fairchildsemi.com 9 FSA9285-- MCPC Compliant USB Port Multimedia Switch with Auto-Detection 8. USB Port and Charger Detection Since VBUS charging power connects through it, the FSA9285 must automatically turn on the VBUS FET to allow the mobile device to charge after shutdown due to a dead battery. When detecting that VBUS is valid, the FSA9285 automatically turns on the VBUS FET after BC1.2 charger detection is complete. Turning on at this time allows the DP / DM switches to turn on at the same time as the VBUS FET. If the FSA9285 detects a USB port (SDP, CDP, or DCP) when VBAT and VDDIO are not valid, it applies 0.6V to DP_CON in accordance with the USB BC1.2 Dead Battery Provision. The FSA9285 automatically removes the 0.6V on DP_CON upon detach of an accessory, when VDDIO returns to a valid voltage, or when VBAT > VBAT_TH. If the mobile device should manually assert the 0.6V on DP_CON, it can do so using the ASSERT_D+ bit (bit 2) of the Manual CHG_CTRL register (14h); VBUS must be valid to do so. 10. Over-Voltage Protection (OVP) and OverCurrent Protection (OCP) When VBUS_IN is less than nominally 6.5V, the FSA9285 allows the VBUS_IN supply to enter the chip-power select voltage regulator block. For VBUS_IN greater than nominally 6.5V, the input is disconnected, protecting the FSA9285 from excess voltage. Upon entering Shutdown Mode, the OVP bit in the Interrupt register is set HIGH (to reflect a change in OVP state) and an interrupt is sent to the baseband. The OVP Status register is also written HIGH to indicate that an OVP condition is present. In Shutdown Mode, the FSA9285 continually monitors VBUS and exits Shutdown Mode when VBUS drops to (c) 2011 Fairchild Semiconductor Corporation FSA9285 * Rev 1.0.3 below 6.5V or it senses an accessory detach. Upon exiting an OVP condition, another OVP interrupt is triggered (reflecting a change in OVP state) and the OVP status bit is cleared (indicating an OVP condition is not present). The Over-Current Protection (OCP) feature limits current through the charger FET to nominally 1.45 A. OCP is only implemented when VBUS_IN is provided by the attached accessory. The FSA9285 senses an over-current event, opens (turns off) the VBUS FET, and reports this to the baseband by asserting the OCP bit (to reflect a change in OCP state) in the Interrupt register. When in an OCP state, the OCP status bit is written HIGH. While the OCP condition is present, the FSA9285 continually monitors the VBUS current and exits Shutdown Mode when the VBUS current drops below nominally 1.45 A or it senses an accessory detach. Upon exiting OCP state, the OCP Interrupt bit is again written HIGH, indicating a change in OCP state and the OCP Status bit is written LOW, indicating an OCP state is not present. 11. Audio Accessory Detection After an audio device is attached and a change in ID_CON resistance is detected (if ID_DIS=0), the FSA9285 asserts an interrupt and the baseband processor can read the Resistor Code register to determine the ID_CON resistance change to detect if a key, such as MCPC SEND / END, was pressed. For powered audio accessories with VBUS present, the FSA9285 detects when VBUS is valid and interrupts the baseband processor. The baseband processor must manually control the FSA9285 switches for proper functionality. MIC can be switched to either VBUS or DP_CON through the Manual SW register, allowing more flexibility. www.fairchildsemi.com 10 FSA9285-- MCPC Compliant USB Port Multimedia Switch with Auto-Detection 9. Dead Battery Provision Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure t o stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit -0.5 6.0 V -0.5 28.0 V USB -1.0 6.0 Stereo/Mono Audio Path Active -2.0 6.0 All Other Channels -0.5 6.0 VBAT/VDDIO Supply Voltage from Battery / Baseband VBUS_IN VSW IIK ICHG ISW ISWPEAK Supply Voltage from Micro-USB Connector Switch I/O Voltage Input Clamp Diode Current -50 Charger Detect CHG_DETB Pin Current Sink Capability Switch I/O Current (Continuous) Peak Switch Current (Pulsed at 1ms Duration, <10% Duty Cycle) mA 30 USB 50 Audio 60 mA mA All Other Channels 50 USB 150 mA Audio 150 mA Charger FET All Other Channels TSTG V Storage Temperature Range -65 2 A 150 mA +150 C TJ Maximum Junction Temperature +150 C TL Lead Temperature (Soldering, 10 Seconds) +260 C ESD USB Connector Pins IEC 61000-4-2 System Level (DP_CON, DM_CON, VBUS_IN, ID_CON) to GND Air Gap 15000 Contact 8000 Human Body Model, JEDEC JESD22-A114 All Pins 5000 Charged Device Model, JEDEC JESD22-C101 All Pins 1500 V 13. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Min. Typ. Max. Unit Battery Supply Voltage 2.7 3.8 4.4 V VBAT_TH Battery Supply Voltage Threshold for Weak / Dead Battery 2.7 3.0 3.3 V VBUS_IN Supply Voltage from VBUS_IN Pin 4.0 5.5 V VDDIO Processor Supply Voltage 1.7 3.6 V USB Path Active 0 4.4 VSW Switch I/O Voltage Audio Path Active -1.5 3.0 0 5.0 VBAT Parameter All Other Pins IDCAP TA Capacitive Load on ID_CON Pin for Reliable Accessory Detection Operating Temperature (c) 2011 Fairchild Semiconductor Corporation FSA9285 * Rev 1.0.3 -40 V 1.0 nF +85 C www.fairchildsemi.com 11 FSA9285-- MCPC Compliant USB Port Multimedia Switch with Auto-Detection 12. Absolute Maximum Ratings All typical values are at TA=25C unless otherwise specified. Symbol Parameter VBAT (V) Condition TA = -40 to +85C Min. Typ. Unit Max. Host Interface Pins (INTB, CHG-DETB) VOH Output High Voltage VOL Output Low Voltage (10) 3.0 to 4.4 IOH=2 mA 0.7 x VDDIO V 3.0 to 4.4 IOL=8 mA 0.4 V 0.3 x VDDIO V 2 I C Interface Pins - Fast Mode (I2C_SDA, I2C_SCL) VIL Low-Level Input Voltage 3.0 to 4.4 VIH High-Level Input Voltage 3.0 to 4.4 II2C Input Current of I2C_SDA and I2C_SCL 3.0 to 4.4 Pins, Input Voltage 0.26 V to 2.34 V 0.7 x VDDIO V -10 10 A 10 A 0.100 A Switch Off Characteristics IOFF Power-Off Leakage Current 0 All Data Ports Except Audio & MIC, VSW=4.4 V All Ports Except Audio & MIC, I/O Pins=0.3 V, 4.1 V, or Floating INO(OFF) Off Leakage Current 4.4 IIDSHRT Short-Circuit Current 3.0 to 4.4 -0.100 0.001 Current Limit if ID_CON=0V 5 VD+/D-=0 V, 0.4 V, ION=8 mA 8 10 VD+/D-=0V, 3.6 V, ION=8 mA 11 17 6.5 6.9 V mA USB Switch (DP_HOSTn, DM_HOSTn) ON Paths RON USB Switch Paths On Resistance (11,12) 3.0 to 4.4 Charging FET ON Path VOVP Over-Voltage Protection (OVP) Threshold Voltage RON Charging FET On Resistance IOCP Over-Current Protection (OCP) Threshold Current (11,12) 3.0 to 4.4 3.0 to 4.4 6.2 VBUS_IN=4.2 V-5.0 V, ION=1 A 3.0 to 4.4 VBUS_IN=5.2 V m 200 1.2 1.65 A Audio_R / Audio_L Switch ON Paths RON RFLAT RTERM Audio Switch On Resistance Audio RON Flatness (11,12) (11,13) 3.0 to 4.4 3.0 to 4.4 VL/R=-0.8 V, 0.8 V, ION=30 mA, f=0-470 kHz 3.5 VL/R=-1.5 V, 1.5 V, ION=30 mA, f=0-470 kHz 4.0 VL/R=-0.8 V, 0.8V, ION=30 mA, f=0-470 kHz 0.1 VL/R=-1.5V, 1.5V, ION=30 mA, f=0-470 kHz 0.2 Internal Termination Resistors 1.5 k Continued on the following page... (c) 2011 Fairchild Semiconductor Corporation FSA9285 * Rev 1.0.3 www.fairchildsemi.com 12 FSA9285-- MCPC Compliant USB Port Multimedia Switch with Auto-Detection 14. Switch Path DC Electrical Characteristics Switch Path DC Electrical Characteristics (Continued) All typical values are at TA=25C unless otherwise specified. Symbol Parameter VBAT (V) Condition TA = -40 to +85C Min. Typ. Max. Unit MIC Switch ON Paths RON (11,12) MIC Path ON Resistance 3.0 to 4.4 MICOVP Over-Voltage Protection (OVP) Threshold Voltage with MIC on (14) VBUS_IN Total Current Consumption IBAT MIC Connected to VBUS_IN, VSW=0 V, 2.8 V, ION=30 mA 40 MIC Connected to DP_CON, VSW=0 V, 2.8 V, ION=30 mA 40 MIC Connected to VBUS_IN Entering OVP 2.80 3.35 V (16) Battery Supply Standby Mode Current No Accessory Attached (ID_CON Floating) Average Battery Supply Standby Mode Current with Accessory Attached (ID_CON Not Floating) VBUS Floating VBUS Floating 3.0 to 4.4 VBUS = 0 V ID_DIS=1 VBUS = 5 V ID_DIS=1 10 15 35 50 100 (16) 150 A (16) Notes: 10. Does not apply to the CHG_DETB pin because it is open drain. 11. Limits based on Electrical Characterization data. 12. On resistance is the voltage drop between the two terminals at the indicated current through the switch. 13. Flatness is the difference between the maximum and minimum values of on resistance over the specified range of conditions. 14. The MIC bias applied should not exceed 2.8 V. 15. VDDIO of either 0 V or in the valid range of 1.7 V to 3.6 V. 16. Typically the battery charges from VBUS. 15. Capacitance Symbol CONUSB CI COFF Parameter VBAT (V) DP_CON, DM_CON On Capacitance (USB Mode, Both HOST1 and HOST2) 3.8 Capacitance for Each I/O Pin Off Capacitance (HOST1 and HOST2) (c) 2011 Fairchild Semiconductor Corporation FSA9285 * Rev 1.0.3 Condition VBIAS=0.2 V, f=1 MHz TA = -40 to +85C Min. Typ. Max. Unit 8 pF 3.8 2 pF 3.8 2 pF www.fairchildsemi.com 13 FSA9285-- MCPC Compliant USB Port Multimedia Switch with Auto-Detection 14. Symbol fSCL tHD;STA Fast Mode Parameter Min. Max. Unit 0 400 kHz SCL Clock Frequency Hold Time (Repeated) START Condition 0.6 s tLOW LOW Period of SCL Clock 1.3 s tHIGH HIGH Period of SCL Clock 0.6 s tSU;STA Set-up Time for Repeated START Condition 0.6 tHD;DAT Data Hold Time tSU;DAT (17) Data Set-up Time 0.9 s 100 tr Rise Time of SDA and SCL Signals tf Fall Time of SDA and SCL Signals tSU;STO s 0 (18) (18) ns 20+0.1Cb (17) 300 ns 20+0.1Cb (17) 300 ns Set-up Time for STOP Condition 0.6 s tBUF BUS-Free Time between STOP and START Conditions 1.3 s tSP Pulse Width of Spikes that Must Be Suppressed by the Input Filter 0 50 ns Notes: 17. Cb equals the total capacitance of one BUS line in pf. If mixed with high-speed devices; faster fall times are allowed, according 2 to the I C Bus specification. 2 (R) 2 18. A fast-mode I C-Bus device can be used in a Standard-Mode I C-Bus system, but the requirement that tSU;DAT 250 ns must be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t r_max + tSU;DAT = 1000 + 250 = 1250 ns before 2 the SCL line is released (according to the Standard-Mode I C Bus specification). Figure 7. Table 5. 2 Definition of Timing for Full-Speed Mode Devices on the I C Bus (R) 2 I C Slave Address Name Size (Bits) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Slave Address 8 0 1 0 0 1 0 1 R/W (c) 2011 Fairchild Semiconductor Corporation FSA9285 * Rev 1.0.3 www.fairchildsemi.com 14 FSA9285-- MCPC Compliant USB Port Multimedia Switch with Auto-Detection 16. I2C AC Electrical Characteristics All typical values are for VBAT=3.8 V at TA=25C unless otherwise specified. Symbol Parameter Xtalk Active Channel Crosstalk DP_CON to DM_CON OIRR Off Isolation Conditions TA = -40 to +85C Min. Typ. Audio Mode f=20 kHz, RT=32 , CL=0 pF -90 USB Mode f=1 MHz, RT=50 , CL=0 pF -60 Audio Mode f=20 kHz, RT=32 , CL=0 pF -100 USB Mode f=1 MHz, RT=50 , CL=0 pF -60 Max. Unit dB dB PSRR Power Supply Rejection Ratio, MIC on VBUS_IN Power Supply Noise 300MvPP, f=217 Hz Sine Wave -100 dB THD Total Harmonic Distortion (Audio Path) 20 Hz to 20 kHz, RL=32/16 , Input Signal Range -1.5 V, 1.5 V 0.07 % tSK(P) Skew of Opposite Transitions of the Same Output (USB Mode) tr=tf=750 ps (10-90%) at 240 MHz, CL=0 pF, RL=50 35 ps tI2CRST Time When I2C_SDA and I2C_SCL Both LOW to Cause Reset See Figure 8 tSDPDET Time from VBUS_IN Valid to VBUS_OUT Valid with See Figure 10 Charger FET Closed and USB Switches Closed for USB Standard Downstream Port 120 ms tCHGOUT Time from VBUS_IN Valid to VBUS_OUT Valid with Charger FET Closed for Both USB Charging See Figure 11 Ports (CDP and DCP) 160 ms tCARKIT Time from VBUS_IN Valid to Car Kit Type-1 or Type-2 Charger Detected See Figure 12 140 ms tIDDET Time from ID_CON Not Floating to INTB LOW to Signal Accessory Attached that is ID_CON Resistance-Based Only (VBUS_IN Not Valid, Default timing configuration) See Figure 13 150 ms tBC11 Timeout for Data Contact During DCD Check (c) 2011 Fairchild Semiconductor Corporation FSA9285 * Rev 1.0.3 30 300 ms 600 900 ms www.fairchildsemi.com 15 FSA9285-- MCPC Compliant USB Port Multimedia Switch with Auto-Detection 17. Switch Path AC Electrical Characteristics FSA9285-- MCPC Compliant USB Port Multimedia Switch with Auto-Detection 18. Timing Diagrams VBAT I2C_SDA 30ms 30ms Internal Reset Time Standby Mode 400s 400s Figure 8. 2 I C Reset Mode Timing VBAT VDDIO INT Mask Clear INT_Mask INTB INT Mask written via I2C command Figure 9. INT Event INT Read INT Mask to INTB Interrupt Timing Diagram Charger FET Closed USB Switches Closed VBUS >4.0V VBUS_IN XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX FLOAT FLOAT ID Resistance VBUS_OUT 120ms Open USB Switch State Figure 10. (c) 2011 Fairchild Semiconductor Corporation FSA9285 * Rev 1.0.3 Closed 120ms USB Standard Downstream Port Attach Timing (19) www.fairchildsemi.com 16 VBUS Voltage XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX FLOAT FLOAT ID Resistance VBUS_OUT 160ms Open USB Switch State Closed CHG_DETB Pin INTB Pin Charger Detection Time 160ms Figure 11. USB Dedicated Charging Port (DCP) or Charging Downstream Port (CDP) Attach Timing (19) Charger FET Closed, USB Switches Closed, and INTB and CHG_DETB Asserted VBUS >4.0V VBUS Voltage FLOAT XXXXXXXX ID Resistance 140ms VBUS_Out Open BB Configures Switches Closed USB Switch State Closed CHG_DETB Pin INTB Pin VBUS Detection Time 140ms Figure 12. Car Kit Type-1 and Type-2 Attach Timing Accessory Attached INTB Asserted BB Reads INTB FLOAT XXXXXX ID Resistance Open BB Configures Switches Closed USB Switch State Closed INTB Pin 150ms BB Read and Clear Figure 13. ID-Based Accessories, No VBUS_IN Attach Timing (20) Notes: 19. USB Switch State timing is based on Automatic Switching mode (EN_MAN_SW = 0). Automatic switching excludes DCP. 20. ID_CON resistance detection based on default Timing Set and Applications register values and on initial ID_CON accessory attach only (50 ms Resistor Detection Time with 3 ID checks on initial attach = 150 ms typical detection time). (c) 2011 Fairchild Semiconductor Corporation FSA9285 * Rev 1.0.3 www.fairchildsemi.com 17 FSA9285-- MCPC Compliant USB Port Multimedia Switch with Auto-Detection Charger FET Closed, USB Switches Closed, and INTB and CHG_DETB Asserted VBUS >4.0V 2 Table 6. Address I C Register Map Reset Value Register Type 01H Device ID R Bit 7 Bit 6 00010000 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Version ID Bit 0 Do Not Use 02H Control R/W 11010001 DCD Timeout EN 03H Interrupt R/C 00000000 Do Not Use OCP Change OVP Change MIC_OVP Change Resistor Code Change VBUS_Valid Change BC1.2_Complete Do Not Use 05H Interrupt Mask R/W 00000000 Do Not Use OCP OVP MIC_OVP Resistor Code Change VBUS_Valid BC1.2_Complete Do Not Use 07H Resistor Code R 00000000 Do Not Use Do Not Use Do Not Use 08H Timing Set R/W 00000000 09H Status R 00000000 0AH Device Type R 00000000 RESETB ID_DIS EN_MAN_SW Do Not Use Do Not Use Do Not Use INT Mask Resistor Code Do Not Use ID_SHORT Do Not Use OCP Do Not Use Resistor Detection Time OVP MIC_OVP Dock 0BH DAC SAR R 00000000 13H Manual SW R/W 00100111 D- Switching 14H Manual CHG_CTRL R/W 00000000 Do Not Use Do Not Use Do Not Use 1BH Applications1 R/W X0001000 Do Not Use Do Not Use Do Not Use 1CH Applications2 R/W XXXX0101 Do Not Use Do Not Use Do Not Use Do Not Use /ID_FLOAT VBUS_Valid Do Not Use USB Dedicated Charging Port (DCP) BC1.2_Active DCD USB Charging USB Standard Downstream Port Downstream (CDP) Port (SDP) DAC SAR Value D+ Switching Assert CHG_DETB MIC_OVP_EN VBUS Switching Assert_D+ # of Consecutive ID Matches for Attach Do Not Use # ID Checks for Resistor Code Change Do Not Use Do Not Use Do Not Use Max. Capacitance on ID Table 7. Device ID Address: 01H Reset Value: 00010000 Type: Read Bit # Name Size (Bits) 7:3 Version ID 5 Rev 0.0=00010 2:0 Do Not Use 3 Do not use (c) 2011 Fairchild Semiconductor Corporation FSA9285 * Rev 1.0.3 Description www.fairchildsemi.com 18 FSA9285-- MCPC Compliant USB Port Multimedia Switch with Auto-Detection 19. Bit Definitions Bit # Name Size (Bits) 7 DCDTimeout_EN 1 1: DCD timeout is enabled. 0: DCD timeout is disabled. Description 6 RESETB 1 1: Do nothing. 0: Reset FSA9285 - resets all of FSA9285 except the Control register (02H), Manual SW (13H), and Manual CHG_CTRL(14H). Note: This bit is momentarily set to 0 on a write. It immediately reverts to 1. 5 ID_DIS 1 1: ID_CON resistor detection is disabled after a resistance is detected on ID_CON. 0: ID_CON resistor detection is enabled after a resistance is detected on ID_CON. Note: The FSA9285 continues to monitor for an ID_FLOAT condition. 4 EN_MAN_SW 1 1: Configure switches based on Manual SW register settings. 0: Use only defined automatic switch settings. This bit needs to be cleared in case of a weak battery explicitly or the device must be defaulted via a VDDIO reset for the dead battery case to operate properly. 3 Do Not Use 1 Do not use. 2 Do Not Use 1 Do not use. 1 Do Not Use 1 Do not use. 1 1: Mask Interrupt - Do not interrupt baseband processor when a bit is set in the Interrupt register. 0: Unmask Interrupt - Interrupt baseband processor if any bit is set in the Interrupt register. 0 INT Mask Table 9. Interrupt Address: 03H Reset Value: 00000000 Type: Read/Clear Bit # Name Size (Bits) 7 Do Not Use 1 N/A 6 OCP Change 1 1: OCP state changed. 0: OCP state has not changed. 5 OVP Change 1 1: OVP state changed. 0: OVP state has not changed. 4 MIC_OVP Change 1 1: MIC OVP state changed. 0: MIC OVP state not changed. 3 Resistor Code Change 1 1: Resistor Code value changed. 0: Resistor Code value has not changed. Note: This interrupt is disabled when ID_DIS=1. The FSA9285 interrupts if transitioning from a non-zero Resistor Code to a Resistor Code=zero (ID_CON floating). 2 VBUS_Valid Change 1 1: VBUS_Valid state changed. 0: VBUS_Valid state has not changed. 1 BC1.2_Complete 1 1: BC1.2 charger detection complete. 0: No change in BC1.2 charger detection status. 0 Do Not Use 1 N/A (c) 2011 Fairchild Semiconductor Corporation FSA9285 * Rev 1.0.3 Description www.fairchildsemi.com 19 FSA9285-- MCPC Compliant USB Port Multimedia Switch with Auto-Detection Table 8. Control Address: 02H Reset Value: 11010001 Type: Read/Write Bit # Name Size (Bits) Description 7 Do Not Use 1 N/A 6 OCP 1 1: Mask OCP state-change interrupt. 0: Do not mask OCP state-change interrupt. 5 OVP 1 1: Mask OVP state-change interrupt. 0: Do not mask OVP state-change interrupt. 4 MIC_OVP 1 1: Mask MIC_OVP state-change interrupt. 0: Do not mask MIC_OVP state-change interrupt. 3 Resistor Code Change 1 1: Mask Resistor Code value-change interrupt. 0: Do not mask Resistor Code value-change interrupt. 2 VBUS_Valid 1 1: Mask VBUS_Valid state-change interrupt. 0: Do not mask VBUS_Valid state-change interrupt. 1 BC1.2_Complete 1 1: Mask BC1.2_complete interrupt. 0: Do not mask BC1.2_complete interrupt. 0 Do Not Use 1 N/A Table 11. Resistor Code Address: 07H Reset Value: 00000000 Type: Read Bit # Name Size (Bits) Description 7:5 Do Not Use 3 N/A 4:0 Resistor Code 5 Resistor code value read from ID_CON (see Table 3 Resistor Identification). Table 12. Timing Set Address: 08H Reset Value: 00000000 Type: Read/Write Bit # Name Size (Bits) 7:4 Do Not Use 4 N/A 3:0 Resistor Detection Time 4 Time to complete the ID_CON resistance measurement for accessory detection (see Table 13). (c) 2011 Fairchild Semiconductor Corporation FSA9285 * Rev 1.0.3 Description www.fairchildsemi.com 20 FSA9285-- MCPC Compliant USB Port Multimedia Switch with Auto-Detection Table 10. Interrupt Mask Address: 05H Reset Value: 00000000 Type: Read/Write Setting Value Resistor Detection Time (ms) 0000 50 0001 100 0010 150 0011 200 0100 300 0101 400 0110 500 0111 600 1000 700 1001 800 1010 900 1011 1000 1100 1101-1111 Table 14. Status Address: 09H Reset Value: 00000000 Type: Read/Write Bit # Name Size (Bits) 7 ID_SHORT 1 1: ID_SHORT detected. 0: ID_SHORT not detected. 6 OCP 1 1: VBUS in over-current state. 0: VBUS not in over-current state. 5 OVP 1 1: VBUS in over-voltage state. 0: VBUS not in over-voltage state. 4 MIC_OVP 1 1: MIC in over-voltage state 0: MIC not in over-voltage state 3 /ID_FLOAT 1 1: ID_CON not floating (resistor detected). 0: ID_CON floating (no resistor detected). 2 VBUS_Valid 1 1: VBUS is valid. 0: VBUS is not valid. 1 BC1.2_Active 1 1: BC1.2 is active. (This is true if a connect is attempted with DCD Timeout disabled and no DCD.) 0: BC1.2 IDLE. 0 DCD 1 1: Data contact detected on last charger-detect sequence. 0: No data contact detected on last charger-detect sequence. (c) 2011 Fairchild Semiconductor Corporation FSA9285 * Rev 1.0.3 Description www.fairchildsemi.com 21 FSA9285-- MCPC Compliant USB Port Multimedia Switch with Auto-Detection Table 13. Timing Table for Timing Set Register Bit # Name Size (Bits) Description 7 Do Not Use 1 Do not use. 6 Do Not Use 1 Do not use. 5 Dock 1 1: Charging dock detected. 0: Charging dock not detected. 4 Do Not Use 1 Do not use. 3 Do Not Use 1 Do not use. 2 DCP 1 1: USB dedicated charging port (DCP) charger detected. 0: USB dedicated charging port (DCP) charger not detected. 1 CDP 1 1: USB charging downstream port (CDP) charger detected. 0: USB charging downstream port (CDP) charger not detected. 0 SDP 1 1: USB standard downstream port (SDP) detected. 0: USB standard downstream port (SDP) not detected. Table 16. DAC SAR Address: 0BH Reset Value: 00000000 Type: Read Bit # Name Size (Bits) 7:0 DAC_SAR 8 Description DAC_SAR Value - Indicates raw 8-bit resistance value detected (see Table 3 Resistor Identification). (21) Table 17. Manual SW Address: 13H Reset Value: 00100111 Type: Read/Write Bit # 7:5 4:2 1:0 Name DM_CON Switching DP_CON Switching VBUS_IN Switching Size (Bits) Description 3 000: Open all switches. 001: DM_CON connected to DM_HOST1 of USB port. 010: DM_CON connected to Audio_L. 011: DM_CON connected to DM_HOST2 of USB port. 3 000: Open all switches. 001: DP_CON connected to DP_HOST1 of USB port. 010: DP_CON connected to Audio_R. 011: DP_CON connected to DP_HOST2 of USB port. 100: DP_CON connected to MIC. 2 00: Open all switches. 01: Do not use. 10: VBUS_IN connected to MIC. 11: VBUS_IN connected to VBUS_OUT (phone sinks current from attached (22) accessory). Notes: 21. When changing manual switch configurations on a single attach, the accessory must pass through an "Open All Switches" state between configurations. Manual Modes require the EN_MAN_SW Manual Mode bit in the Control register (02H) to be set. 22. VBUS_IN must be valid for the charger FET to close in manual FET switching. (c) 2011 Fairchild Semiconductor Corporation FSA9285 * Rev 1.0.3 www.fairchildsemi.com 22 FSA9285-- MCPC Compliant USB Port Multimedia Switch with Auto-Detection Table 15. Device Type Address: 0AH Reset Value: 00000000 Type: Read Bit # Name Size (Bits) Description 7:5 Do Not Use 3 N/A 4 Assert CHG_DETB 1 1: Assert CHG_DETB LOW. 0: Normal operation (CHG_DETB asserted LOW for DCP, CDP, ACA, and Car Kit Type 1/2; CHG_DETB is HIGH otherwise.) Note: EN_MAN_SW is not required for this bit to take effect. 3 MIC_OVP_EN 1 1: Enable MIC_OVP (only use when MIC is connected to VBUS). 0: Do not enable MIC_OVP. Note: EN_MAN_SW is not required for this bit to take effect. 2 Assert_D+ 1 1: Force 0.6 V on DP_CON. 0: Do not force 0.6 V on DP_CON. Note: EN_MAN_SW is not required for this bit to take effect, VBUS must be valid. 1:0 Do Not Use 2 N/A Table 19. Applications1 Address: 1BH Reset Value: X0001000 Type: Read/Write Bit # Name Size (Bits) Description 7:5 Do Not Use 3 N/A 4:2 # Consecutive ID Matches for Attach 3 000: 1 001: 2 010: 3 011: 4 100: 5 101: 6 110: 7 111: 8 1:0 Do Not Use 2 N/A Table 20. Applications2 Address: 1CH Reset Value: XXXX0101 Type: Read/Write Bit # Name Size (Bits) 7:4 Do Not Use 4 N/A 3:2 # ID Checks for Resistor Code Change 2 00: 1 01: 2 10: 3 11: 4 1:0 Max. Capacitance on ID 2 00: 500 pF 01: 1 nF 10: 1.5 nF 11: 2 nF (c) 2011 Fairchild Semiconductor Corporation FSA9285 * Rev 1.0.3 Description www.fairchildsemi.com 23 FSA9285-- MCPC Compliant USB Port Multimedia Switch with Auto-Detection Table 18. Manual CHG_CTRL Address: 14H Reset Value: 00000000 Type: Read/Write Product D E X Y FSA9285UCX 2.010 mm 1.672 mm 0.236 mm 0.205 mm Part Number Operating Temperature Range FSA9285UCX -40 to +85C (c) 2011 Fairchild Semiconductor Corporation FSA9285 * Rev 1.0.3 Top Mark Package NX 20-Lead, WLCSP (2.010 x 1.672 x 0.625 mm, 0.4 mm Pitch) www.fairchildsemi.com 24 FSA9285-- MCPC Compliant USB Port Multimedia Switch with Auto-Detection Product-Specific Dimensions BALL A1 INDEX AREA F A E 1.20 B A1 Cu Pad 0.03 C 1.20 A1 2X 1.60 D 0.40 Mask Opening Mask Opening 0.40 0.40 option 1 0.03 C 2X TOP VIEW Cu Pad option 2 RECOMMENDED LAND PATTERN (NSMD TYPE) 0.06 C 0.625 0.547 0.05 C E C SEATING PLANE SIDE VIEWS D 0.005 1.20 0.40 20X E D C B 1.60 0.40 A 1 2 3 4 BOTTOM VIEW F C A B NOTES: A. NO JEDEC REGISTRATION APPLIES. B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCE PER ASMEY14.5M, 2009. D. DATUM C IS DEFINED BY THE SPHERICAL CROWNS OF THE BALLS. E. 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