Single-Supply, Low Power, Precision FET Input Quad Buffer AD8244 Data Sheet FEATURES PIN CONFIGURATION IN A 1 10 IN D OUT A 2 9 OUT D +VS 3 8 -VS OUT B 4 7 OUT C IN B 5 6 IN C 11689-001 AD8244 Low power 250 A maximum supply current per amplifier FET input 2 pA maximum input bias current at 25C Extremely high input impedance Low noise 13 nV/Hz voltage noise at 1 kHz 0.4 V p-p voltage noise (0.1 Hz to 10 Hz) 0.8 fA/Hz current noise at 1 kHz High dc precision 3 V/C maximum offset drift (B grade) 3 MHz bandwidth Unique pinout No leakage from inputs to supply pins Provides guarding capability Rail-to-rail output Single-supply operation Input range extends to ground Wide supply range Single-supply: 3 V to 36 V Dual-supply: 1.5 V to 18 V Available in a compact 10-lead MSOP Figure 1. Pinout Isolates Inputs from Low-Impedance Leakage Sources Biopotential electrodes Medical instrumentation High impedance sensor conditioning Filters Photodiode amplifiers 200nV/DIV 1s/DIV 11689-002 APPLICATIONS Figure 2. 0.1 Hz to 10 Hz Voltage Noise GENERAL DESCRIPTION The AD8244 is a precision, low power, FET input, quad unity-gain buffer that is designed to isolate very large source impedances from the rest of the signal chain. The 2 pA maximum bias current, near zero current noise, and 10 T input impedance introduce almost no error, even with source impedance well into the megaohms. Many traditional operational amplifier pinouts have a supply pin that is next to the noninverting input. A guard trace must be routed between these pins to avoid leakage currents much larger than the bias current of a FET input op amp. Guard traces can be routed between pins for large packages, such as DIP or even SOIC; however, the board area consumed by these packages is prohibitive for many modern applications. The AD8244 solves this problem with a unique pinout that physically separates the Rev. A high impedance inputs from the low impedance supplies and outputs of the other buffers. This configuration simplifies guarding while reducing board space, allowing high performance and high density in the same design. The AD8244 design is focused on solving problems specific to buffers. This includes close channel-to-channel matching which allows channels of the AD8244 to be used in differential signal chains with minimal error. With its low voltage noise, wide supply range, and high precision, the AD8244 is also flexible enough to provide high performance anywhere a unity-gain buffer is needed, even with low source resistance. The AD8244 is specified over the industrial temperature range of -40C to +85C. It is available in a 10-lead MSOP package. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2013-2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD8244 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Guarding ...................................................................................... 14 Applications ....................................................................................... 1 Input Protection ......................................................................... 15 Pin Configuration ............................................................................. 1 Layout Considerations ............................................................... 15 General Description ......................................................................... 1 Differential Signal Chains ......................................................... 15 Revision History ............................................................................... 2 Low Output Impedance vs. Frequency.................................... 15 Specifications..................................................................................... 3 Applications Information .............................................................. 16 Absolute Maximum Ratings ............................................................ 6 Electrocardiogram (ECG) ......................................................... 16 Thermal Resistance ...................................................................... 6 Filtering........................................................................................ 16 ESD Caution .................................................................................. 6 Photodiode Amplifier ................................................................ 17 Pin Configuration and Function Descriptions ............................. 7 Low Noise, JFET Input Buffer .................................................. 18 Typical Performance Characteristics ............................................. 8 Outline Dimensions ....................................................................... 19 Theory of Operation ...................................................................... 14 Ordering Guide .......................................................................... 19 Overview...................................................................................... 14 REVISION HISTORY 12/14--Rev. 0 to Rev. A Added Figure 1 Caption and Changes to Figure 2 ....................... 1 Changes to Low Output Impedance vs. Frequency Section ..... 15 Changes to Electrocardiogram (ECG) Section, Filtering Section, Figure 42, and Figure 43 ................................................................ 16 Changes to Figure 44 ...................................................................... 17 Changes to Ordering Guide .......................................................... 19 10/13--Revision 0: Initial Version Rev. A | Page 2 of 20 Data Sheet AD8244 SPECIFICATIONS +VS = 5 V, -VS = 0 V, TA = 25C, VIN = 0.2 V, RL = 10 k to ground, unless otherwise noted. Table 1. Parameter DC PERFORMANCE Offset Voltage Over Temperature Average Temperature Coefficient Offset Voltage Matching Input Bias Current Over Temperature Input Bias Current Matching Over Temperature SYSTEM PERFORMANCE Nominal Gain System Error1 Average Temperature Coefficient Gain Matching NOISE PERFORMANCE Voltage Noise Spectral Density Peak-to-Peak Current Noise Spectral Density Peak-to-Peak DYNAMIC PERFORMANCE Small Signal Bandwidth Slew Rate Settling Time to 0.01% INPUT CHARACTERISTICS Input Voltage Range2 Over Temperature Input Impedance3 OUTPUT CHARACTERISTICS Output Swing Over Temperature Output Swing Over Temperature Short-Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Power Supply Rejection Supply Current per Amplifier Over Temperature TEMPERATURE RANGE Specified Performance Test Conditions/Comments Min AD8244A Typ Max 100 TA = -40C to +85C TA = -40C to +85C Channel to channel 0.5 TA = 85C Channel to channel TA = 85C Min 600 1.25 10 800 10 150 100 0.5 0.05 2 0.05 2 1 VOUT = 0.2 V to 3 V TA = -40C to +85C Channel to channel AD8244B Typ Max 350 0.675 5 500 2 50 0.2 1 0.08 2 0.10 Unit V mV V/C V pA pA pA pA 0.05 1 0.08 V/V % ppm/C % 2 nV/Hz V p-p f = 1 kHz f = 0.1 Hz to 10 Hz 13 0.4 13 0.4 f = 1 kHz f = 0.1 Hz to 10 Hz 0.8 8 0.8 8 fA/Hz fA p-p -3 dB 3 0.8 8 3 0.8 8 MHz V/s s VOUT = 0.2 V to 3 V 0 0 TA = -40C to +85C 4 3.5 0 0 10||4 RL = 10 k to ground TA = -40C to +85C RL = no load TA = -40C to +85C 0.025 0.03 0.025 0.03 4.9 4.88 4.97 4.95 3 1.5 0.025 0.03 0.025 0.03 -40 4.9 4.88 4.97 4.95 V V V V mA pF 36 18 250 300 V V dB A A +85 C 8 200 36 18 80 180 V V T||pF 10||4 8 200 Single supply Dual supply VIN = 2.5 V, +VS = 4.5 V to 5.5 V IOUT = 0 mA TA = -40C to +85C 4 3.5 3 1.5 80 180 250 300 +85 -40 Error as a percentage of the measurement. This includes the effects of open-loop gain and common-mode rejection ratio. The inputs of the AD8244 can go up to the positive supply; however, the input range is derated because error increases near the positive supply as the input transistors start to saturate. The inputs also maintain high impedance when driven slightly below ground. 3 For more information on the input impedance, see Figure 24 and Figure 37. 1 2 Rev. A | Page 3 of 20 AD8244 Data Sheet VS = 5 V, TA = 25C, VIN = 0 V, RL = 10 k, unless otherwise noted. Table 2. Parameter DC PERFORMANCE Offset Voltage Over Temperature Average Temperature Coefficient Offset Voltage Matching Input Bias Current Over Temperature Input Bias Current Matching Over Temperature SYSTEM PERFORMANCE Nominal Gain System Error1 Average Temperature Coefficient Gain Matching Nonlinearity NOISE PERFORMANCE Voltage Noise Spectral Density Peak-to-Peak Current Noise Spectral Density Peak-to-Peak DYNAMIC PERFORMANCE Small Signal Bandwidth Slew Rate Settling Time to 0.01% INPUT CHARACTERISTICS Input Voltage Range2 Over Temperature Input Impedance3 OUTPUT CHARACTERISTICS Output Swing Over Temperature Output Swing Over Temperature Short-Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Power Supply Rejection Supply Current per Amplifier Over Temperature TEMPERATURE RANGE Specified Performance Test Conditions/Comments Min AD8244A Typ Max 100 TA = -40C to +85C TA = -40C to +85C Channel to channel 0.5 TA = 85C Channel to channel TA = 85C Min 600 1.25 10 800 10 150 AD8244B Typ Max 100 0.5 0.05 2 0.05 2 1 350 0.675 5 500 2 50 0.2 1 0.05 2 0.08 V mV V/C V pA pA pA pA V/V % ppm/C % ppm VOUT = -3 V to +3 V TA = -40C to +85C Channel to channel VOUT = -3 V to +3 V 20 20 f = 1 kHz f = 0.1 Hz to 10 Hz 13 0.4 13 0.4 f = 1 kHz f = 0.1 Hz to 10 Hz 0.8 8 0.8 8 fA/Hz fA p-p -3 dB 3.3 0.8 14 3.3 0.8 14 MHz V/s s VOUT = -3 V to +3 V TA = -40C to +85C -5 -5 +4 +3.5 0.03 1 0.05 Unit -5 -5 10||4 RL = 10 k TA = -40C to +85C RL = no load TA = -40C to +85C -4.9 -4.88 -4.975 -4.95 +4.9 +4.88 +4.97 +4.95 -4.9 -4.88 -4.975 -4.95 3 1.5 TA -40 90 180 V V T||pF +4.9 +4.88 +4.97 +4.95 V V V V mA pF 36 18 250 300 V V dB A A +85 C 10 200 36 18 3 1.5 80 250 300 +85 -40 90 180 nV/Hz V p-p +4 +3.5 10||4 10 200 Single supply Dual supply VS = 3 V to 18 V IOUT = 0 mA TA = -40C to +85C 2 Error as a percentage of the measurement. This includes the effects of open-loop gain and common-mode rejection ratio. The inputs of the AD8244 can go up to the positive supply; however, the input range is derated because error increases near the positive supply as the input transistors start to saturate. 3 For more information on the input impedance, see Figure 24 and Figure 37. 1 2 Rev. A | Page 4 of 20 Data Sheet AD8244 VS = 15 V, TA = 25C, VIN = 0 V, RL = 10 k, unless otherwise noted. Table 3. Parameter DC PERFORMANCE Offset Voltage Over Temperature Average Temperature Coefficient Offset Voltage Matching Input Bias Current Over Temperature Input Bias Current Matching Over Temperature SYSTEM PERFORMANCE Nominal Gain System Error1 Average Temperature Coefficient Gain Matching Nonlinearity NOISE PERFORMANCE Voltage Noise Spectral Density Peak-to-Peak Current Noise Spectral Density Peak-to-Peak DYNAMIC PERFORMANCE Small Signal Bandwidth Slew Rate Settling Time to 0.01% INPUT CHARACTERISTICS Input Voltage Range2 Over Temperature Input Impedance3 OUTPUT CHARACTERISTICS Output Swing Over Temperature Output Swing Over Temperature Short-Circuit Current Capacitive Load Drive POWER SUPPLY Operating Range Power Supply Rejection Supply Current per Amplifier Over Temperature TEMPERATURE RANGE Specified Performance Test Conditions/Comments Min AD8244A Typ Max 100 TA = -40C to +85C TA = -40C to +85C Channel to channel 0.9 TA = 85C Channel to channel TA = 85C Min 600 1.25 10 800 10 150 AD8244B Typ Max 100 0.9 0.05 2 0.05 2 1 350 0.545 3 500 3 100 0.2 V mV V/C V pA pA pA pA VOUT = -10 V to +10 V TA = -40C to +85C Channel to channel VOUT = -10 V to +10 V 5 5 V/V % ppm/C % ppm f = 1 kHz f = 0.1 Hz to 10 Hz 13 0.4 13 0.4 nV/Hz V p-p f = 1 kHz f = 0.1 Hz to 10 Hz 0.8 8 0.8 8 fA/Hz fA p-p -3 dB 3.6 0.8 18 3.6 0.8 18 MHz V/s s 0.03 2 0.05 VOUT = -10 V to +10 V TA = -40C to +85C 1 Unit -15 -15 +14 +13.5 0.008 1 0.01 -15 -15 10||4 RL = 10 k TA = -40C to +85C RL = no load TA = -40C to +85C -14.87 -14.84 -14.95 -14.93 3 1.5 +14.87 +14.84 +14.95 +14.93 -14.87 -14.84 -14.95 -14.93 TA -40 +14.87 +14.84 +14.95 +14.93 V V V V mA pF 36 18 250 300 V V dB A A +85 C 20 200 36 18 90 180 V V T||pF 10||4 20 200 Single supply Dual supply VS = 3 V to 18 V IOUT = 0 mA TA = -40C to +85C +14 +13.5 3 1.5 80 250 300 +85 -40 90 180 Error as a percentage of the measurement. This includes the effects of open-loop gain and common-mode rejection ratio. The inputs of the AD8244 can go up to the positive supply; however, the input range is derated because error increases near the positive supply as the input transistors start to saturate. 3 For more information on the input impedance, see Figure 24 and Figure 37. 1 2 Rev. A | Page 5 of 20 AD8244 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Supply Voltage Output Short-Circuit Current Duration Maximum Voltage at IN x or OUT x1 Minimum Voltage at IN x or OUT x1 Storage Temperature Range Operating Temperature Range Maximum Junction Temperature ESD Human Body Model (HBM) Charged Device Model (CDM) Machine Model (MM) 1 Rating 18 V Indefinite +VS + 0.3 V -VS - 0.3 V -65C to +150C -40C to + 85C 150C 3 kV 1.25 kV 100 V For voltages beyond these limits, use input protection resistors. See the Input Protection section for more information. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL RESISTANCE JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 5. Thermal Resistance Package Type 10-Lead MSOP ESD CAUTION Rev. A | Page 6 of 20 JA 152 Unit C/W Data Sheet AD8244 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS +VS 3 OUT B 4 IN B 5 10 IN D AD8244 9 OUT D TOP VIEW (Not to Scale) 8 -VS 7 OUT C 6 IN C Figure 3. Pin Configuration Table 6. Pin Function Description Pin Number 1 2 3 4 5 6 7 8 9 10 Mnemonic IN A OUT A +VS OUT B IN B IN C OUT C -VS OUT D IN D Description Channel A Input Channel A Output Positive Supply Voltage Channel B Output Channel B Input Channel C Input Channel C Output Negative Supply Voltage Channel D Output Channel D Input Rev. A | Page 7 of 20 11689-003 IN A 1 OUT A 2 AD8244 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VS = 5 V, TA = 25C, VIN = 0 V, RL = 10 k, unless otherwise noted. 50 40 40 HITS HITS 30 30 20 20 10 -400 -200 0 200 400 600 OFFSET VOLTAGE (V) 0 -800 11689-004 0 -600 -400 -200 0 400 200 600 11689-007 10 800 OFFSET VOLTAGE MATCHING (V) Figure 4. Typical Distribution of Offset Voltage Figure 7. Typical Distribution of Offset Voltage Matching 12 VS = 15V TA = -40C TO +85C 40 VIN = 3V 10 35 30 HITS HITS 8 6 4 25 20 15 10 2 0 -300 -200 -100 0 100 200 300 SYSTEM ERROR (V/V) Figure 5. Typical Distribution of Offset Voltage Drift 11689-008 0 1 2 3 4 5 6 7 8 9 10 OFFSET VOLTAGE DRIFT (V/C) 11689-005 5 0 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 Figure 8. Typical Distribution of System Error 25 50 VS = 3V TO 18V 20 40 HITS HITS 15 30 10 20 5 -0.60 -0.55 -0.50 -0.45 -0.40 -0.35 INPUT BIAS CURRENT (pA) 0 -40 Figure 6. Typical Distribution of Input Bias Current -20 0 20 PSRR (V/V) 40 60 80 11689-009 0 11689-006 10 Figure 9. Typical Distribution of Power Supply Rejection Ratio (PSRR) Rev. A | Page 8 of 20 Data Sheet AD8244 10 120 REPRESENTATIVE SAMPLE 110 5 90 PSRR (dB) 0 GAIN (dB) -PSRR VS = 5V VIN = 0V 100 -5 VS = +3V VS = +5V VS = 5V VS = 15V -10 +PSRR VS = 5V VIN = 0V 80 +PSRR, SINGLE SUPPLY +VS = +5V, -VS = GND VIN = +2.5V 70 60 50 40 -15 10k 100k 20 0.1 11689-010 1k 1M FREQUENCY (Hz) Figure 10. Gain vs. Frequency 1 10 100 FREQUENCY (Hz) 1k 10k 11689-013 30 -20 Figure 13. PSRR vs. Frequency 10 10 TYPICAL MISMATCH BETWEEN ANY TWO CHANNELS CL = 100pF 5 IN-AMP GAIN MATCHING (%) 1 GAIN (dB) 0 -5 VS = +3V VS = +5V VS = 5V VS = 15V -10 1/2 0.1 AD8244 0.01 1k 10k 100k 0.001 11689-011 -20 1M FREQUENCY (Hz) 10 100 1k 10k 100k FREQUENCY (Hz) 11689-014 -15 Figure 14. Gain Matching vs. Frequency Figure 11. Gain vs. Frequency, CL = 100 pF 10 1k 1 GAIN MATCHING (%) 100 10 1/2 0.1 AD8244 0.001 100 1k 10k 100k FREQUENCY (Hz) 1M 10 100 1k 10k 100k FREQUENCY (Hz) Figure 15. Gain Matching vs. Frequency, 1 k Source Imbalance Figure 12. Output Impedance vs. Frequency Rev. A | Page 9 of 20 11689-015 0.1 10 IN-AMP 0.01 1 11689-012 OUTPUT IMPEDANCE () TYPICAL MISMATCH BETWEEN ANY TWO CHANNELS AD8244 Data Sheet 15 1k VS = 5V REPRESENTATIVE SAMPLE SHORT-CIRCUIT CURRENT (mA) 1 0.1 -20 0 20 40 60 80 TEMPERATURE (C) 0 -5 ISHORT - -10 -15 -40 11689-016 80 -50 OUTPUT VOLTAGE SWING (mV) REFERRED TO SUPPLY VOLTAGES SYSTEM ERROR (V/V) 60 +VS REPRESENTATIVE SAMPLES NORMALIZED AT 25C VIN = 3V 60 40 20 0 -20 -40 -60 -100 -40C +25C +85C RL = 100k -150 -200 +200 +150 +100 +50 -80 0 20 40 TEMPERATURE (C) 60 80 -VS 11689-017 -20 0 3 6 9 12 15 18 SUPPLY VOLTAGE (VS) Figure 17. System Error vs. Temperature, Normalized at 25C Figure 20. Output Voltage Swing vs. Supply Voltage, RL = 100 k 240 +VS -0.1 OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES 220 200 VS = 15V 180 VS = +5V 160 140 120 -0.2 -40C +25C +85C RL = 10k -0.3 -0.4 +0.4 +0.3 +0.2 +0.1 100 -40 -20 0 20 40 60 TEMPERATURE (C) 80 -VS 11689-018 SUPPLY CURRENT PER AMPLIFIER (A) 40 Figure 19. Short-Circuit Current vs. Temperature 100 -100 -40 20 TEMPERATURE (C) Figure 16. Input Bias Current vs. Temperature 80 0 -20 11689-020 0.01 -40 5 11689-019 10 0 3 6 9 12 15 18 SUPPLY VOLTAGE (VS) Figure 18. Supply Current vs. Temperature Figure 21. Output Voltage Swing vs. Supply Voltage, RL = 10 k Rev. A | Page 10 of 20 11689-021 INPUT BIAS CURRENT (pA) 100 ISHORT+ 10 AD8244 25 4 20 3 15 2 1 -40C +25C +85C -1 -2 10 5 0 -10 -3 -15 -4 -20 -5 100 1k 100k 10k 1M LOAD RESISTANCE () RL = 100k RL = 10k -5 -25 -10 80 -0.4 60 NONLINEARITY (ppm) 100 -0.6 -0.8 -40C +25C +85C +0.8 +0.6 0 2 4 6 8 10 20 0 -40 +0.2 -80 OUTPUT CURRENT (A) RL = 100k RL = 10k -20 -60 10m REPRESENTATIVE SAMPLE VS = 5V 40 +0.4 -100 -3 11689-023 OUTPUT VOLTAGE SWING (V) REFERRED TO SUPPLY VOLTAGES +VS 1m -2 -4 Figure 25. Nonlinearity, VS = 15 V -0.2 100 -6 OUTPUT VOLTAGE (V) Figure 22. Output Voltage Swing vs. Load Resistance -VS 10 -8 -2 -1 0 1 2 3 OUTPUT VOLTAGE (V) 11689-126 0 REPRESENTATIVE SAMPLE VS = 15V 11689-025 NONLINEARITY (ppm) 5 11689-022 OUTPUT VOLTAGE SWING (V) Data Sheet Figure 26. Nonlinearity, VS = 5 V Figure 23. Output Voltage Swing vs. Output Current 1k 10 NOISE (nV/Hz) 6 4 2 100 10 VS = 15V 0 -10 -5 0 5 10 INPUT VOLTAGE (V) 15 1 0.1 1 10 100 1k FREQUENCY (Hz) Figure 27. Voltage Noise Spectral Density vs. Frequency Figure 24. Input Bias Current vs. Input Voltage Rev. A | Page 11 of 20 10k 11689-028 -2 -15 VS = 5V 11689-026 INPUT BIAS CURRENT (pA) 8 AD8244 Data Sheet 1s/DIV 200nV/DIV VS = 15V 25 20 15 10 VS = 5V 5 VS = +5V 0 100 1k 10k 100k 1M FREQUENCY (Hz) 11689-031 11689-029 MAXIMUM OUTPUT VOLTAGE (V p-p) 30 Figure 31. Large Signal Frequency Response Figure 28. 0.1 Hz to 10 Hz Voltage Noise 5 VS = 15V 3 2 5V/DIV 1 18.4s TO 0.01% 0 -1 0.002%/DIV -2 -3 11689-032 -4 0 10 20 30 40 50 60 WARM-UP TIME (Seconds) 70 80 11689-129 50s/DIV -5 Figure 32. Large Signal Pulse Response and Settling Time, RL = 10 k, CL = 100 pF Figure 29. Change in Offset Voltage vs. Warm-Up Time 40 VS = 5V VIN = 5.5V 35 SETTLING TIME (s) 30 INPUT VOLTAGE OUTPUT VOLTAGE 25 SETTLED TO 0.01% 20 15 10 1ms/DIV 0 2 4 6 8 10 12 14 16 18 20 STEP SIZE (V) Figure 33. Settling Time vs. Step Size, RL = 10 k, CL = 100 pF Figure 30. No Phase Reversal Rev. A | Page 12 of 20 11689-033 5 2V/DIV 11689-030 CHANGE IN OFFSET VOLTAGE (V) 4 Data Sheet AD8244 -20 TYPICAL CHANNEL-TO-CHANNEL ISOLATION CHANNEL A FULLY DRIVEN RL = 10k CHANNEL ISOLATION (dB) -40 -60 -80 -100 -120 4s/DIV -160 10 1k 100 100k 10k FREQUENCY (Hz) 11689-136 20mV/DIV 11689-036 -140 Figure 36. Channel Isolation vs. Frequency Figure 34. Small Signal Pulse Response, RL = 10 k, CL = 100 pF 5.0 CL = NO LOAD CL = 100pF CL = 200pF 4.8 INPUT CAPACITANCE DOES NOT DEPEND ON NEGATIVE SUPPLY VOLTAGE INPUT CAPACITANCE (pF) 4.6 4.4 4.2 4.0 3.8 3.6 3.4 3.2 3.0 -16 -14 -12 -10 -8 -6 VIN (V) REFERRED TO +VS Figure 35. Small Signal Pulse Response with Various Capacitive Loads, RL = No Load Rev. A | Page 13 of 20 -4 -2 +VS 11689-038 4s/DIV 11689-037 25mV/DIV Figure 37. Input Capacitance vs. Input Voltage (VIN) Referred to +VS AD8244 Data Sheet THEORY OF OPERATION +VS +VS OUT +VS 500 IN -VS 11689-039 -VS -VS Figure 38. Simplified Schematic GUARDING When using low input bias current FET input amplifiers, designers must pay careful attention to voltage gradients from the input node to adjacent conductors on the board. These gradients can create leakage currents that overwhelm the input impedance and bias current performance of the FET input. These leakage currents get much worse with contamination, humidity, and temperature. Guarding techniques can be used to protect against parasitic leakage currents by greatly reducing the voltage gradient seen by the input node. Physically, a guard is a low impedance conductor that surrounds a high impedance node and is raised to the voltage of that node. It serves to buffer leakage by diverting it away from the sensitive node and into the low impedance guard. A complication results from the fact that many traditional op amp pinouts place a supply pin next to the noninverting input. The only way to guard the input of one LARGE FOOTPRINT PACKAGES 1 GUARD -IN SINGLE OP AMP -VS 8 1 7 +VS 2 INPUT +IN 3 GUARD SMALL FOOTPRINT PACKAGES 6 OUT 4 5 -IN 2 +IN GUARD INPUT SINGLE OP AMP 7 +VS 6 OUT 3 -VS 4 GUARD 8 5 *LEAKAGE PATH FROM +IN TO -VS CAUSES LARGE INPUT CURRENT Figure 39. Single Op Amp Guarding Patterns The AD8244 solves this problem with a unique pinout that naturally isolates the high impedance inputs from the low impedance nodes, such as the supplies and outputs of the other buffers. Additionally, the buffers of the AD8244 can be used to guard their own inputs, reducing the voltage gradient seen by the input to only the low offset voltage of the buffer. The AD8244 facilitates this by making guard traces easy to route without the need for traces to go between pins. Rev. A | Page 14 of 20 GUARD TRACE SURROUNDS INPUT NODE FROM SENSOR IN A GUARD TRACE OUT A 1 2 IN A OUT A SOLDER MASK REMOVED AD8244 3 +VS Figure 40. Guarding with the AD8244 11689-041 The AD8244 is a precision, quad, FET input, unity-gain buffer that is designed to isolate very large source impedances from the rest of the signal chain. N-channel JFETs are used as the input transistors to provide a low offset (350 V maximum), low noise (13 nV/Hz typical), high impedance (more than 10 T) input stage that operates right down to the negative supply voltage. Using a new drift trimming method, the B grade AD8244 is able to achieve very low offset voltage over temperature (0.545 mV maximum), and it introduces minimal system error over temperature. The AD8244 design is optimized for high precision applications, such as buffers for biopotential electrodes, where it is important that buffers have very high impedance inputs and channels that match closely. Because the AD8244 fits into a 10-lead package, whereas a quad op amp requires a minimum of 14 leads, routing space is reduced and parasitics from the feedback traces are eliminated. Furthermore, the flexible design and the high channel density of the AD8244 allow it to be used in the signal chain anywhere a unity-gain buffer is needed. of these op amps is to route the guard trace between the input pin and the supply pin. Traces can be routed between pins for large packages, such as DIP or even SOIC; however, the board area consumed by these packages is prohibitive for many modern applications. 11689-042 OVERVIEW Data Sheet AD8244 INPUT PROTECTION DIFFERENTIAL SIGNAL CHAINS All terminals of the AD8244 are protected against ESD. In addition, the input structure allows for dc overload conditions up to a diode drop above the positive supply and a diode drop below the negative supply. Voltages more than a diode drop beyond the supplies cause the ESD diodes to conduct and enable current to flow through the diode. Therefore, use an external resistor in series with each of the inputs to limit current for voltages beyond the supplies. In either scenario, the AD8244 input safely handles a continuous 6 mA current at room temperature. The AD8244 can be used to buffer the inputs of difference amplifiers and instrumentation amplifiers to take advantage of qualities of the JFET input. In applications such as these, which use two channels of the AD8244 to buffer the positive and negative of a differential signal path, it is the mismatch between the channels, rather than the absolute error, that introduces error into the system. The AD8244 is designed so that the channels closely match and can be used in differential circuits with excellent results. Channel-to-channel matching errors are specified to aid in the design process. When driving the inputs of an instrumentation amplifier, difference amplifier, or other differential input circuit, the gain matching from channel to channel defines the common-mode rejection ratio (CMRR) error introduced to the system by the AD8244. The unit conversion is as follows: For applications where the AD8244 encounters extreme overload voltages, as in cardiac defibrillators, use external series resistors and low leakage diode clamps, such as FJH1100 or BAV199L. LAYOUT CONSIDERATIONS The inputs of the AD8244 buffers are extremely high impedance. Shunt impedances from leakage resistance and parasitic capacitance in the printed circuit board (PCB) layout can severely degrade the performance of the JFET input. If a buffer output is used to surround the corresponding input node, leakage resistance and parasitic capacitance from the layout can be kept extremely low. Remove solder mask from the guard traces to guard against surface leakage due to contamination. In addition to the guard traces on the primary side, route a guard trace around any vias in the input net on the other side of the board as well. Keep the parasitic capacitance seen by the output small to maintain the optimum step response. Amplifiers used in the same signal path, such as buffering the voltage for two inputs of an inamp or difference amplifier, must have matched impedance in the input traces. This includes matched length and symmetrical traces. Place any input resistors close to the AD8244 inputs to avoid interaction with trace parasitics. If one of the channels is not in use, connect the input to a voltage that is within its linear range to avoid overdrive conditions that can interfere with other channels. Leave the output unconnected. Place decoupling capacitors, such as 0.1 F, near the AD8244. Larger capacitors, such as 10 F, can be used farther away from the device. CMRR (dB) = 20 x log10(100/Gain Matching (%)) The JFET pinch-off voltage can vary from channel to channel and cause additional mismatch when the JFET begins to saturate near the positive rail. The CMRR error is minimized by keeping the input voltage away from the positive input range limit. Because the input impedance is very high, the CMRR achieved in differential systems stays high, even with large or mismatched source resistance. See the Typical Performance Characteristics section for more information. LOW OUTPUT IMPEDANCE vs. FREQUENCY The closed-loop output impedance of the AD8244 increases at higher frequencies when the loop gain is reduced, as shown in Figure 12. The AD8244 drives 200 pF directly with slight ringing, as shown in Figure 35. By placing a small resistor in series with the output, the capacitive load drive of the AD8244 can be increased. For applications that need the AD8244 input performance and very low output impedance over frequency, such as driving a cable shield, a switching load, or a large amount of capacitance at high frequencies, an op amp can be added in a configuration, such as the one in Figure 41. This configuration takes advantage of the low op amp output impedance at low frequencies, and the load capacitor reduces the output impedance at high frequencies. Typically, RF x CF should be less than or equal to RO x CL. 1/4 RS AD8244 RO A1 VOUT CL VIN RF Figure 41. Adding an Op Amp for Low Output Impedance Rev. A | Page 15 of 20 11689-043 CF AD8244 Data Sheet APPLICATIONS INFORMATION Sallen-Key Low-Pass Filter In an ECG system, mismatches between the source impedance of different leads, working against the input impedance of the front-end amplifier, can create unbalanced voltage dividers that reduce the system CMRR. When presented to a moderately high input impedance amplifier, the combined impedance of the skin, electrolyte, electrodes, and the protection resistors can be enough to cause power line noise pickup, current noise issues, and signal division. Dry electrode systems, which are becoming increasingly common and have significantly higher source impedance, are especially sensitive to these errors. Typically, a high input impedance, low bias current, FET input op amp is used to buffer the electrode signal before it is presented to an instrumentation amplifier. This buffer solves the majority of these problems; however, when an instrument is in the field, it can be subject to dust pickup and humidity. If the op amp input is not guarded, these environmental factors can create unwanted leakage currents that bring back the aforementioned issues from insufficient input impedance. The AD8244 pinout is configured to make it simple to guard the inputs from parasitic resistance and capacitance while it also drives the instrumentation amplifier inputs, creating a more robust design, while saving power and board space. The CMRR of the AD8244 driving an instrumentation amplifier initially depends on the gain matching for the chosen supplies and voltage range, as well as the instrumentation amplifier used, but it can be improved with design techniques such as right leg drive (RLD) or digital filtering. FILTERING C1 2nF R1 1/4 R2 AD8244 VOUT C2 1nF VIN NOTES 1. R1 = R2 = R 2. R = 112.5M/fC, Q = 0.707 11689-143 ELECTROCARDIOGRAM (ECG) Figure 42. Sallen-Key Low-Pass Filter The following equations describe the corner frequency, fC, and quality factor, Q, for the low-pass filter case of the Sallen-Key topology, shown in Figure 42: fC = 1/(2 R1 x R2 x C1 x C2 ) Q = ( R1 x R2 x C1 x C2 )/(C2 x (R1 + R2)) For an example of a design with this topology, choose a filter where Q = 0.707 and R1 = R2 = R. This requires that C1 = 2 x C2. The corner frequency equation can now be simplified to fC = 1/(2 x R x C2 x 2) If an available capacitor, such as 1 nF, is chosen for C2, R can be written in terms of the desired cutoff frequency: R = 1/(22 x x 1 nF x fC) = 112.5 M/fc (that is, R = 750 k for fC = 150 Hz) Sallen-Key High-Pass Filter R1 C1 22nF C2 22nF 1/4 AD8244 VOUT R2 VIN NOTES 1. R2 = R, R1 = R/2 2. R = 10.2M/fC, Q = 0.707 11689-144 In filtering applications, it is generally recommended to use capacitors such as C0G or NP0 ceramics for distortion and dielectric absorption performance. These types of capacitors do not have a high volumetric efficiency and are only available in values less than a few tens of nanofarads, depending on the case size and voltage rating. For a given cutoff frequency, using smaller capacitors requires larger resistor values. At low frequencies where the resistor values become very large, the bias current of a typical op amp can introduce significant offsets and additional noise. The subpicoampere bias current of the AD8244 allows resistor values in the tens of megaohms with no additional error while providing an excellent low power, small footprint solution for filter design. Between the four channels of the AD8244, a filter with more than eight poles can be implemented while using less space than the same filter with a quad op amp. Figure 43. Sallen-Key High-Pass Filter The high-pass filter case of the Sallen-Key topology has the same corner frequency equation as the low-pass filter. However, the equation for Q changes to Q = ( R1 x R2 x C1 x C2 )/(R1 x (C1 + C2)) In this case, a Q of 0.707 is achieved with C1 = C2 = C, and 2 x R1 = R2 = R, which is a symmetrical result to the low-pass filter case. The corner frequency then simplifies to fC = 1/(2 x x R x C) For a low corner frequency, a larger available capacitor such as 22 nF can be chosen, yielding the following expression for R: R = 10.2 M/fc (that is, a 0.5 Hz filter requires R1 = 10 M and R2 = 20 M) Rev. A | Page 16 of 20 Data Sheet AD8244 Twin-T Notch Filter PHOTODIODE AMPLIFIER R 1/4 AD8244 2C VOUT (1 - K) x R' 1/4 AD8244 VIN R/2 11689-145 C K x R' C Figure 44. Twin-T Notch Filter The following equations describe the parameters of the Twin-T notch filter with active feedback shown in Figure 44: fO = 1/(2RC) Q = 0.25/(1 - K) where K is an attenuation factor from 0 to 1, as shown in Figure 44. A K of either 0 or 1 can be achieved with only one buffer. Photodiodes in precision circuits are typically measured in photovoltaic mode, in which there is no reverse bias voltage. Two benefits to this measurement mode are that there is no dark current, and the output is linearly related to the light intensity. However, in photovoltaic mode, the signal current can be very small, requiring a high gain transimpedance amplifier (TIA). There are a limited number of amplifiers suited for building TIAs for measuring photodiodes or other low current sensors, which can make it difficult to achieve high performance. Using an AD8244 as the interface to the photodiode eliminates the need for a low bias current op amp, allowing optimization of other parameters, such as precision, slew rate, output drive, board space, and cost. As with any composite amplifier, it is important to pay special attention to stability. The unity-gain crossover frequency of the op amp must be less than the AD8244 bandwidth for this configuration to be unity-gain stable. The noise gain of the op amp varies with the shunt resistance of the diode, which is temperature dependent. GUARD One of the best things about this filter is that fO and Q are independent, which allows for easy tuning of filter characteristics. However, designers use the Twin-T notch filter sparingly in production designs because of its sensitivity to component tolerances, which affect both the depth and the frequency of the notch. Reducing the Q is one way to ensure that the desired frequency has sufficient attenuation independent of component variance and drift; however, reducing the Q also linearly increases the distance between the pass bands. The notch depth can be improved and the stop-band width decreased simultaneously by cascading multiple filter stages. To illustrate the benefit of cascading stages, Figure 45 shows the response of two filters, both designed to provide greater than 26 dB of attenuation at 60 Hz 5%, which allows for component tolerance. The single stage filter requires a Q of 0.5 and results in a -3 dB notch bandwidth of 120 Hz. The two stage filter has a Q of 2.25 for each stage, and the -3 dB notch bandwidth is reduced to about 40 Hz. 20 10 0 -20 -26dB FROM 57Hz TO 63Hz -30 -40 -50 -60 SINGLE STAGE NOTCH TWO STAGE CASCADED NOTCH -70 -80 10 100 FREQUENCY (Hz) 1k 11689-046 MAGNITUDE (dB) -10 Figure 45. Cascading Notch Filters Rev. A | Page 17 of 20 RF CF 1/4 AD8244 IPHD A1 VOUT 11689-044 C = 7500pF 60Hz: R = 357k 50Hz: R = 422k R Figure 46. AD8244 in a Photodiode Application AD8244 Data Sheet LOW NOISE, JFET INPUT BUFFER 1/4 RO AD8244 1/4 RO AD8244 VOUT RS 1/4 VIN RO AD8244 1/4 RO AD8244 Figure 47. Reducing the Voltage Noise Rev. A | Page 18 of 20 11689-045 The voltage noise of the AD8244 can be reduced by placing multiple buffers in parallel. For example, two buffers in parallel reduce the voltage noise by 2, or all four buffers placed in parallel act as a buffer with 1/2 the noise. The trade-offs to this method are increased bias current, current noise, and input capacitance. Place a small resistor, such as 50 , between the outputs to avoid extra current flow due to the slight differences between each output. For less power sensitive applications, these 50 resistors can be omitted to boost the available output current. Data Sheet AD8244 OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 1 5.15 4.90 4.65 6 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15 MAX 1.10 MAX 0.30 0.15 6 0 0.23 0.13 COMPLIANT TO JEDEC STANDARDS MO-187-BA 0.70 0.55 0.40 091709-A 0.15 0.05 COPLANARITY 0.10 Figure 48. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Model1 AD8244ARMZ AD8244ARMZ-R7 Temperature Range -40C to +85C -40C to +85C AD8244BRMZ AD8244BRMZ-R7 -40C to +85C -40C to +85C AD8244-EVALZ 1 Package Description 10-Lead Mini Small Outline Package [MSOP], Standard Grade 10-Lead Mini Small Outline Package [MSOP], Standard Grade, 7" Tape and Reel 10-Lead Mini Small Outline Package [MSOP], High Performance Grade 10-Lead Mini Small Outline Package [MSOP], High Performance Grade, 7" Tape and Reel Evaluation Board Z = RoHS Compliant Part. Rev. A | Page 19 of 20 Package Option RM-10 RM-10 Branding Y54 Y54 RM-10 RM-10 Y55 Y55 AD8244 Data Sheet NOTES (c)2013-2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11689-0-12/14(A) Rev. A | Page 20 of 20