MT48LC32M16A2TG-75:C - Micron Technology

Products and specifications discussed herein are subject to change by Micron without notice.

512Mb: x4, x8, x16 SDRAM

Features

PDF: 09005aef809bf8f3/Source: 09005aef80818a4a Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

Synchronous DRAM

MT48LC128M4A2 – 32 Meg x 4 x 4 banks

MT48LC64M8A2 – 16 Meg x 8 x 4 banks

MT48LC32M16A2 – 8 Meg x 16 x 4 banks

For the latest data sheet, refer to Micr on’s Web site

Features

• PC100- and PC133-compliant

• Fully synchr onous; all signals registere d on positive

edge of system clock

• Internal pipe lined operatio n; column addres s can be

changed every clock cycle

• Internal banks for hiding row access/pr echarge

• Programmable burst lengths: 1, 2, 4, 8, or full page

• A uto prechar ge, includes concurr ent auto precharge ,

and auto refresh modes

• Self refresh mode

• 64ms, 8,192-cycle refresh

• LVTTL-compatible inputs and outputs

• Single +3.3V ±0.3V power supply

P art Number Example:

MT48LC32M16A2P-75:C

Table 1: Address Table

Parameter 32 Meg x 4 32 Meg x 8 32 Meg x 16

Configuration 32 Meg x 4

x 4 banks 16 Meg x 8

x 4 banks 8 Meg x 16

x 4 banks

Refresh count 8K 8K 8K

Row

addressing 8K (A0–A12) 8K (A0–A12) 8K (A0–A12)

Bank

addressing 4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1)

Column

addressing 4K (A0–A9,

A11, A12) 2K (A0–A9,

A11) 1K (A0–A9)

Table 2: Key Timing Parameters

Speed

Grade Clock

Frequency

Access Time Setup

Time Hold

TimeCL = 2 CL = 3

-7E 143 MHz – 5.4ns 1.5ns 0.8ns

-75 133 MHz – 5.4ns 1.5ns 0.8ns

-7E 133 MHz 5.4ns – 1.5ns 0.8ns

-75 100 MHz 6ns – 1.5ns 0.8ns

Notes: 1. Refer to Micron technical note: TN-48-05.

2. Off-center parting line.

3. Contact factory for availability.

4. Available on x4 and x8 only.

Options Marking

• Configurations

–128 Meg x 4 (32 Meg x 4 x 4 banks) 128M4

–64 Meg x 8 (16 Meg x 8 x 4 banks) 64M8

–32 Meg x 16 (8 M eg x 16 x 4 banks) 32M16

•WRITE recovery (

tWR)

–tWR = “2 CLK”1A2

•Plastic package – OCPL

–54-pin TSOP II (400 mil) TG

–54-pin TSOP II (400 mil) Pb-free P

• Timing (cycle time)

–7.5ns @ CL = 2 (PC133) -7E4

–7.5ns@ CL = 3 (PC133) -75

• Self refresh

–Standard None

–Low power L3

• Operating temperature range

–Commercial (0oC to +70oC) None

–Industrial (–40oC +85oC) IT

• Revision :C

PDF: 09005aef809bf8f3/Source: 09005aef80818a4a Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

512Mb: x4, x8, x16 SDRAM

Table of Contents

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Burst Length (BL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

CAS Latency (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

WRITE Burst Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

COMMAND INHIBIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

LOAD MODE REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

BURST TERMINATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Bank/Row Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

READs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

WRITEs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Clock Suspend. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Burst READ/Single WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Concurrent Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Temperature and Thermal Impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

PDF: 09005aef809bf8f3/Source: 09005aef80818a4a Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

512Mb: x4, x8, x16 SDRAM

List of Figur es

List of Figures

Figure 1: 128 Meg x 4 SDRAM Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Figure 2: 64 Meg x 8 SDRAM Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Figure 3: 32 Meg x 16 SDRAM Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Figure 4: Pin Assignment (Top View) 54-Pin TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Figure 5: Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Figure 6: CAS Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Figure 7: Activating a Specific Row In a Specific Bank. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 8: Example Meeting tRCD (MIN) when 2 < tRCD (MIN)/tCK ≤ 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Figure 9: READ Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Figure 10: CAS Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Figure 11: Consecutive READ Bursts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Figure 12: Random READ Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 13: READ-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Figure 14: READ-to-WRITE with Extra Clock Cy cle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Figure 15: READ-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Figure 16: Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Figure 17: WRITE Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 18: WRITE Burst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Figure 19: WRITE-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Figure 20: Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 21: WRITE-to-READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 22: WRITE-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 23: Terminating a WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 24: PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 25: Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Figure 26: CLOCK SUSPEND During WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Figure 27: CLOCK SUSPEND During READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Figure 28: READ with Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Figure 29: READ with Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Figure 30: WRITE with Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Figure 31: WRITE with Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Figure 32: Example Temperature Test Point Location, 54-Pin TSOP : Top View . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Figure 33: Initialize and Load Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Figure 34: Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Figure 35: Clock Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Figure 36: Auto-Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Figure 37: Self Refresh Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Figure 38: READ – Without Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Figure 39: READ – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Figure 41: Single REA D – With A uto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Figure 42: Alternating Bank Read Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Figure 43: READ – Full-Page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Figure 44: READ DQM Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Figure 45: WRITE – Without Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Figure 46: WRITE – With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Figure 47: Single WRITE – Without Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Figure 48: Single WRITE with Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Figure 49: Alternating Bank WRITE Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Figure 50: WRITE – Full-Page Burst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Figure 51: WRITE – DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Figure 52: 54-Pin Plastic TSOP (400 mil). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

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512Mb: x4, x8, x16 SDRAM

List of Tables

Table 1: Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Table 2: Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Table 3: Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Table 4: Burst Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Table 5: CAS Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Table 6: Truth Table 1 – Commands and DQM Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Table 7: Truth Table 2 – CKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Table 8: Truth Table 3 – Current State Bank n, Command to Bank n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Table 9: Truth Table 4 – Current State Bank n, Command to Bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Table 10: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Table 11: Temperature Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Table 12: Summary of Thermal Impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Table 13: DC Electrical Characteristics And Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Table 14: IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Table 15: Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Table 16: Electrical Characteristics and Recommended AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .45

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512Mb: x4, x8, x16 SDRAM

General Description

The 512Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing

536,870,912 bits. It is internally configured as a quad-bank DRAM with a synchronous

interface (all signals are registered on the positive edge of the cl ock signal, CLK). Each of

the x4’s 134,217,728-bit banks is organized as 8,192 rows b y 4,096 columns by 4 bits . Each

of the x8’s 134,217,728-bit banks is organized as 8,192 rows by 2,048 columns by 8 bits.

Each of the x16’s 134,217,728-bit banks is organized as 8,192 rows b y 1,024 columns by

16 bits.

Read and write accesses to the SDRAM are burst oriented; accesses start at a selected

location and continue for a programmed number of locations in a programmed

sequence. Accesses beg in with the registration of an ACTIVE command, which is then

followed by a READ or WRITE command. The address bits registered coincident with the

ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select

the bank; A0–A12 select the row). The address bits registered coincident with the READ

or WRITE command are used to select the starting column location for the burst access.

The SDRAM pro vides for progr ammable READ or WRITE burst lengths (BL ) of 1, 2, 4, or 8

locations, or the full page, with a burst terminate option. An auto precharge function

may be enabled to provide a self-timed row precharge that is initiated at the end of the

burst sequence.

The 512Mb SDRAM uses an internal pipelined ar chi tectur e to achieve high-spe ed opera-

tion. This architecture is compatible with the 2n rule of prefetch architectures, but it also

allows the column address to be changed on every clock cycle to achieve a high-speed,

fully random access. Precharging one bank while accessing one of the other three banks

will hide the PRECHARGE cycles and pr ovide seamless, high-speed, random-access

operation.

The 512Mb SDRAM is designed to operate at 3.3V. An auto refr esh mode is provided,

along with a power-saving, power-do wn mode. All inputs and outputs are LVTTL-

compatible.

SDRAMs offer substantial advances in DRAM operating perfor mance, including the

ability to synchronously burst data at a high data rate with automatic column-address

generation, the ability to interleave be tween internal banks to hide pre charge time, and

the capability to randomly change column addresses on each clock cycl e during a burst

access.

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512Mb: x4, x8, x16 SDRAM

General Description

Figure 1: 128 Meg x 4 SDRAM Functional Block Diagram

RAS#

CAS#

ROW-

ADDRESS

MUX

CLK

CS#

WE#

CKE

CONTROL

LOGIC

COLUMN-

ADDRESS

COUNTER/

LATCH

MODE REGISTER

COMMAND

DECODE

A0–A12,

BA0, BA1

DQM

ADDRESS

4096

(x4)

16384

I/O GATING

DQM MASK LOGIC

READ DATA LATCH

WRITE DRIVERS

COLUMN

DECODER

BANK0

MEMORY

ARRAY

(8,192 x 4,096 x 4)

BANK0

ROW-

ADDRESS

LATCH

DECODER

8192

SENSE AMPLIFIERS

BANK

CONTROL

LOGIC

DQ0–

DQ3

DATA

INPUT

DATA

OUTPUT

BANK1BANK2 BANK3

1 1

REFRESH

COUNTER

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512Mb: x4, x8, x16 SDRAM

General Description

Figure 2: 64 Meg x 8 SDRAM Functional Block Diagram

RAS#

CAS#

ROW-

ADDRESS

MUX

CLK

CS#

WE#

CKE

CONTROL

LOGIC

COLUMN-

ADDRESS

COUNTER/

LATCH

MODE REGISTER

COMMAND

DECODE

A0–A12,

BA0, BA1

DQM

ADDRESS

2048

(x8)

16384

I/O GATING

DQM MASK LOGIC

READ DATA LATCH

WRITE DRIVERS

COLUMN

DECODER

BANK0

MEMORY

ARRAY

(8,192 x 2,048 x 8)

BANK0

ROW-

ADDRESS

LATCH

DECODER

8192

SENSE AMPLIFIERS

BANK

CONTROL

LOGIC

DQ0–

DQ7

8DATA

INPUT

DATA

OUTPUT

BANK1BANK2 BANK3

1 1

REFRESH

COUNTER

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512Mb: x4, x8, x16 SDRAM

General Description

Figure 3: 32 Meg x 16 SDRAM Functional Block Diagram

RAS#

CAS#

ROW-

ADDRESS

MUX

CLK

CS#

WE#

CKE

CONTROL

LOGIC

COLUMN-

ADDRESS

COUNTER/

LATCH

MODE REGISTER

COMMAND

DECODE

A0–A12,

BA0, BA1

DQML,

DQMH

ADDRESS

1024

(x16)

16384

I/O GATING

DQM MASK LOGIC

READ DATA LATCH

WRITE DRIVERS

COLUMN

DECODER

BANK0

MEMORY

ARRAY

(8,192 x 1,024 x 16)

BANK0

ROW-

ADDRESS

LATCH

DECODER

8192

SENSE AMPLIFIERS

BANK

CONTROL

LOGIC

DQ0–

DQ15

16 DATA

INPUT

DATA

OUTPUT

BANK1BANK2 BANK3

2 2

REFRESH

COUNTER

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512Mb: x4, x8, x16 SDRAM

General Description

Figure 4: Pin Assignment (Top View) 54-Pin TSOP

Note: The # symbol indicates signal is active LOW. A dash (-) indicates x8 and x4 pin function is

same as x16 pin function.

DQ0

DQ1

DQ2

VssQ

DQ3

DQ4

DQ5

DQ6

VssQ

DQ7

DQML

WE#

CAS#

RAS#

CS#

BA0

BA1

A10

Vss

DQ15

VssQ

DQ14

DQ13

DQ12

DQ11

VssQ

DQ10

DQ9

DQ8

Vss

DQMH

CLK

CKE

A12

A11

Vss

x8x16 x16x8 x4x4

DQ0

DQ1

DQ2

DQ3

DQ0

DQ1

DQ7

DQ6

DQ5

DQ4

DQM

DQ3

DQ2

DQM

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512Mb: x4, x8, x16 SDRAM

General Description

Table 3: Pin Descriptions

Numbers Symbols Type Description

38 CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on

the positive edge of CLK. CLK also increments the internal burst counter and

controls the output registers.

37 CKE Input Clock enable: CKE acti vates (HIGH) an d deactivates (LOW) the CLK signal.

Deactivating the clock provides PRECHARGE power-down and SELF REFRESH

operation (all banks idle), ACTIVE power-down (row active in any bank), or CLOCK

SUSPEND operation (burst/access in progress). CKE is synchronous except after the

device enters power-down and self refresh modes, where CKE becomes

asynchronous until after exiting the same mode. The input buffers, in clu di ng CLK,

are disabled during power-down and self refresh modes, providing low standby

power. CKE may be tied HIGH.

19 CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the

command decoder. All commands are masked when CS# is registered HIGH. CS#

provides for external bank selection on systems with multiple banks. CS# is

considered part of the command code.

18, 17, 16 RAS#,

CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command

being entered.

39 x4, x8:

DQM Input Input/output mask: DQM is an input mask signal for write accesses and an output

enable signal for read accesses. Input data is masked when DQM is sampled HIGH

during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock

latency) when DQM is sampled HIGH during a READ cycle. On the x4 and x8, DQML

(Pin 15) is a NC and DQMH is DQM. On the x16, DQML corresponds to DQ0–DQ7,

and DQMH corresponds to DQ8–DQ15. DQML and DQMH are considered same

state when referenced as DQM.

15, 39 x16:

DQML,

DQMH

20, 21 BA0, BA1 Input Bank address inputs: BA0 and BA 1 define to w hich bank the ACTIVE, READ, WRITE,

or PRECHARGE command is being applied.

23–26, 29–

34, 22, 35,

A0–A12 Input Address inputs: A0–A12 are sampled during the ACTIVE command (row-address

A0–A12) and READ/WRITE command (column-address A0–A9, A11, A12 [x4]; A0–

A9, A11 [x8]; A0–A9 [x16]; with A10 defining auto precharge) to select one location

out of the memory array in the respective bank. A10 is sampled during a

PRECHARGE command to determine whether all banks are to be precharged (A10

[HIGH]) or bank selected by (A10 [LOW]). The address inputs also provide the op-

code during a LOAD MO DE REGISTER command.

2, 4, 5, 7, 8,

10, 11, 13,

42, 44, 45,

47, 48, 50,

51, 53

DQ0–DQ15 x16: I/O Data input/output: Data bus for x16 (4, 7, 10, 13, 15, 42 , 45, 48, and 51 are NCs for

x8; 2, 4, 7, 8, 10, 13, 15, 42, 45, 47, 48, 51, and 53 are NCs for x4).

2, 5, 8, 11,

44, 47, 50,

DQ0–DQ7 x8: I/O Data input/output: Data bus for x8 (2, 8, 47, and 53 are NCs for x4).

5, 11, 44,

50 DQ0–DQ3 x4: I/O Data input/output: Data bus for x4.

40 NC – No connect: This pin should be left unconnected.

3, 9, 43, 49 VDDQ Supply DQ power: Isolated DQ power to the die for improved noise immunity.

6, 12, 46,

52 VSSQ Supply DQ ground: Isolated DQ ground to the die for improved noise immunity.

1, 14, 27 VDD Supply Power supply: +3.3V ±0.3V.

28, 41, 54 VSS Supply Ground.

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512Mb: x4, x8, x16 SDRAM

Functional Description

The 512Mb SDRAMs (32 Meg x 4 x 4 banks, 16 Meg x 8 x 4 banks, and 8 Meg x 16 x 4

banks) are quad-bank DRAMs that operate at 3.3V and include a synchronous interface

(all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s

134,217,728-bit banks is organized as 8,192 rows by 4,096 columns by 4 bits. Each of the

x8’s 134,217,728-bit banks is organized as 8,192 rows by 2,048 columns by 8 bits. Each of

the x16’s 134,217,728-bit banks is organized as 8,192 rows by 1,024 columns b y 16 bits.

Read and write accesses to the SDRAM are burst oriented; accesses start at a selected

location and continue for a programmed number of locations in a programmed

sequence. Accesses beg in with the registration of an ACTIVE command, which is then

followed by a READ or WRITE command. The address bits registered coincident with the

ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1

select the bank, A0–A12 select the row). The addr ess bits (x4: A0–A9, A11, A12; x8: A0–A9,

A11; x16: A0–A9) registered coincident with the READ or WRITE command are used to

select the starting column location for the burst access.

Prior to normal ope ration, the SDR AM must be initialized . The fo ll owing sections

provide detailed information covering device initialization, register definition,

command descriptions, and device operation.

Initialization

SDRAMs must be powered up and initialized in a predefined manner. Operational

procedures other than those specified may r esult in undefined operation. After power is

applied to VDD and VDDQ (simultaneously) and the clock is stable (stable clock is

defined as a signal cycling within timing constraints specified for the clock pin), the

SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND

INHIBIT or NOP. Starting at some point during this 100µs period and continuing at least

through the end of this pe riod, C O MMAND INHIBIT or NOP commands should be

applied.

After the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP

command having been applied, a PRECHARGE command should be applied. All banks

must then be pr echarged, thereby placing the device in the all banks idle state.

Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO

REFRESH cycles are complete, the SDRAM is ready for mode register programmin g.

Because the mode register will power up in an unknown state, it should be loaded prior

to applying any operational command.

If desired, the two AUTO REFRESH commands can be is sue d after the LMR com m a nd .

The recommended power-up sequence for SDRAMs:

1. S i multaneously apply power to VDD and VDDQ.

2. Assert and hold CKE at a LVTTL logic LOW since all inputs and outputs are LVTTL-

compatible.

3. P rovide stable CLOCK signal. Stable clock is defined as a signal cycling within timing

constraints speci fie d for th e c loc k pin.

4. Wait at least 100µs prior to is sui n g any command other than a COMMAND INHIBIT

or NOP.

5. Starting at some point during this 100µs period, bring CKE HIGH. Continuing at least

through the end of this period, one or more COMMAND INHIBIT or NOP commands

must be applied.

6. Perfor m a PRECHARGE ALL command.

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512Mb: x4, x8, x16 SDRAM

Functional Description

7. Wait at least tRP time; during this time, NOPs or DESELECT commands must be

given. All banks will complete their precharge, thereby placing the device in the all

banks idle state.

8. Issue an AUTO REFRESH command.

9. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT commands

are allowed.

10. Issue an AUTO REFRESH command.

11. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT commands

are allowed.

12. The SDRAM is no w ready for mode register programming. Because the mode register

will power up in an unknown state, it should be loaded with desired bit values prior to

applying any operational command. Using the LMR command, progr am the mode

with BA1 = 0, BA0 = 0 and retains the stored information until it is programmed again

or the device loses power. N ot programming the mode register upon initia lization will

result in default settings which may not be desired. Outputs are guaranteed High-Z

after the LMR command is issued. Outputs should be High-Z already before the LMR

command is issued.

13. Wait at least tMRD time, during which only NOP or DESELECT commands are

allowed.

At this point the DRAM is ready for any valid command.

Note: If desired, more than two AUTO REFRESH commands can be issued in the sequence.

After steps 9 and 10 are complete, repeat them until the desired number of AUTO

REFRESH + tRFC loops is achieved.

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512Mb: x4, x8, x16 SDRAM

Mode Register

The mode register is used to define the specific mode of operation of the SDRAM. This

definition includes the selection of BL, a burst type, CL, an operating mode, and a write

burst mode, as shown in Figure5 on page 14. The mode register is programmed via the

LO AD MODE REGISTER command and will retain the stored information until it is

programm ed again or the device loses power.

Mode r egister bits M0–M2 specify BL, M3 specifies the type of burst (sequential or inter-

leaved), M4–M6 specify CL, M7 and M8 specify the operating mode, M9 specifies the

write burst mode, and M10 and M11 are reserved for future use. Address A12 (M12 ) is

undefined but should be driven LOW during loading of the mode register.

The mode regi ster must be loaded when all banks are idle, and the controller must wait

the specified time before initiating the subsequent operation. Violating either of these

requirements will result in unspecified operation.

Burst Length (BL)

Re ad and write access es to the SDRAM ar e bur st oriented, wi th BL being progr ammable,

as shown in Figure5 on page 14. BL determines the maximum number of column loca-

tions that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4,

or 8 locations ar e available for b oth the sequenti al and the interleave d burst types , and a

full-page burst is available for the sequential type . The full-page burst is used in

conjunction with the BURST TERMINATE command to generate arbitrary burst lengths.

Re served states should not be used because unknown operation or incompatibility with

future versions may result.

When a READ or WRITE command is issued, a block of columns equal to BL is effectively

selected. All accesses for that burst take place within this block, meaning that the burst

will wrap within the block if a boundary is reached. The block i s uniquely selected b y A1–

A9, A11, A12 (x4); A1–A9, A11 (x8); or A1–A9 (x16) when BL = 2; by A2–A9, A11, A12 (x4);

A2–A9, A11 (x8) or A2–A9 (x16) when the BL = 4; and by A3–A9, A11, A12 (x4); A3–A9, A11

(x8) or A3–A9 (x16) when the BL = 8. The remaining (least significant) address bit(s) is

(are) used to select the starting location within the block. Full-page bursts wrap within

the page if the boundary is reached.

Burst Type

Accesses wi thin a given burst may be programmed either to be sequential or interleaved;

this is referred to as the burst type and is selected via bit M3.

The ordering of accesses within a burst is determined by BL, the burst type and the

starting column address, as shown in Table 4 on page 15.

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512Mb: x4, x8, x16 SDRAM

Figure 5: Mode Register Definition

Notes: 1. Should program M12, M11, M10 = “0, 0, 0” to ensure compatibility with future devices.

M3 = 0

Reserved

Full Page

M3 = 1

Reserved

Operating Mode

Standard operation

All other states reserved

–

Defined

–

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

Burst Length

Burst LengthCAS Latency BT

A9 A7 A6 A5 A4 A3

A8 A2 A1 A0

Mode Register (Mx)

Address Bus

976543

8210

M6-M0

M8 M7

Op Mode

A10

A11

Reserved1WB

Write Burst Mode

Programmed burst length

Single location access

A12

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512Mb: x4, x8, x16 SDRAM

Notes: 1. For full-page accesses: y = 4,096 (x4); y = 2,048 (x8); y = 1,024 (x16).

2. For BL = 2, A1–A9, A11, A12 (x4); A1–A9, A11 (x8); or A1–A9 (x16) select the block-of-two

burst; A0 selects the st arting column within the block.

3. For BL = 4, A2–A9, A11, A12 (x4); A2–A9, A11 (x8); or A2–A9 (x16) select the block-of-four

burst; A0–A1 select the starting column within the block.

4. For BL = 8, A3–A9, A11, A12 (x4); A3–A9, A11 (x8); or A3–A9 (x16) select the block-of-eight

burst; A0–A2 select the starting column within the block.

5. For a full-page burst, the full row is selected and A0–A9, A11, A12 (x4); A0–A9, A11 (x8); or

A0–A9 (x16) select the starting column.

6. Whenever a boundary of the block is reached within a given sequence above, the following

access wraps within the block.

7. For BL = 1, A0–A9, A11, A12 (x4); A0–A9, A11 (x8); or A0–A9 (x16) select the unique column

to be accessed, and mode register bit M3 is ignored.

CAS Latency (CL)

CL is the delay, in clock cycles, between the registration of a READ command and the

availability of the first pi ece of output data. The latency can be set to two or three clocks.

If a READ command is registered at clock edge n and the latency is m clocks, the data will

be available by clock edge n + m. The DQs will start driving as a result of the clock edge

one cycle earlier ( n + m - 1), and pro vided that the relevant access times ar e met, the data

will be val id b y clock edge n + m. For example, assuming that the clock cycle time is such

that all relevant access times are met, if a READ command is registered at T0 and the

Table 4: Burst Definition

Burst

Length Starting Column

Address

Order of Accesses Within a Burst

Type = Sequential Type = Interleaved

2––A0

––0 0-1 0-1

––1 1-0 1-0

4 – A1 A0

– 0 0 0-1-2-3 0-1-2-3

– 0 1 1-2-3-0 1-0-3-2

– 1 0 2-3-0-1 2-3-0-1

– 1 1 3-0-1-2 3-2-1-0

8 A2A1A0

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7

0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6

0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4

1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3

1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2

1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1

1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

Full

page (y) n = A0–A12/11/9

(location 0–y) Cn, Cn + 1,

Cn + 2

Cn + 3,

Cn + 4…,

…Cn - 1,

Cn…

Not supported

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512Mb: x4, x8, x16 SDRAM

latency is programmed to two clocks, the DQs will start driving after T1 and the data will

be valid b y T2, as shown in Figur e 6. Table 5 indicates the operating fr equencies at whic h

each CL setting can be use d.

Reserved states should not be used as unkno wn operation or incompatibility with future

versions may result.

Figure 6: CAS Latency

Operating Mode

The normal operating mode is selected by setting M7 and M8 to zero; the other comb i-

nations of values for M7 and M8 are reserved for future use and/or test modes. The

programmed burst length applies to both READ and WRITE bursts.

Test modes and reserved states should not be used because unknown operation or

incompatibility with future versions may result.

WRITE Burst Mode

When M9 = 0, BL programmed via M0–M2 applies to both READ and WRITE bursts;

when M9 = 1, the programmed burst length appli es to READ bursts, but write accesses

are single-location (nonburst) accesses.

Table 5: CAS La tency

Speed

Allowable Operating

Frequency (MHz)

CL = 2 CL = 3

-7E ≤ 133 ≤ 143

-75 ≤ 100 ≤ 133

CLK

T2T1 T3T0

CL = 3

OUT

tOH

COMMAND NOPREAD

tAC

NOP

Don’t Care

Undefined

CLK

T2T1 T3T0

CL = 2

OUT

tOH

COMMAND

NOPREAD

tAC

NOP

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512Mb: x4, x8, x16 SDRAM

Commands

Commands Table 6 provides a quick reference of available commands. This is followed by a written

description of each command. Three additional Truth Tables appear in the Operations

section, beginning on page 35; these tabl es provide current state/next state information.

Notes: 1. CKE is HIGH for all commands shown except SELF REFRESH.

2. A0–A11 define the op-code written to the mode register, and A12 should be driven LOW.

3. A0–A12 provide row addr ess, and BA0, BA1 determine which bank is made active.

4. A0–A9, A11, A12 (x4); A0–A9, A11 (x8); or A0–A9 (x16) provide column address; A10 HIGH

enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto pre-

charge feature; BA0, BA1 determine which bank is being read from or written to.

5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged

and BA0, BA1 are “Don’t Care.”

6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.

7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except

for CKE.

8. Activates or deactivat es the DQs during WRITEs (zero-clock delay) and READs (two-clock

delay).

COMMAND INHIBIT

The COMMAND INHIBIT function pr ev ents new commands from being executed b y the

SDRAM, regardless of whether the CLK signal is enable d. The SDRAM is effectivel y dese-

lected. Operations alre ady in progress are not affected.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM that is

selected (CS# is L O W). This prevents unwanted c ommands from being r egister ed duri ng

idle or wait states. Operations already in progress are not affected.

Table 6: Truth Table 1 – Commands and DQM Operation

Notes 1–2 apply to entire table; notes appear below

Name (Function) CS# RAS# CAS# WE# DQM Address DQs Notes

COMMAND INHIBIT (NOP) HXXXX X X

NO OPERATION (NOP) LHHHX X X

ACTIVE (Select bank and act iva t e ro w) LLHHXBank/rowX 3

READ (Select bank and column, and start READ burst) LHLHL/H

8Bank/col X 4

WRITE (Select bank and column, and start WRITE

burst) L H L L L/H8Bank/col Valid 4

BURST TERMINATE LHHLX X Active

PRECHARGE (Deactivate row in bank or banks) LLHLXCode X 5

AUTO REFRESH or SELF REFRESH

(Enter self refresh mode) LLLHX X X6, 7

LOAD MODE REGISTER LLLLXOp-codeX 4

Write enable/output enable ––––L – Active8

Write inhibit/output High-Z ––––H – High-Z8

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512Mb: x4, x8, x16 SDRAM

Commands

LOAD MODE REGISTER

The mode register is loaded via inputs A0–A11 (A12 should be driven LOW). See “Mode

all banks are idle, and a subsequent executable command cannot be issued until tMRD

is met.

ACTIVE

The ACTIVE command is used to open (or activate) a row in a particular bank for a

subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address

provided on inputs A0–A12 s elec ts the row. This row remains active (or open) for

accesses until a PRECHARGE command is issued to that bank. A PRECHARGE

command must be issued before opening a different row in the same bank.

READ

The READ command is used to initiate a burst r ead access to an activ e row. The value on

the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A9, A11,

A12 (x4); A0–A9, A11 (x8); or A0–A9 (x16) selects the starting column location. The value

on input A10 determines whether auto precharge is used. If auto precharge is selected,

the row being accessed will be precharged at the end of the READ burst; if auto

precharge is not selected, the row will remain open for subsequent accesses. Read data

appears on the DQs subject to the logic level on the DQM inputs two clocks earlier. If a

given DQM signal was registered HIGH, the corresponding DQs will be High-Z two

clocks later; if the DQM signal was registered LOW, the DQs will provide valid data.

WRITE

The WRITE command is used to initiate a burst write access to an active row. The value

on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A9, A11,

A12 (x4); A0–A9, A11 (x8); or A0–A9 (x16) selects the starting column location. The value

on input A10 determines whether auto precharge is used. If auto precharge is selected,

the row being accessed will be precharged at the end of the WRITE burst; if auto

precharge is not selected, the row will remain open for subsequent accesses. Input data

appearing on the DQs is written to the memory array subject to the DQM input logic

level appeari n g c oinc id ent with the data. If a given DQM signal is r egister ed LOW, the

corresponding data will be written to memory; if the DQM signal is registered HIGH, the

corresponding data inputs will be ignored, and a WRITE will not be executed to that

byte/column location.

PRECHARGE

The PRECHARGE command is used to deactivate the open row in a particular bank or

the open row in all banks. The bank(s) will be available for a subsequent row access a

specifie d time (tRP) after the PRECHARGE command is issued. Input A10 determines

whether one or all banks ar e to be precharged, and in the case where only one bank is to

be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as

“Don’t Care.” After a bank has been precharged, it is in the idle state and must be acti-

vated prior to any READ or WRITE commands being issued to that bank.

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512Mb: x4, x8, x16 SDRAM

Commands

Auto Precharge

Auto precharge is a feature that performs the same individual-bank PRECHARGE func-

tion described above, without requiring an explicit command. This is accomplished by

using A10 to enable auto precharge in conjunction with a specifi c REA D or WRITE

command. A PRECHARGE of the bank/row that is addressed with the READ or WRITE

command is automatically performed upon completion of the READ or WRITE burst,

except in the full-page burst mode , wher e auto prechar ge does not apply. Auto pr echarge

is nonpersistent in that it is ei ther enabled or disabled for each individual REA D or

WRITE command.

Auto precharge ensures that the precharge is initiated at the earliest valid stage within a

burst. The user must not issue another command to the same bank until the precharge

time (tRP) is completed. This is determined as if an explicit PRECHARGE command was

issued at the earliest possible time, as described for each burst type in the “Operations”

section on page 20.

BURST TERMINATE

The BURST TERMINATE command is used to truncate either fixed-length or full-page

bursts. The most recently re gistered READ or WRITE command prior to the BURST

TERMINATE command will be trunca ted, as shown in the “Operations” section on

page 20. The BURST TERMINATE command does not precharge the row; the row will

remain open until a PRECHARGE command is issued.

AUTO REFRESH

AUTO REFRESH is used during normal operation of the SDRAM and is analogous to

CAS#-BEFORE-RAS# (CBR) REFRESH in conventional DRAMs. This command is

nonpersistent, so it must be issue d each time a refresh is required. All activ e banks must

be PRECHARGED prior to issuing an AUTO REFRESH command. The AUTO REFRESH

command should not be issued until the minimum tRP has been met after the

PRECHARGE command as shown in the “Operations” section on page 20.

The addressing is generated by the internal refresh controller. This makes the address

bits “Don’t Care” during an AUTO REFRESH command. The 512Mb SDRAM requires

8,192 AUTO REFRESH cycles every 64ms (tREF), regardless of width option. Providing a

distributed AUTO REFRESH command every 7.81µs will meet the refr esh requirement

and ensure that each row is refreshed. Alternatively, 8,192 AUTO REFRESH commands

can be issued in a burst at the minimum cycle rate (tRC), once every 64ms.

SELF REFRESH

The SELF REFRESH co mm and can be use d to retain data in the SDRAM, even if the rest

of the system is powered down. When in the self r efresh mode, the SDRAM retains data

without external clo ck ing. The SELF REF RESH com m and is initiated like an AUTO

REFRESH command except CKE is disabled (LOW). After the SELF REFRESH command

is registered, all the inputs to the SDRAM become “Don’t Care” with the exception of

CKE, which must remain LOW.

After self refr esh mode is engaged, the SDRAM provides its own internal clocking,

causing it to perform its own AUTO REFRESH cycles. The SDRAM must remain in self

refresh mode for a minimum period equal to tRAS and may remain in self refresh mode

for an indefinite period beyond that.

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512Mb: x4, x8, x16 SDRAM

Operations

The procedur e for exit ing self r efresh requir e s a sequence of c ommands . Fir st, CLK must

be stable (stable clock is defined as a signal cycling within timing constraints specified

for the clock pin) prior to CKE going back HIGH. When CKE is HIGH, the SDRAM must

have NOP commands issued (a minimum of two clocks ) for tXSR because time is

required for the completion of any internal refresh in progress.

Upon exiting the self refresh mode, AU TO REFRESH commands must be issued every

7.81µs or less as both SELF REFRESH and AUTO REFRESH utilize the row refresh

counter.

Operations

Bank/Row Activation

Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row

in that bank must be “opened.” This is accomplished via the ACTIVE command, which

selects both the bank and the row to be activated (see Figure 7).

After opening a ro w (issuing an A CTIVE command), a RE AD or WRITE command may be

issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by

the clock period and rounded up to the next whole number to determine the earliest

clock edge after the ACTIVE command on which a READ or WRITE command can be

entered. For example, a tRCD specification of 20ns with a 125 MHz clock (8ns period)

results in 2.5 clocks, rounded to 3. This is reflected in Figure8 on page 21, which covers

any case where 2 < tRCD (MIN)/tCK ≤ 3 (the same procedure is used to convert other

specificati o n limits from time units to clock cycles ). A subsequent ACTIVE command to

a different r ow in the same bank can only be issued after the previous active row has

been “closed” (precharged). The minimum time interval between successi ve A CTIVE

commands to the same bank is defined by tRC.

Figure 7: Activating a Specific Row In a Specific Bank

CS#

WE#

CAS#

RAS#

CKE

CLK

A0–A12 ROW

ADDRESS

Don’t Care

HIGH

BA0, BA1 BANK

ADDRESS

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512Mb: x4, x8, x16 SDRAM

Operations

Figure 8: Example Meeting tRCD (MIN) when 2 < tRCD (MIN)/tCK ≤ 3

READs

READ bursts are initiated with a READ command, as shown in Figure9.

The starting column and bank addresses are provided with the READ command, and

auto precharg e either i s enabled or disabled for that burst access. If auto precharge is

enabled, the row being accessed is precharged at the completion of the burst. For the

generic READ commands used in the following illustrations, auto precharge is disabled.

During READ bursts, the valid data-out element from the starting column address will

be available following CL after the READ command. Each subsequent data-out element

will be valid by the next positive clock edge . Figure 10 on page 22 shows ge neral timing

for each possible CL setting.

A subsequent ACTIVE command to another bank can be issued while the first bank is

being accessed, which resul ts in a r eduction of total r o w-access o verhead. The minimum

time interval between successive ACTIVE commands to different banks is defined by

tRRD.

Figure 9: READ Command

CLK

T2T1 T3T0

COMMAND NOPACTIVE READ or

WRITE

NOP

RCD

Don’t Care

CS#

WE#

CAS#

RAS#

CKE

CLK

COLUMN

ADDRESS

A0–A9, A11, A12: x4

A0–A9, A11: x8

A0–A9: x16

A10

BA0, BA1

Don't Care

HIGH

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

BANK

ADDRESS

A12: x8

A11, A12: x16

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512Mb: x4, x8, x16 SDRAM

Operations

Figure 10: CAS Latency

Upon completion of a burst, assuming no other commands have been initiated, the DQs

will go H igh-Z . A full -page burst wi ll conti nue until terminated (at the end of the page, it

will wrap to the start address and continue). Data from any READ burst may be trun-

cated with a subsequent READ command, and data from a fixed-length READ burst may

be immediatel y foll owed by data from a READ comm and .

In either case, a continuous flow of data can be maintained. The first data element from

the new burst either follo ws the last element of a completed burst or the last desir ed data

element of a longer burst that is being truncated. The new READ command should be

issued x cycles before the clock edge at which the last de sired data element is valid,

where x = CL - 1. This is shown in Figure10 for CL = 2 and CL = 3; data element n + 3 is

either the last of a burst of four or the last desired of a longer burst.

The 512Mb SDRAM uses a pipelined architecture and theref ore does not require the 2n

rule associated with a prefetch architecture. A READ command can be initiated on any

clock cycle following a previous READ command. Ful l-spe ed random read accesses can

be performed to the same bank, as shown in Figur e12 on page 24, or each subsequent

READ may be performed to a different bank.

CLK

T2T1 T3T0

CL = 3

OUT

tOH

COMMAND NOPREAD

tAC

NOP

Don’t Care

Undefined

CLK

T2T1 T3T0

CL = 2

OUT

tOH

COMMAND NOPREAD

tAC

NOP

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512Mb: x4, x8, x16 SDRAM

Operations

Figure 11: Consecutive READ Bursts

Note: Each READ command may be to any bank. DQM is LOW.

Don’t Care

CLK

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOP

BANK,

COL n

NOP

BANK,

COL b

OUT

n + 1 D

OUT

n + 2 D

OUT

n + 3 D

OUT

READ

x = 1 cycle

CL = 2

CLK

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOP

BANK,

COL n

NOP

BANK,

COL b

OUT

n + 1 D

OUT

n + 2 D

OUT

n + 3 D

OUT

READ NOP

x = 2 cycles

CL = 3

Transitioning Data

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512Mb: x4, x8, x16 SDRAM

Operations

Figure 12: Random READ Accesses

Note: Each READ command may be to any bank. DQM is LOW.

Data from any READ burst may be truncated with a subsequent WRITE command, and

data from a fixed-length READ burs t may be immediately followed by data from a

WRITE command (subject to bus turnaround limitations). Th e WRI TE burst may be

initiated on the clock edge immediately following the last (or last desired) data element

from the READ burst, provided that I/O contention can be avoided. In a given system

design, ther e may be a possibility that the device driving the input data will go Low-Z

before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur

between the last read data and the WRITE command.

The DQM input is used to avoid I/O contention, as sho wn in Figure 13 on page 25 and

Figure14 on page 25. The DQ M si gnal must be asser ted (H IGH ) at le as t tw o clo cks prior

to the WRITE command (DQM latency is two clocks for output buffers) to suppress data-

out from the READ. After the WRITE command is registered, the DQs will go High-Z (or

remai n High-Z), regardless of the state of the DQM signal, pr ovided the DQM was active

on the clock just prior to the WRITE command that truncated the READ command. If

not, the second WRITE will be an invalid WRITE. For example, if DQM was LOW during

T4 in Figure14 on page 25, then the WRITEs at T5 and T7 would be valid, while the

WRITE at T6 would be invalid.

CLK

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP

BANK,

COL n

Don’t Care

OUT

READ READ READ NOP

BANK,

COL aBANK,

COL xBANK,

COL m

CLK

OUT

T2T1 T4T3 T5T0

COMMAND

ADDRESS

READ NOP

BANK,

COL n

OUT

READ READ READ NOP

BANK,

COL aBANK,

COL xBANK,

COL m

CL = 2

CL = 3

Transitioning Data

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512Mb: x4, x8, x16 SDRAM

Operations

The DQM signal must be de-asserted prior to the WRITE command (DQM latency is

zero clocks for input buffers) to ensure that the written data is not masked. Figure 13

shows the case where the clock frequency allows for bus contention to be avoided

without adding a NOP cycle, and Figure14 shows the case where the additional NOP is

needed.

Figure 13: READ-to-WRITE

Note: A CL = 3 is used for illustration. The READ command may be to any bank, and the WRITE

command may be to any bank. If a burst of 1 is used, then DQM is not required.

Figure 14: READ-to-WRITE with Extra Clock Cycle

Note: CL = 3 is used for illustration. The READ command may be to any bank, and the WRITE

command may be to any bank.

A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE

command to the same bank (provided that auto pr echarge was not activated), and a full-

page burst may be truncated with a PRECHARGE command to the same bank. The

PRECHAR GE command should be issued x cycles before the clock edge at which the last

desired data element is valid, where x = CL - 1. This is shown in Figure 15 on page 26 for

Don’t Care

READ NOP NOP WRITENOP

CLK

T2T1 T4T3T0

DQM

OUT

COMMAND

ADDRESS

BANK,

COL nBANK,

COL b

tDS

tHZ

tCK

Transitioning Data

Don’t Care

READ NOP NOPNOP NOP

DQM

CLK

OUT

T2T1 T4T3T0

COMMAND

ADDRESS

BANK,

COL n

WRITE

BANK,

COL b

tHZ

Transitioning Data

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512Mb: x4, x8, x16 SDRAM

Operations

each possible CL; data element n + 3 is either the last of a burst of four or the last desired

of a longer burst. Following the PRECHARGE command, a subsequent command to the

same bank cannot be issued until tRP is met. Note that part of the row precharge time is

hidden during the access of the last data element(s).

In the case of a fixed-length burst being executed to completion, a PRECHARGE

command issued at the optimum time (as desc ribed abov e) provi des the same operation

that would result from the same fixed-length burst with auto precharge. The disadvan-

tage of the PRECHARGE command is that it requires that the command and address

buses be available at the appropriate time to issue the command; the advantage of the

PRECHARG E command is that it can be used to truncate fixed-leng th or full-page bursts .

Full-page READ bursts can be truncated with the BURST TERMINATE command, and

fixed-length READ bursts may be truncated with a BURST TERMINATE command,

provided that auto precharge was not activated. The BURST TERMINATE command

should be issued x cycles before the clock edge at which the last desired data element is

valid, where x = CL - 1. This is shown in Figure16 on page 27 for each possible CL; data

element n + 3 is the last desired data element of a longer burst.

Figure 15: READ-to-PRECHARGE

DON’T CARE

CLK

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOPNOP

OUT

n + 1 D

OUT

n + 2 D

OUT

n + 3

PRECHARGE ACTIVE

tRP

NOTE: DQM is LOW.

CLK

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOPNOP

OUT

n + 1 D

OUT

n + 2 D

OUT

n + 3

PRECHARGE ACTIVE

tRP

X = 1 cycle

CAS Latency = 2

CAS Latency = 3

X = 2 cycles

BANK a,

COL nBANK a,

ROW

BANK

(a or all)

BANK a,

COL nBANK a,

ROW

BANK

(a or all)

TRANSITIONING DATA

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512Mb: x4, x8, x16 SDRAM

Operations

Figure 16: Terminating a READ Burst

Note: DQM is LOW.

CLK

DQ DOUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOP

BANK,

COL n

NOP

DOUT

n + 1 DOUT

n + 2 DOUT

n + 3

BURST

TERMINATE NOP

Don’t Care

CLK

DQ DOUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP

BANK,

COL n

NOP

DOUT

n + 1 DOUT

n + 2 DOUT

n + 3

BURST

TERMINATE NOP

x = 1 cycle

CL = 2

CL = 3

x = 2 cycles

Transitioning Data

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512Mb: x4, x8, x16 SDRAM

Operations

WRITEs

WRITE bursts are initiated with a WRITE command, as shown in Figure17.

The starting column and bank addresses are provided with the WRITE command, and

auto prec harge i s either enabled or disabled for that acc ess . If auto pr e charge is enab led,

the row being accessed is precharged at the completion of the burst. For the generic

WRITE commands us ed in the fol lowing illustrations, auto precharge is disabled.

During WRITE bursts, the first valid data-in element will be registered coincident with

the WRITE command. Subsequent data elements will be registered on each successive

positive clock edge. Upon completion of a fixed-length burst, assuming no other

commands have been initiated, the DQs will remain H ig h-Z and any additional input

data will be ignored (see Figure18 on page 29). A full-page burst will continue until

terminated (at the end of the page, it will wrap to the start address and continue). Data

for any WRITE burst may be truncated with a subsequent WRITE command, and data

for a fixed-length WRITE burst may be immediately followed by data for a WRITE

command. The new WRITE command can b e issued on any c lock follo wi ng the pr evious

WRITE command, and the data provided coincident with the new command applies to

the new command. An example is shown in Figure19 on page 29. Data n + 1 is either the

last of a burst of two or the last desired of a longer burst. The 512Mb SDRAM uses a pipe-

lined architecture and therefore does not require the 2n rule associated with a prefetch

architec tur e. A WRITE com mand can be initiated on any clock cycle fol lo wing a pr evious

WRITE command. Full-speed random write accesses within a page can be performed to

the same bank, as shown in Figure20 on page 30, or each subsequent WRITE may be

performed to a different bank.

Figure 17: WRITE Command

CS#

WE#

CAS#

RAS#

CKE

CLK

COLUMN

ADDRESS

A10

Don’t Care

HIGH

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

A0–A9, A11, A12: x4

A0–A9, A11: x8

A0–A9: x16

A12: x8

A11, A12: x16

BA0, BA1

BANK

ADDRESS

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512Mb: x4, x8, x16 SDRAM

Operations

Figure 18: WRITE Burst

Note: BL = 2. DQM is LOW.

Data for any WRITE burst may be truncated with a subsequent READ command, and

data for a fixed -length WRITE burst m ay be imme diately fol lowed b y a REA D command.

After the READ command is registered, the data inputs will be ignor ed, and WRITEs will

not be executed. An example is shown in Figure 21 on page 30. Data n+ 1 is either the

last of a burst of two or the last desired of a longer burst.

Figure 19: WRITE-to-WRITE

Note: DQM is LOW. Each WRITE command may be to any bank.

CLK

DQ DIN

T2T1 T3T0

COMMAND

ADDRESS

NOP NOP

Don’t Care

WRITE

DIN

n + 1

NOP

BANK,

COL n

Transitioning Data

CLK

T2T1T0

COMMAND

ADDRESS

NOPWRITE WRITE

BANK,

COL nBANK,

COL b

n + 1 D

Don’t Care

Transitioning Data

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Operations

Figure 20: Random WRITE Cycles

Note: Each WRITE command may be to any bank. DQM is LOW.

Figure 21: WRITE-to-READ

Note: The WRITE or READ commands may be to any bank. DQM is LOW.

Data for a fixed-length WRITE burst may be followed by, or truncated with, a

PRECHARGE command to the same bank (provided that auto pr echarge was not acti-

vated), and a full-page WRITE burst may be truncated with a PRECHARGE command to

the same bank. The PRECHARGE command should be issued tWR after the clock edge at

which the last desired input data element is registered. The auto precharge mode

requires a tWR of at least one clock plus time, regardless of frequency. In addition, when

truncating a WRITE burst, the DQM signal must be used to mask input data for the clock

edge prior to, and the clock edge coincident with, the PRECHARGE command. An

example is sho wn in Fi gur e22 on page 31. Data n+ 1 is either the last of a burst of two or

the last desir ed of a longer burst. Following the PRECHARGE command, a subsequent

command to the same bank cannot be issued until tRP is met. The precharge can be

issued coinci de nt w it h th e firs t coi ncident second clock (Figure 22 on pag e 31). In the

case of a fixed-length burst being executed to completion, a PRECHARGE command

issued at the optimum time (as described above) provides the same operation that

would result from the same fixed-length burst with auto precharge. The disadvantage of

Don’t Care

CLK

T2T1 T3T0

COMMAND

ADDRESS

WRITE

BANK,

COL n

WRITE WRITE WRITE

BANK,

COL aBANK,

COL xBANK,

COL m

Transitioning Data

Don’t Care

CLK

T2T1 T3T0

COMMAND

ADDRESS

NOPWRITE

BANK,

COL n

n + 1 D

OUT

READ NOP NOP

BANK,

COL b

NOP

OUT

b + 1

T4 T5

Transitioning Data

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512Mb: x4, x8, x16 SDRAM

Operations

the PRECHARGE command is that it requires that the command and address buses be

available at the appropriate time to issue the command; the advantage of the

PRECHARG E command is that it can be used to truncate fixed-leng th or full-page bursts .

Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE

command. When truncating a WRITE burst, the inpu t data applied coincident with the

BURST TERMINATE command will be ignored. The last data written (provided that

DQM is LOW at that time) will be the input data applied one clock previous to the

BURST TERMINATE command. This is shown in Figur e23 on page 32, where data n is

the last desired data element of a longer burst.

Figure 22: WRITE-to-PRECHARGE

Note: DQM could remain LOW in this example if the WRITE burst is a fixed length of two.

Don’t Care

DQM

CLK

T2T1 T4T3T0

COMMAND

ADDRESS BANK a,

COL n

NOPWRITE

PRECHARGE

NOPNOP

n + 1

ACTIVE

tRP

BANK

(a or all)

BANK a,

ROW

DQM

COMMAND

ADDRESS BANK a,

COL n

NOPWRITE

PRECHARGE

NOPNOP

n + 1

ACTIVE

tRP

BANK

(a or all)

BANK a,

ROW

NOP

tWR @ tCLK > 15ns

tWR = tCLK < 15ns

Transitioning Data

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Operations

Figure 23: Terminating a WRITE Burst

Note: DQMs are LOW.

PRECHARGE

The PRECHARGE command shown in Figure 24 is used to deactivate the open row in a

particular bank or the open row in all banks. The bank(s) will be available for a subse-

quent row access some specified time (tRP) after the PRECHARGE command is issued.

Input A10 determines whether one or all banks are to be precharged, and in the case

where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all

banks are to be pr echarged, inputs BA0, BA1 ar e tr eated as “ Don’t Car e. ” After a bank has

been pre charged, it is in the idle state and must be activated prior to any READ or WRITE

commands being issued to that bank.

Figure 24: PRECHARGE Command

Don’t Care

CLK

T2T1T0

COMMAND

ADDRESS BANK,

COL n

WRITE BURST

TERMINATE NEXT

COMMAND

DIN

(ADDRESS)

(DATA)

Transitioning Data

Don’t Care

CS#

WE#

CAS#

RAS#

CKE

CLK

A10

HIGH

All Banks

Bank Selected

A0–A9, A11, A12

BA0, BA1

BANK

ADDRESS

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512Mb: x4, x8, x16 SDRAM

Operations

Power-Down

Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND

INHIBIT when no accesses are in progress. If power-down occurs when all banks are

idle, this mode is referred to as precharge power -down; if power-down occurs when

there is a ro w activ e in any bank, this mode is referred to as active power-down. Entering

power-down deactivates the input and output buffers, excluding CKE, for maximum

power savings while in standby. The device may not remain in the power-down state

longer than the refresh period (64ms) since no refresh operations are performed in this

mode.

The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE

HIGH at the desired clock edge (meeting tCKS). See Figure25.

Figure 25: Power-Down

Clock Suspend

The clock suspend mode occurs when a column access/burst is in progress and CKE is

registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing”

the synchronous logic.

For each positive clock edge on which CKE is sampled LOW, the next internal positive

clock edge is suspended. Any command or data pr esent on the input pins at the time of a

suspended internal clock edge is ignored; any data present on the DQ pins remains

driven; and burst counters are not incremented, as long as the clock is suspended (see

examples in Figures 26 and 27 on page 34).

Clock suspend mode is exited by registering CKE HIGH; the internal clock and related

operation will resume on the subsequent positive clock edge.

Don’t Care

tRAS

tRCD

tRC

All banks idle Input buffers gated off

Exit power-down mode.

()()

tCKS >tCKS

COMMAND

NOP ACTIVE

Enter power-down mode.

NOP

CLK

CKE

()()

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512Mb: x4, x8, x16 SDRAM

Operations

Figure 26: CLOCK SUSPEND During WRITE Burst

Note: BL = 4 or greater. DM is LOW.

Figure 27: CLOCK SUSPEND During READ Burst

Note: CL = 2, BL = 4 or greater. DQM is LOW.

Burst READ/Single WRITE

The burst read/single write mode is entered by progra mming the write burst mode bit

(M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the

access of a single column location (burst of one), regardless of the programmed burst

length. READ commands access columns according to the programmed burst length

and sequence, just as in the normal mode of operation (M9 = 0).

Don’t Care

COMMAND

ADDRESS

WRITE

BANK,

COL n

NOPNOP

CLK

T2T1 T4T3 T5T0

CKE

INTERNAL

CLOCK

NOP

n + 1 D

n + 2

Transitioning Data

Don’t Care

CLK

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP

BANK,

COL n

NOP

OUT

n + 1 D

OUT

n + 2 D

OUT

n + 3

CKE

INTERNAL

CLOCK

NOP

Transitioning Data

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512Mb: x4, x8, x16 SDRAM

Operations

Concurrent Auto Precharge

An access command to (READ or WRITE) another bank while an access command with

auto precharge enabled is executing is not allowed b y SDRAMs, unless the SDRAM

supports con current auto precharge. Micron SDRAMs support concurrent auto

precharge. Four cases where concurrent auto precharge occurs are defined below.

READ with Auto Precharge

• Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-

rupt a READ on bank n, CL later. The PRECHARGE to bank n will begin when the

READ to bank m is registered (see Figure 28).

• Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will

interrupt a READ on bank n when register ed. DQM s hould be us ed two clocks prior to

the WRITE command to prevent bus contention. The PRECHARGE to bank n will

begin when the WRITE to bank m is regi stered (see Figur e29 on page 36).

Figure 28: READ with Auto Precharge Interrupted by a READ

Note: DQM is LOW.

CLK

DOUT

T2T1 T4T3 T6T5T0

COMMAND

READ - AP

BANK nNOP NOPNOPNOP

DOUT

a + 1 DOUT

dDOUT

d + 1

NOP

BANK n

CL = 3 (BANK m)

BANK m

ADDRESS

Idle

NOP

BANK n,

COL aBANK m,

COL d

READ - AP

BANK m

Internal

States t

Page Active READ with Burst of 4 Interrupt Burst, Precharge

Page Active READ with Burst of 4 Precharge

RP - BANK ntRP - BANK m

CL = 3 (BANK n)

Transitioning Data Don’t Care

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Operations

Figure 29: READ with Auto Precharge Interrupted by a WRITE

Notes: 1. DQM is HIGH at T2 to prevent DOUT - a + 1 from contending with DIN - d at T4.

WRITE with Auto Precharge

• Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-

rupt a WRITE on bank n when registered, with the data-out appearing CL later. The

PRECHAR GE to bank n wil l begin after tWR is met, where tWR begins when the READ

to bank m is registered. The last valid WRITE to bank n will be data-in registered one

clock prior to the READ to bank m (see Figure 30).

• Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will

interrupt a WRITE on bank n when registered. The PRECHARGE to bank n will begin

after tWR is met, where tWR begins when the WRITE to bank m is registered. The last

valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank

m (see Figure 31 on page 37).

Figure 30: WRITE with Auto Precharge Interrupted by a READ

Note: DQM is LOW.

CLK

T2T1 T4T3 T6T5T0

COMMAND

NOPNOPNOPNOP

d + 1

d + 2 D

d + 3

NOP

BANK n

BANK m

ADDRESS

Idle

NOP

DQM

BANK n,

COL aBANK m,

COL d

WRITE - AP

BANK m

Internal

States

Page

Active READ with Burst of 4 Interrupt Burst, Precharge

Page Active WRITE with Burst of 4 Write-Back

RP -

BANK

ntWR -

BANK

CL = 3 (BANK n)

READ - AP

BANK n

Don’t CareTransitioning Data

OUT

Don’t Care

CLK

T2T1 T4T3 T6T5T0

COMMAND WRITE - AP

BANK nNOPNOPNOPNOP

a + 1

NOP NOP

BANK n

BANK m

ADDRESS

BANK n,

COL aBANK m,

COL d

READ - AP

BANK m

Internal

States t

Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge

Page Active READ with Burst of 4

ttRP - BANK m

OUT

d + 1

CL = 3 (BANK m)

RP - BANK n

WR - BANK n

Transitioning Data

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512Mb: x4, x8, x16 SDRAM

Operations

Figure 31: WRITE with Auto Precharge Interrupted by a WRITE

Note: DQM is LOW.

Notes: 1. CKEn is the logic state of CKE at clock edge n; CKEn - 1 was the state of CKE at the previous

clock edge.

2. Current state is the state of the SDRAM immediately prior to clock edge n.

3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COM-

MANDn.

4. All state s an d sequenc e s not shown are illegal or reserved.

5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for

clock edge n + 1 (provided that tCKS is met).

6. Exiting self refresh at clock edge n will put the device in the all banks idle state once tXSR is

met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring

during the tXSR period. A minimum of two NOP commands must be provided during tXSR

period.

7. After exiting clock suspend at clock edge n, the device will re sume op eration and reco gnize

the next command at clock edge n + 1.

Table 7: Truth Table 2 – CKE

Notes 1–4 apply to entire table; notes appear below

CKEn - 1 CKEnCurrent State COMMANDnACTIONnNotes

L L Power-do wn X Maintain power -down

Self refresh X Maintain self refresh

Clock suspend X Maintain clock suspend

L H Power-down COMMAND INHIBIT or NOP Exit power-down 5

Self refresh COMMAND INHIBIT or NOP Exit self refresh 6

Clock suspend X Exit clock suspend 7

H L All banks idle COMMAND INHIBIT or NOP Power-down entry

All Banks idle AUTO REFRESH Self refresh entry

Reading or writing WRITE or NOP Clock suspend entry

H H See Table 8 on page 38

Don’t Care

CLK

T2T1 T4T3 T6T5T0

COMMAND

WRITE - AP

BANK nNOPNOPNOPNOP

d + 1

a + 1 D

a + 2

d + 2 D

d + 3

NOP

BANK n

BANK m

ADDRESS

NOP

BANK n,

COL aBANK m,

COL d

WRITE - AP

BANK m

Internal

States

Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge

Page Active WRITE with Burst of 4 Write-Back

WR - BANK ntRP - BANK ntWR - BANK m

Transitioning Data

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512Mb: x4, x8, x16 SDRAM

Operations

Notes: 1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH (see Table 7 on page 37) and

after tXSR has been met (if the previous state was self refresh).

2. This table is bank-specific, except where noted, that is, the current state is for a specific

bank and the commands shown are those allowed to be issued to that bank when in that

state. Exceptions are covered in the notes below.

3. Current state definitions:

4. The following states must not be interrupted by a command issued to the same bank. COM-

MAND INHIBIT or NOP commands or allowable commands to the other bank should be

issued on any clock edge occurring during these states. Allowable commands to the other

bank are determi ned by its current s tate and Table 8 and according to Table 9 on page 40.

Table 8: Truth Table 3 – Current State Bank n, Command to Bank n

Notes: 1–6 apply to entire table; notes appear below and on next page

Current

State CS# RAS# CAS# WE# Command (Action) Notes

Any HXXX

COMMAND INHIBIT (NOP/continue previous operation)

LHHH

NO OPERATION (NOP/continue previous operation)

Idle L L H H ACTIVE (Select and activate row)

LLLH

AUTO REFRESH 7

LLLL

LOAD MODE REGISTER 7

LLHL

PRECHARGE 11

Row activeLHLH

READ (Select column and start READ burst) 10

LHLL

WRITE (Select column and start WRITE burst) 10

LLHL

PRECHARGE (Deactivate row in bank or banks) 8

Read

(auto

precharge

disabled)

LHLH

READ (Select column and start new READ burst) 10

LHLL

WRITE (Select column and start WRITE burst) 10

LLHL

PRECHARGE (Truncate READ burst, start PRECHARGE) 8

LHHL

BURST TER MINATE 9

Write

(auto

precharge

disabled)

LHLH

READ (Select column and start READ burst) 10

LHLL

WRITE (Select column and start new WRITE burst) 10

LLHL

PRECHARGE (Truncate WRITE burst, start PRECHARGE) 8

LHHL

BURST TER MINATE 9

Idle: The bank has been precharged, and tRP has been met.

Row active: A row in the bank has been activated, and tRCD has been met. No data

bursts/accesses and no register accesses are in progress.

Read: A READ burst has been initiated, with auto precharge disabled and has

not yet terminated or been terminated.

Write: A WRITE burst has been initiated, with auto precharge disabled, and

has not yet terminated or been terminated.

Precharging: Starts with registration of a PRECHARGE command and ends when tRP

is met. After tRP is met, the bank will be in the idle state.

Row activating: Starts with registration of an ACTIVE command and ends when tRCD is

met. After tRCD is met, the bank will be in the row active state.

Read with auto

precharge enabled: Starts with registration of a READ command with auto precharge

enabled and ends when tRP has been met. Aft er tRP is met, the bank

will be in the idle state.

Write w/auto

precharge enabled: Starts with registration of a WRITE command with auto precharge

enabled and ends when tRP has been met. Aft er tRP is met, the bank

will be in the idle state.

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512Mb: x4, x8, x16 SDRAM

Operations

5. The following states must not be interrupted by any executable command; COMMAND

INHIBIT or NOP commands must be applied on each positive clock edge during these states.

6. All state s an d sequenc e s not shown are illegal or reserved.

7. Not bank-specific; requires that all banks are idle.

8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid

state for precharging.

9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regard-

less of bank.

10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with

auto precharge enabled and READs or WRITEs with auto precharge disabled.

11. Does not affect the state of the bank and acts as a NOP to that bank.

Refreshing: Starts with registration of an AUTO REFRESH command and ends when

tRC is met. After tRC is met, the SDRAM will be in the all banks idle

state.

Accessing mode

when tMRD has been met. After tMRD is met, the SDRAM will be in the

all banks idle state.

Prechargi ng all: Starts with registration of a PRECHARGE ALL command and ends when

tRP is met. After tRP is met, all banks will be in the idle state.

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512Mb: x4, x8, x16 SDRAM

Operations

Notes: 1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH (see Table 7 on page 37) and

after tXSR has been met (if the previous state was self refresh).

2. This table describes alternate bank operation, except where noted; that is, the current state

is for bank n and the commands shown are those allowed to be issued to bank m (assuming

that bank m is in such a state that the given command is allowable). Exceptions are covered

in the notes below.

3. Current state definitions:

4. AUTO REFRESH, SELF REFRESH, and LOAD MODE REGISTER commands may only be issued

when all banks are idle.

Table 9: Truth Ta ble 4 – Current State Bank n, Command to Bank m

Notes 1–6 apply to entire table; notes appear below and on next page

Curr e n t Sta te CS# RAS# CAS# WE# Command (Action) Notes

Any H X X X COMMAND INHIBIT (NOP/continue previous operation)

LHHH

NO OPERATION (NOP/con tinue previous operation)

Idle X X X X Any command otherwise allowed to bank m

Row

activating,

active, or

precharging

LLHH

ACTIVE (Select and activate row)

LHL H

READ (Select column and start READ burst) 7

LHL L

WRITE (Select column and start WRITE burst) 7

LLHL

PRECHARGE

Read

(auto

precharge

disabled)

LLHH

ACTIVE (Select and activate row)

LHL H

READ (Select column and start new READ burst) 7, 10

LHL L

WRITE (Select column and start WRITE burst) 7, 11

LLHL

PRECHARGE 9

Write

(auto

precharge

disabled)

LLHH

ACTIVE (Select and activate row)

LHL H

READ (Select column and start READ burst) 7, 12

LHL L

WRITE (Select column and start new WRITE burst) 7, 13

LLHL

PRECHARGE 9

Read

(with auto

precharge)

LLHH

ACTIVE (Select and activate row)

LHL H

READ (Select column and start new READ burst) 7, 8, 14

LHL L

WRITE (Select column and start WRITE burst) 7, 8, 15

LLHL

PRECHARGE 9

Write

(with auto

precharge)

LLHH

ACTIVE (Select and activate row)

LHL H

READ (Select column and start READ burst) 7, 8, 16

LHL L

WRITE (Select column and start new WRITE burst) 7, 8, 17

LLHL

PRECHARGE 9

Idle: The bank has been prechar ged, and tRP has been met.

Row active: A row in the bank has been activated, and tRCD has been met. No data

bursts/accesses and no register accesses are in progress.

Read: A READ burst has been initiated, with auto precharge disabled, and has

not yet terminated or been terminated.

Write: A WRITE burst has been initiated, with auto precharge disabled, and

has not yet terminated or been terminated.

Read with auto

precharge enabled: Starts with regis tration of a READ command with auto precharge

enabled, and ends when tRP has been met. After tRP is met, the bank

will be in the idle state.

Write with auto

precharge enabled: Starts with registration of a WRITE command with auto precharge

enabled, and ends when tRP has been met. After tRP is met, the bank

will be in the idle state.

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512Mb: x4, x8, x16 SDRAM

Operations

5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank

represented by the current state only.

6. All state s an d sequenc e s not shown are illegal or reserved.

7. READs or WRITEs to bank m listed in the Command (Action) column include READs or

WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled.

8. Concurrent auto precharge: Bank n will in itiate the auto pr echarge command when its

burst has been interrupted by bank m’s burst.

9. Burst in bank n continues as initiated.

10. For a READ without auto precharge interrupted by a READ (with or without auto pre-

charge), the READ to bank m will interrupt the READ on bank n, CL later (Figure 11 on

page 23).

11. For a READ without auto precharge interrupted by a WRITE (with or without auto pre-

charge), th e WRITE to bank m will interrupt the READ on bank n when registered (Figure 13

and Figure 14 on page 25). DQM should be used one clock prior to the WRITE command to

prevent bus contention.

12. For a WRITE without auto precharge interrupted by a READ (with or without auto pre-

charge), the READ to bank m will interrupt the WRITE on bank n when registered (Figure 21

on page 30), with the data-out appearing CL later. The last valid WRITE to bank n will be

data-in registered one clock prior to the READ to bank m.

13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto pre-

charge), th e WR ITE to bank m will interru pt th e WRI T E on bank n when registered

(Figure 19 on page 29). The last valid WRITE to bank n will be data-in registered one clock

prior to the READ to bank m.

14. For a READ with auto precharge interrupted by a READ (with or without auto precharge),

the READ to bank m will interrupt the READ on bank n, CL later. The PRECHARGE to bank n

will begin when the READ to bank m is registered (Figure 28 on page 35).

15. For a READ with auto prechar ge interrupted by a WRITE (with or wit h out auto precharge),

the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be

used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE

to bank n will begin when the WRITE to bank m is registered (Figure 29 on page 36).

16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge),

the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out

appearing CL later. The PRECHARGE to bank n will begin after tWR is met, where tWR

begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-

in registered one clock prior to the READ to bank m (Figure 30 on page 36).

17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge) ,

the WRITE to bank m will interrupt the WRITE on bank n when registered. The PRECHARGE

to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is reg-

istered . The la st v al id WRITE to bank n will be data registered one clock prior to the WRITE

to bank m (Figure 31 on page 37).

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512Mb: x4, x8, x16 SDRAM

Electrical Specifications

S tresses gr eater than those listed may cause permanent damage to the device . This is a

stress r ating only, and functional operation of the device at these or any other conditions

above those indicate d in the operational sections of this spe c ification is not implie d.

Exposure to absolute maximum rating conditions for extended periods may affect reli-

ability.

Note: For further information, refer to technical note TN-00-08: Thermal Applications, available

on Micron’s Web site.

Temperature and Thermal Impedance

It is imper ative that the SDRAM device’s temperature specifications, shown in Table 11

on page 43, be maintained to ensure the junction temperatur e is in the proper operating

range to meet data sheet specifications. An important step in maintaining the proper

junction temperature is using the device’s thermal impedances correctly. The thermal

impedances are listed in Tabl e 12 on page 43 for the appl ic ab le die revision and pack-

ages being made available. The se thermal impedance values v a ry according to the

density, package, and particular design used for each device.

Incorr ectly using thermal impedances can produce significant errors. Read Micron tech-

nical note TN-00-08, “ The rmal Applications” prior to using the thermal impedance s

listed in Table 12 on page 43. To ensure the compatibility of current and future designs,

contact Micron Applications Engineering to confirm thermal impedance values. The

SDRAM device’s safe junction temperatur e range can be maintained when the TC speci-

fication is not exce eded. In applic ations wher e the device’s ambient temperatur e is too

high, use of forced air and/or heat sinks may be required to satisfy the case temperature

specifications.

Table 10: Absolute Maximum Ratings

Parameter Symbol Min Max Units Notes

VDD supply voltage relative to VSS VDD –1.0 +4.6 V

VDDQ supply voltage relative to VSS VDDQ –1.0 +4.6 V

Voltage on any pin relative to VSS VIN, VOUT, NC –1.0 +4.6 V

SDRAM device temperatures TACommercial 0 +70 °C 1

Industrial –40 +85 °C 1

Storage (plas t i c ) –55 +155 °C 1

Power dissipation – – +1 W

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Electrical Specifications

Notes: 1. MAX operating case temperature, TC, is measured in the center of the package on the top

side of the device, as shown on page 47.

2. Device functionality is not guaranteed if the device exceeds maximum TC during operation.

3. Both temperature specifications must be satisfied.

4. The case temperature should be measur ed by gluing a thermocouple to the top center of

the component. This should be done with a 1mm bead of conductive epoxy, as defined by

the JEDEC EIA/JESD51 standards. Care should be taken to ensure the thermocouple bead is

touching the case.

5. Operating ambient temperature surroun ding the package.

Figure 32: Example Temperature Test Point Location, 54-Pin TSOP: Top View

Table 11: Temperature Limits

Parameter Symbol Min Max Units Notes

Operating case temperature:

Commercial

Industrial

TC0

–40 80

°C 1, 2, 3, 4

Junction temperature:

Commercial

Industrial

TJ0

–40 85

°C 3

Ambient temperature:

Commercial

Industrial

TA0

–40 70

°C 3, 5

Peak reflow temperature TPEAK –260°C

Table 12: Summary of Thermal Impedance

Die Size

(mm2)Package Number of

Leads Test

Board

θJA θJMA θJMA θJB

(°C/W)

θJC

(°C/W)(°C/W)

0m/s (°C/W)

1m/s (°C/W)

2m/s

94 TSOP 54 2-layer 62.6 48.4 44.2 19.2 6.7

4-layer 39.2 32.3 30.6 19.3

22.22mm

11.11mm

Test point

10.16mm

5.08mm

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Electrical Specifications

Table 13: DC Electrical Characteristics And Operating Conditions

Notes 1, 5, and 6 apply to entire table; notes appear on page 47; VDD, VDDQ = +3.3V ±0.3V

Parameter/Condition Symbol Min Max Units Notes

Supply voltage VDD, VDDQ3 3.6 V

Input high voltage: Logic 1; All inputs VIH 2VDD + 0.3 V 22

Input low voltage: Logic 0; All inputs VIL –0.3 0.8 V 22

Input leakage current: Any input 0V ≤ VIN ≤ VDD

(All other pins not under test = 0V) II–5 5 µA

Output leakage current: DQs are disabled;

0V ≤ VOUT ≤ VDDQIOZ –5 5 µA

Output levels:

Output high voltage (IOUT = –4mA) VOH 2.4 – V 26

Output low voltage (IOUT = 4mA) VOL –0.4V26

Table 14: IDD Specifications and Conditions

Notes 1, 5, 6, 11, and 13 apply to entire table; notes appear on page 47; VDD, VDDQ = +3.3V ±0.3V

Parameter/Condition Symbol

Max

Units Notes-7E -75

Operating current: Active mode;

Burst = 2; READ or WRITE; tRC = tRC (MIN) IDD1 120 110 mA 3, 18, 19,

Standby current: power-down mode;

CKE = LOW; All banks idle IDD23.53.5mA29

Standby current: Active mode; CS# = HIGH;

CKE = HIGH; All banks active after tRCD met;

No accesses in progress

IDD3 45 45 mA 3, 12, 19,

Operating current: Burst mode; Page burst;

READ or WRITE; All banks active IDD4 125 115 mA 3, 18, 19,

Auto refresh current:

CS# = HIGH; CKE = HIGH

tRFC = tRFC (MIN) IDD5 255 255 mA 3, 18, 19,

29, 30

tRFC = 7.81µs IDD66 6mA

Self refresh current: CKE ≤ 0.2V Standard IDD76 6mA•

Low power (L) IDD73 3mA

Table 15: Capacitance

Note 2 applies to entire table; notes appear on page 47

Parameter Symbol Min Max Units

Input capacitance: CLK CI12.5 3.5 pF

Input capacitance: All other input-only pin s CI22.5 3.8 pF

Input/output capacitance: DQs CIO4.0 6.0 pF

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Electrical Specifications

Table 16: Electrical Characteristics and Recommended AC Operating Conditions

Notes 5, 6, 7, 8, 9, and 11 apply to entire table; notes appear on page 47

AC Characteristics

Symbol

-7E -75

Units NotesParameter Min Max Min Max

Access time from CLK (positive edge) CL = 3 tAC(3) – 5.4 – 5.4 ns 27

CL = 2 tAC(2) – 5.4 – 6 ns

Address hold time tAH 0.8 – 0.8 – ns

Address setup time tAS 1.5 – 1.5 – ns

CLK high-level width tCH 2.5 – 2.5 – ns

CLK low-level width tCL 2.5 – 2.5 – ns

Clock cycle time CL = 3 tCK(3) 7 – 7.5 – ns 23

CL = 2 tCK(2) 7.5 – 10 – ns 23

CKE hold time tCKH 0.8 – 0.8 – ns

CKE setup time tCKS 1.5 – 1.5 – ns

CS#, RAS#, CAS#, WE#, DQM hold time tCMH 0.8 – 0.8 – ns

CS#, RAS#, CAS#, WE#, DQM setup time tCMS 1.5 – 1.5 – ns

Data-in hold time tDH 0.8 – 0.8 – ns

Data-in setup time tDS 1.5 – 1.5 – ns

Data-out High-Z time CL = 3 tHZ(3) – 5.4 – 5.4 ns 10

CL = 2 tHZ(2) – 5.4 – 6 ns 10

Data-out Low-Z time tLZ 1 – 1 – ns

Data-out hold time (load) tOH 2.7 – 2.7 – ns

Data-out hold time (no load) tOHN1.8 – 1.8 – ns 28

ACTIVE-to-PRECHARGE command tRAS 37 120,000 44 120,000 ns

ACTIVE-to-ACTIVE command period tRC 60 – 66 – ns

ACTIVE-to-READ or WRITE delay tRCD 15 – 20 – ns

Refresh period (8,192 rows) tREF – 64 – 64 ms

AUTO REFRESH period tRFC 66 – 66 – ns

PRECHARGE command period tRP 15 – 20 – ns

ACTIVE bank a to ACTIVE bank b command tRRD 14 – 15 – ns

Transition time tT 0.3 1.2 0.3 1.2 ns 7

WRITE recovery time tWR 1 CLK +

7ns –1 CLK +

7.5ns ––24

14 – 15 – ns 14, 25

Exit SELF REFRESH-to-ACTIVE command tXSR 67 – 75 – ns 20

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Electrical Specifications

Table 17: AC Functional Characteristics

Notes 5, 6, 7, 8, 9, and 11 apply to entire table; notes appear below

Parameter Symbol -7E -75 Units Notes

READ/WRITE command -to-READ/WRITE command tCCD 1 1 tCK 17

CKE to clock disable or power-down entry mode tCKED 1 1 tCK 14

CKE to clock enable or power-down exit setup mode tPED 1 1 tCK 14

DQM to input data delay tDQD 0 0 tCK 17

DQM to data mask during WRITEs tDQM 0 0 tCK 17

DQM to data High-Z during READs tDQZ 2 2 tCK 17

WRITE command to input data delay tDWD 0 0 tCK 17

Data-in to ACTIVE command tDAL 4 5 tCK 15, 21

Data-in to PRECHARGE command tDPL 2 2 tCK 16, 21

Last data-in to burst STOP command tBDL 1 1 tCK 17

Last data-in to new READ/WRITE command tCDL 1 1 tCK 17

Last data-in to PRECHARGE command tRDL 2 2 tCK 16, 21

LOAD MODE REGISTER command to ACTIVE or REFRESH command tMRD 2 2 tCK 26

Data-out to High-Z from PRECHARGE command CL = 3 tROH(3) 3 3 tCK 17

CL = 2 tROH(2) 2 2 tCK 17

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Notes

Notes 1. All v o ltages referenced to VSS.

2. This parameter is sampled. VDD, VDDQ = +3.3V; f = 1 MHz, TA = 25°C; pin under test

biased at 1.4V.

3. IDD is dependent on output loading and cycle rates. Specified value s are obtained

with minimum cycle time and the outputs open.

4. Enables on-chip refresh and address counters.

5. The minimum specifications are used only to indicate cycle time at which proper

operation over the full temperature range (0°C ≤ TA ≤ 70°C for commerc ial; –40°C ≤ TA

≤ 85°C for industrial) is ensu red.

6. An initial pause of 100µs is required after power-up , followed by two AUTO REFRESH

commands, before proper device operation is ensured. (VDD and VDDQ must be pow-

ered up simultaneously. VSS and VSSQ must be at same potential.) Th e tw o AUTO

REFRESH command wake-ups should be repeated any time the tREF refresh require-

ment is exceeded.

7. AC characteristics assume tT = 1ns.

8. In addition to meeting the transition rate specification, the clock and CKE must tr an-

sit between VIH and VIL (or between VIL and VIH) in a monotonic manner.

9. Outputs measured at 1.5V with equivale nt load :

10. tHZ defines the time at which the output achieves the open circuit condition; it is not

a reference to VOH or VOL. The last valid data elemen t will meet tOH befor e going

High-Z.

11. AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced to 1.5V

crossover point. If the input transition time is longer than 1ns, then the timing is ref-

erenced at VIL (MAX) and VIH (MIN) and no longer at the 1.5V crossover point. Refer

to Micron technical note TN-48-09.

12. Other input signals are allowed to transition no more than once every two clocks and

are otherwise at valid VIH or VIL levels.

13. IDD specifications are tested after the device is properly initialized.

14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum

cycle rate.

15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at

minimum cycle rate.

16. Timing actually specified by tWR.

17. Required clocks are specified by JEDEC functionality and are not dependent on any

timing parameter.

18. The I DD curr ent will increase or decrease in a proportional amount by the amount the

frequency is altered for the test condition.

19. Address transitions average one transition every two clocks.

20. CLK must be toggled a minimum of two times during this period.

21. Based on tCK = 7.5ns for -75 and -7E.

Q50pF

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Notes

22. VIH overshoot: VIH (MA X) = VDDQ + 2V for a pulse width ≤ 3ns, and the pulse width

cannot be greater than one-thir d of the cycle rate . VIL undershoot: VIL (MIN) = –2V for

a pulse width ≤ 3ns for all inputs. VIH o vershoot for pin A12 is limited to VDDQ + 1V for

a pulse width ≤ 3ns, and the pulse width cannot be greater than one-thir d of the cycle

rate.

23. The clock frequency must remain constant (stable clock is defi ned as a signal cycling

within timing constraints specified for the clock pin) during access or precharge

states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be

used to reduce the data rate.

24. Auto precharge mode only. The prechar ge timing budget (tRP) begins 7.5ns/7ns after

the first clock delay, after the last WRITE is executed.

25. Precharge mode only.

26. JEDEC and PC100, PC133 specify three clocks.

27. tAC for -75/-7E at CL = 3 with no load is 4.6ns and is guaranteed by design.

28. Parameter guaranteed by design.

29. For -75, CL = 3, tCK = 7.5ns; for -7E, CL = 2, tCK = 7.5ns.

30. C KE is HIGH during refresh command period tRFC (MIN) else CKE is LOW. The IDD6

limit is actually a nomina l value and does not result in a fail value.

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Timing Diagrams

Figure 33: Initialize and Load Mode Register

Notes: 1. If CS is HIGH at clock high time, all commands applied are NOP.

2. The mode register may be loaded prior to the AUTO REFRESH cycles if desired.

3. JEDEC and PC100 specify three clocks.

4. Outputs are guaranteed High-Z after command is issued.

5. A12 should be a LOW at Tp + 1.

tCH

tCL

tCK

CKE

COMMAND

BA0, BA1 BANK

tRFC tMRD

tRFC

AUTO REFRESH AUTO REFRESH Program mode register

2, 3, 4

tCMH

tCMS

Precharge

all banks

()()

tRP

()()

tCKS

Power-up:

and

CLK stable

T = 100µs

MIN

PRECHARGE NOP AUTO

REFRESH NOP

LOAD MODE

()()

AUTO

REFRESH

ALL

BANKS

()()

High-Z

tCKH

()()

DQM/

DQML, DQMH

()()

()()()()

()()

NOP

()()

tCMH

tCMS tCMH

tCMS

A0–A9,

A11, A12 ROW

tAH

tAS

CODE

()()

A10 ROW

tAH

tAS

CODE

()()

ALL BANKS

SINGLE BANK

()()

Don’t Care

T0 T1 Tn + 1 To + 1 Tp + 1 Tp + 2 Tp + 3

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Timing Diagrams

Figure 34: Power-Down Mode

Note: Violating refresh requirements during power-down may result in a loss of data.

tCH

tCL

tCK

Two clock cycles

CKE

CLK

All banks idle, enter

power-down mode

Precharge all

active banks

Input buffers gated off while in

power-down mode

Exit power-down mode

()()

Don’t Care

tCKS tCKS

COMMAND

tCMH

tCMS

PRECHARGE NOP NOP ACTIVENOP

()()

All banks idle

BA0, BA1

BANK

BANK(S)

()()

High-Z

tAH

tAS

tCKH

tCKS

DQM/

DQML, DQMU

()()

A0–A9,

A11, A12

ROW

()()

ALL BANKS

SINGLE BANK

A10

ROW

()()

T0 T1 T2 Tn + 1 Tn + 2

()()

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Timing Diagrams

Figure 35: Clock Suspend Mode

Notes: 1. For this example, BL = 2, CL = 3, and auto precharge is disabled.

2. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”

tCH

tCL

tCK

tAC

tLZ

DQM/

DQML, DQMU

CLK

A0–A9,

A11, A12

BA0, BA1

A10

tOH

DOUT m

tAH

tAS

tAH

tAS

tAH

tAS

BANK

tDH

Din e

tAC tHZ

DOUT

+ 1

COMMAND

tCMH

tCMS

NOPNOP NOP NOPNOPREAD WRITE

Don’t Care

Undefined

CKE

tCKS tCKH

BANK

COLUMN m

tDS

Din + 1

NOP

tCKH

tCKS

tCMH

tCMS

COLUMN e

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

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Timing Diagrams

Figure 36: Auto-Refresh Mode

tCH

tCL

tCK

CKE

CLK

tRFC RFC

()()

tRP

()()

COMMAND

tCMH

tCMS

NOPNOP

()()

BANK

ACTIVE

AUTO

REFRESH

()()

NOPNOPPRECHARGE

Precharge all

active banks

AUTO

REFRESH

High-Z

BA0, BA1

BANK(S)

()()

tAH

tAS

tCKH

tCKS

()()

NOP

()()

DQM /

DQML, DQMH

A0–A9,

A11, A12

ROW

()()

ALL BANKS

SINGLE BANK

A10

ROW

()()

Don’t Care

T0 T1 T2 Tn + 1 To + 1

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Timing Diagrams

Figure 37: Self Refresh Mode

Notes: 1. No maximum time limit for self refresh; tRAS (MIN) applies to non-self refresh mode.

2. tXSR requires minimum of two clocks regardless of frequency or timing.

tCH

tCL

tCK

tRP

CKE

CLK

Enter self refresh mode

Precharge all

active banks

tXSR

CLK stable prior to exiting

self refresh mode

Exit self refresh mode

(Restart refresh time base)

()()()()

()()

Don’t Care

COMMAND

tCMH

tCMS

AUTO

REFRESH

PRECHARGE NOP NOP or COMMAND

INHIBIT

()()

BA0, BA1 BANK(S)

()()

High-Z

tCKS

AUTO

REFRESH

≥ tRAS(MIN)1

()()

tCKH

tCKS

DQM/

DQML, DQMU

()()

A0–A9,

A11,A12

()()

ALL BANKS

SINGLE BANK

A10

()()

T0 T1 T2 Tn + 1 To + 1 To + 2

()()

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Timing Diagrams

Figure 38: READ – Without Auto Precharge

Notes: 1. For this example, BL = 4, CL = 2, and the READ burst is followed by a “manual” PRECHARGE.

2. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”

ALL BANKS

tCH

tCL

tCK

tAC

tLZ tRP

tRAS

tRCD CAS Latency

tRC

DQM/

DQML, DQMU

CKE

CLK

A0–A9,

A11, A12

BA0, BA1

A10

tOH

DOUT m

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

BANK BANK BANK

ROW

BANK

tHZ

tOH

DOUT m + 3

tAC tOH

tAC

DOUT m + 2DOUT m + 1

COMMAND

tCMH

tCMS

PRECHARGENOPNOP NOPACTIVE NOP READ NOP ACTIVE

DISABLE AUTO PRECHARGE SINGLE BANK

Don’t Care

Undefined

tCKH

tCKS

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8

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Timing Diagrams

Figure 39: READ – With Auto Precharge

Notes: 1. For this example, BL = 4, and CL = 2.

2. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”

ENABLE AUTO PRECHARGE

tCH

tCL

tCK

tAC

tLZ tRP

tRAS

tRCD CAS Latency

tRC

DQM/

DQML, DQMU

CKE

CLK

A0–A9,

A11, A12

BA0, BA1

A10

tOH

OUT

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

BANK BANK

ROW

BANK

Don’t Care

Undefined

tHZ

tOH

OUT

m + 3

tAC tOH

tAC

OUT

m + 2D

OUT

m + 1

COMMAND

tCMH

tCMS

NOPNOP NOPACTIVE NOP READ NOP ACTIVENOP

tCKH

tCKS

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8

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Timing Diagrams

Figure 40: Single READ – Without Auto Precharge

Notes: 1. For this example, BL = 1, CL = 2, and the READ burst is followed by a “manual” PRECHARGE.

2. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”

ALL BANKS

tCH

tCL

tCK

tAC

tLZ tRP

tRAS

tRCD CAS Latency

tRC

tOH

OUT

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

BANK BANK(S) BANK

ROW

BANK

tHZ

tCMH

tCMS

NOPNOPNOP PRECHARGE

ACTIVE NOP READ ACTIVE NOP

DISABLE AUTO PRECHARGE SINGLE BANKS

Don’t Care

Undefined

COLUMN m2

tCKH

tCKS

T0 T1 T2 T3 T4 T5 T6 T7 T8

DQM/

DQML, DQMH

CKE

CLK

A0–A9,

A11, A12

BA0, BA1

A10

COMMAND

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Timing Diagrams

Figure 41: Single READ – With Auto Precharge

Notes: 1. For this example, BL = 1, and CL = 2.

2. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”

3. READ command is not allowe d else tRAS would be violated.

ENABLE AUTO PRECHARGE

tCH

tCL

tCK

tRP

tRAS

tRCD CAS Latency

tRC

DQM/

DQML, DQMH

CKE

CLK

A0–A9, A12

BA0, BA1

A10

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

BANK BANK

ROW

BANK

Don’t Care

Undefined

tHZ

tOH

OUT

tAC

COMMAND

tCMH

tCMS

NOP3READACTIVE NOP NOP3ACTIVENOP

tCKH

tCKS

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8

NOP NOP

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Timing Diagrams

Figure 42: Alternating Bank Read Accesses

Notes: 1. For this example, BL = 4, and CL = 2.

2. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”

ENABLE AUTO PRECHARGE

DQM/

DQML, DQMU

CLK

A0–A9,

A11, A12

BA0, BA1

A10

OUT

CMH

CMS

ROW

Don’t Care

Undefined

OUT

m + 3

AC t

OUT

m + 2 D

OUT

m + 1

COMMAND

CMH

CMS

NOP NOP ACTIVE NOP READ NOP ACTIVE

OUT

AC t

READ

ENABLE AUTO PRECHARGE

ROW

ACTIVE

ROW

BANK 0 BANK 0 BANK 3 BANK 3 BANK 0

CKE

CKH

CKS

COLUMN m

COLUMN b

T0 T1 T2 T4 T3 T5 T6 T7 T8

RP - BANK 0

RAS - BANK 0

RCD - BANK 0 t

RCD - BANK 0 CAS Latency - BANK 0

RCD - BANK 3 CAS Latency - BANK 3

RC - BANK 0

RRD

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Timing Diagrams

Figure 43: READ – Full-Page Burst

Notes: 1. For this example, CL = 2.

2. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”

3. Page left open; no tRP.

tCH

tCL tCK

tAC

tLZ

tRCD CAS Latency

DQM/

DQML, DQMH

CKE

CLK

A0–A9,

A11, A12

BA0, BA1

A10

tOH

DOUT

tCMH

tCMS

tAH

tAS

tAH

tAS

tAC tOH

DOUT

m+1

ROW

tHZ

tAC tOH

DOUT

tAC tOH

DOUT

m+2

tAC tOH

DOUT

m-1

tAC tOH

Dout m

Full-page burst does not self-terminate.

Can use BURST TERMINATE command.

()()

Full page completed

1,024 (x16) locations within same row

2,048 (x8) locations within same row

4,096 (x4) locations within same row

Don’t Care

Undefined

COMMAND

tCMH

tCMS

NOPNOP NOPACTIVE NOP READ NOP BURST TERMNOP NOP

()()

NOP

()()

tAH

tAS

BANK

()()

BANK

tCKH

tCKS

()()

COLUMN m

T0 T1 T2 T4T3 T5 T6 Tn + 1 Tn + 2 Tn + 3 Tn + 4

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Timing Diagrams

Figure 44: READ DQM Operation

Notes: 1. For this example, BL = 4, and CL = 2.

2. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”

tCH

tCL

tCK

tRCD CAS Latency

DQM/

DQML, DQMU

CKE

CLK

A0–A9,

A11, A12

BA0, BA1

A10

tCMS

ROW

BANK

ROW

BANK

Don’t Care

Undefined

tAC

OUT

tOH

OUT

m + 3D

OUT

m + 2

ttHZ LZ

tCMH

COMMAND

NOPNOP NOPACTIVE NOP READ NOPNOP NOP

tHZ

tAC tOH

tAH

tAS

tCMS tCMH

tAH

tAS

tAH

tAS

tCKH

tCKS

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8

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Timing Diagrams

Figure 45: WRITE – Without Auto Precharge

Notes: 1. For this example, BL = 4, and the WRITE burst is followed by a “manual” PRECHARGE.

2. 14ns to 15ns is required between <DIN m> and the PRECHARGE command, regardless of fre-

quency.

3. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”

DISABLE AUTO PRECHARGE

tCH

tCL

tCK

tRP

tRAS

tRCD

tRC

DQM/

DQML, DQMU

CKE

CLK

A0–A9,

A11, A12

BA0, BA1

A10

tCMH

tCMS

tAH

tAS

ROW

BANK BANK

ROW

BANK

Don’t Care

tDH

tDS

m + 1 D

m + 2 D

m + 3

COMMAND

tCMH

tCMS

NOPNOP NOPACTIVE NOP WRITE PRECHARGE

tAH

tAS

tAH

tAS

tDH

tDS tDH

tDS

SINGLE BANK

tCKH

tCKS

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8 T9

ROW

BANK

ROW

ACTIVE

NOP

ALL BANKs

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Timing Diagrams

Figure 46: WRITE – With Auto Precharge

Notes: 1. For this example, BL = 4.

2. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”

ENABLE AUTO PRECHARGE

tCH

tCL

tCK

tRP

tRAS

tRCD

tRC

DQM/

DQML, DQMH

CKE

CLK

A0–A9,

A11, A12

BA0, BA1

A10

tCMH

tCMS

tAH

tAS

ROW

BANK

ROW

BANK

tWR

Don’t Care

tDH

tDS

m + 1 D

m + 2 D

m + 3

COMMAND

tCMH

tCMS

NOPNOP

NOP

ACTIVE NOP WRITE

NOP ACTIVE

tAH

tAS

tAH

tAS

tDH

tDS tDH

tDS

tCKH

tCKS

NOP

COLUMN

T0 T1 T2 T4T3 T5 T6 T7 T8 T9

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Timing Diagrams

Figure 47: Single WRITE – Without Auto Precharge

Notes: 1. For this example, BL = 1, and the WRITE burst is followed by a “manual” PRECHARGE.

2. 14ns to 15ns is required between <DIN m> and the PRECHARGE command, regardless of fre-

quency.

3. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”

4. PRECHARGE command not allowed else tRAS would be violate d.

DISABLE AUTO PRECHARGE

tCH

tCL

tCK

tRP

tRAS

tRCD

tRC

DQM/

DQML, DQMU

CKE

CLK

A0–A9,

A11, A12

BA0, BA1

A10

tCMH

tCMS

tAH

tAS

ROW

BANK BANK

ROW

BANK

Don’t Care

tDH

tDS

m + 1 D

m + 2 D

m + 3

COMMAND

tCMH

tCMS

NOPNOP NOPACTIVE NOP WRITE PRECHARGE

tAH

tAS

tAH

tAS

tDH

tDS tDH

tDS

SINGLE BANK

tCKH

tCKS

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8 T9

ROW

BANK

ROW

ACTIVE

NOP

ALL BANKs

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Timing Diagrams

Figure 48: Single WRITE with Auto Precharge

Notes: 1. For this example, BL = 1, and the WRITE burst is followed by a “manual” PRECHARGE.

2. 14ns to 15ns is required between <DIN m> and the PRECHARGE command, regardless of fre-

quency.

3. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”

4. WRITE command not allowed else tRAS would be violated.

ENABLE AUTO PRECHARGE

tCH

tCL

tCK

tRP

tRAS

tRCD3

tRC

DQM/

DQML, DQMH

CKE

CLK

A0–A9,

A11, A12

BA0, BA1

A10

tCMH

tCMS

tAH

tAS

ROW

BANK BANK

ROW

BANK

tWR2

COMMAND

tCMH

tCMS

NOP4

NOP

ACTIVE NOP4

WRITE NOP

ACTIVE

tAH

tAS

tAH

tAS

tDH

tDS

tCKH

tCKS

NOP

COLUMN m3

T0 T1 T2 T4T3 T5 T6 T7 T8 T9

Don’t Care

Undefined

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Timing Diagrams

Figure 49: Alternating Bank WRITE Accesses

Notes: 1. For this example, BL = 4.

2. Requires one clock plus time (7ns to 7.5ns) with auto precharge or 14ns to 15ns

with PRECHARGE.

3. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”

tCH

tCL

tCK

CLK

Don’t Care

tDH

tDS

m + 1 D

m + 2 D

m + 3

COMMAND

tCMH

tCMS

NOP

ACTIVE NOP WRITE

NOP NOP ACTIVE

tDH

tDS tDH

tDS

ACTIVE WRITE

tDH

tDS

b + 1 D

b + 3

tDH

tDS tDH

tDS

ENABLE AUTO PRECHARGE

DQM/

DQML, DQMU

A0–A9,

A11, A12

BA0, BA1

A10

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

ENABLE AUTO PRECHARGE

ROW

BANK 0 BANK 0 BANK 1

BANK 0

BANK 1

CKE

tCKH

tCKS

b + 2

tDH

tDS

COLUMN b

COLUMN m

tRP - BANK 0

tRAS - BANK 0

tRCD - BANK 0 t

RCD - BANK 0

tWR - BANK 0

WR - BANK 1

tRCD - BANK 1

tRC - BANK 0

RRD

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

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Timing Diagrams

Figure 50: WRITE – Full-Page Burst

Notes: 1. x16: A11 and A12 = “Don’t Care”; x8: A12 = “Don’t Care.”

2. tWR must be sati sf ied prior to PRECHARGE command.

3. Page left open; no tRP.

tCH

tCL tCK

tRCD

DQM/

DQML, DQMH

CKE

CLK

A0–A9,

A11, A12

BA0, BA1

A10

tCMS

tAH

tAS

tAH

tAS

ROW

Full-page burst does

not self-terminate.

Can use BURST TERMINATE

command to stop.2, 3

()()

Full page completed Don’t Care

COMMAND

tCMH

tCMS

NOPNOP NOPACTIVE NOP WRITE BURST TERMNOP NOP

()()

DQ DIN m

tDH

tDS

DIN m + 1 DIN m + 2 DIN m + 3

tDH

tDS tDH

tDS

DIN m - 1

tDH

tDS

tAH

tAS

BANK

()()

BANK

tCMH

tCKH

tCKS

()()

1,024 (x16) locations within same row

2,048 (x8) locations within same row

4,096 (x4) locations within same row

COLUMN

T0 T1 T2 T3 T4 T5 Tn + 1 Tn + 2 Tn + 3

()()

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Timing Diagrams

Figure 51: WRITE – DQM Operation

Notes: 1. For this example, BL = 4.

2. x16: A11 and A12 = “Don’t Care;” x8: A12 = “Don’t Care.”

tCH

tCL

tCK

tRCD

DQM/

DQML, DQMU

CKE

CLK

A0–A9,

A11, A12

BA0, BA1

A10

tCMS

tAH

tAS

ROW

BANK

ROW

BANK

ENABLE AUTO PRECHARGE

DIN m + 3

tDH

tDS

DIN mDIN m + 2

tCMH

COMMAND

NOPNOP

NOP

ACTIVE NOP WRITE

NOPNOP

DON’T CARE

tCMS tCMH

tDH

tDS

tDH

tDS

tAH

tAS

tAH

tAS

DISABLE AUTO PRECHARGE

tCKH

tCKS

COLUMN m

T0 T1 T2 T3 T4 T5 T6 T7

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

prodmktg@micron.com www.micron.com Customer Commen t Line: 800-932- 4992

Micron, the M logo, and the Micron logo are trademarks of Micron Technology , Inc. All other trademarks ar e the property of

their respective owners.

This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range

set forth herein. Although consider ed final, th es e specificat i o ns a re subject to change, as further product development and

data characterization sometimes occur.

512Mb: x4, x8, x16 SDRAM

Package Dimensions

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Package Dimensions

Figure 52: 54-Pin Plastic TSOP (400 mil)

Notes: 1. All dimensions in millimeters.

2. Package width and length do not include mold protrusion; allowable mol d protru sio n is

0.25mm per side.

SEE DETAIL A

0.80 TYP 0.71

10.16 ±0.08

0.50 ±0.10

PIN #1 ID

DETAIL A

22.22 ±0.08

0.375 ±0.075

1.2 MAX

0.10

0.25

11.76 ±0.20

0.80

TYP

0.15 +0.03

–0.02

0.10 +0.10

–0.05

GAGE PLANE

PLASTIC PACKAGE MATERIAL: EPOXY NOVOLAC

LEAD FINISH: TIN/LEAD PLATE

PACKAGE WIDTH AND LENGTH DO NOT INCLUDE

MOLD PROTRUSION. ALLOWABLE PROTRUSION

IS 0.25 PER SIDE.