HM514170C Series
HM51S4170C Series
262,144-word × 16-bit Dynamic Random Access Memory
Rev. 1.0
Jul. 21, 1995
Description
The Hitachi HM51(S)4170C are CMOS dynamic RAM organized as 262,144-word × 16-bit.
HM51(S)4170C have realized higher density, higher performance and various functions by employing 0.8
µm CMOS process technology and some new CMOS circuit design technologies. The HM51(S)4170C
offer fast page mode as a high speed access mode. Multiplexed address input permits the
HM51(S)4170C to be packaged in standard 400-mil 40-pin plastic SOJ and standard 400-mil 44-pin
plastic TSOPII. Internal refresh timer enables HM51S4170C self refresh operation.
Features
• Single 5 V (±10%)
• High speed
— Access time: 70 ns/80 ns (max)
• Low power dissipation
— Active mode: 660 mW/578 mW (max)
— Standby mode: 11 mW (max)
1.1 mW (max) (L-version)
• Fast page mode capability
• 1024 refresh cycles:16 ms
128 ms (L-version)
•2
WE
-byte control
• 2 variations of refresh
—
RAS
-only refresh
—
CAS
-before-
RAS
refresh
• Battery backup operation (L-version)
• Self refresh operation (HM51S4170C)
HM514170C, HM51S4170C Series
2
Ordering Information
Type No. Access Time Package
HM514170CJ-7
HM514170CJ-8 70 ns
80 ns 400-mil 40-pin plastic SOJ (CP-40DA)
HM514170CLJ-7
HM514170CLJ-8 70 ns
80 ns
HM51S4170CJ-7
HM51S4170CJ-8 70 ns
80 ns
HM51S4170CLJ-7
HM51S4170CLJ-8 70 ns
80 ns
HM514170CTT-7
HM514170CTT-8 70 ns
80 ns 400-mil 44-pin plastic TSOPII (TTP-44/40DB)
HM514170CLTT-7
HM514170CLTT-8 70 ns
80 ns
HM51S4170CTT-7
HM51S4170CTT-8 70 ns
80 ns
HM51S4170CLTT-7
HM51S4170CLTT-8 70 ns
80 ns
HM514170C, HM51S4170C Series
3
Pin Arrangement
V
I/O0
I/O1
I/O2
I/O3
V
I/O4
I/O5
I/O6
I/O7
NC
LWE
UWE
RAS
A9
A0
A1
A2
A3
V
CC
CC
CC
V
I/O15
I/O14
I/O13
I/O12
V
I/O11
I/O10
I/O9
I/O8
NC
NC
CAS
OE
A8
A7
A6
A5
A4
V
SS
SS
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
I/O0
I/O1
I/O2
I/O3
V
I/O4
I/O5
I/O6
I/O7
NC
LWE
UWE
RAS
A9
A0
A1
A2
A3
V
CC
CC
CC
V
I/O15
I/O14
I/O13
I/O12
V
I/O11
I/O10
I/O9
I/O8
NC
NC
CAS
OE
A8
A7
A6
A5
A4
V
SS
SS
SS
1
2
3
4
5
6
7
8
9
10
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
32
31
30
29
28
27
26
25
24
23
(Top view)
(Top view)
HM514170CJ/CLJ Series
HM51S4170CJ/CLJ Series HM514170CTT/CLTT Series
HM51S4170CTT/CLTT Series
Pin Description
Pin Name Function
A0 – A9 Address input
– Row address A0 – A9
– Column address A0 – A7
– Refresh address A0 – A9
I/O0 – I/O15 Data-in/data-out
RAS Row address strobe
CAS Column address strobe
UWE / LWE Read/write enable
OE Output enable
VCC Power (+5 V)
VSS Ground
NC No connection
HM514170C, HM51S4170C Series
4
Block Diagram
256 k Memory Array Mat
I/O Bus & Column Decoder
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
I/O Bus & Column Decoder
Peripheral Circuit
I/O Bus & Column Decoder
I/O Bus & Column Decoder
256 k Memory Array Mat
I/O Bus & Column Decoder
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
I/O Bus & Column Decoder
Peripheral Circuit
I/O Bus & Column Decoder
I/O Bus & Column Decoder
Row
Decoder Row
Decoder
Row
Decoder Row
Decoder Row
Decoder Row
Decoder
Row
Decoder Row
Decoder
Selector Selector Selector Selector
Peripheral Circuit
UWE
RAS
OE
I/O12
Buffer
I/O13
Buffer
I/O14
Buffer
I/O15
Buffer
I/O0
Buffer
I/O1
Buffer
Selector Selector Selector Selector
I/O2
Buffer
I/O3
Buffer
I/O4
Buffer I/O12
I/O13
I/O14I/O15
I/O0I/O1I/O2I/O3
I/O4
Address A0,A1,A2,A3 Address A4,A5 A6,A7,A8
Row
Decoder Row
Decoder
Row
Decoder Row
Decoder Row
Decoder Row
Decoder
Row
Decoder Row
Decoder
I/O5
Buffer
I/O5
I/O6
Buffer
I/O6
I/O7
Buffer
I/O7
I/O11
I/O10
I/O9
I/O8
I/O11
Buffer
I/O10
Buffer
I/O9
Buffer
I/O8
Buffer
CAS
LWE
A9
Operation Mode
The HM51(S)4170C series has the following 11 operation modes.
HM514170C, HM51S4170C Series
5
1. Read cycle
2. Early write cycle
3. Delayed write cycle
4. Read-modify-write cycle
5.
RAS
-only refresh cycle
6.
CAS
-before-
RAS
refresh cycle
7. Self refresh cycle (HM51S4170C)
8. Fast page mode read cycle
9. Fast page mode early write cycle
10. Fast page mode delayed write cycle
11.Fast page mode read-modify-write cycle
Inputs
RAS CAS UWE LWE Output Operation
H H D D Open Standby
H L H H Valid Standby
L L H H Valid Read cycle
LLL
*2 L*2 Open Early write cycle
LLL
*2 L*2 Undefined Delayed write cycle
L L H to L H to L Valid Read-modify-write cycle
L H D D Open RAS-only refresh cycle
H to L L D D Open CAS-before-RAS refresh cycle
Self refresh cycle (HM51S4170C)
L H to L H H Valid Fast page mode read cycle
L H to L L*2 L*2 Open Fast page mode early write cycle
L H to L L*2 L*2 Undefined Fast page mode delayed write cycle
L H to L H to L H to L Valid Fast page mode read modify-write cycle
Notes: 1. H: High (inactive) L: Low (active) D: H or L
2. tWCS ≥ 0 ns Early write cycle
tWCS < 0 ns Delay write cycle
3. Mode is determined by the OR function of the UWE and LWE. (Mode is set by the earliest of
UWE and LWE active edge and reset by the latest of UWE and LWE inactive edge.) However
write OPERATION and output HIZ control are done independently by each UWE, LWE.
HM514170C, HM51S4170C Series
6
Absolute Maximum Ratings
Parameter Symbol Value Unit
Voltage on any pin relative to VSS VT–1.0 to +7.0 V
Supply voltage relative to VSS VCC –1.0 to +7.0 V
Short circuit output current Iout 50 mA
Power dissipation PT1.0 W
Operating temperature Topr 0 to +70 °C
Storage temperature Tstg –55 to +125 °C
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter Symbol Min Typ Max Unit Note
Supply voltage VSS 000V2
V
CC 4.5 5.0 5.5 V 1, 2
Input high voltage VIH 2.4 —6.5 V 1
Input low voltage VIL –1.0 —0.8 V 1
Notes: 1. All voltage referred to VSS
2. The supply voltage with all VCC pins must be on the same level.
The supply voltage with all VSS pins must be on the same level.
DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V)
HM514170C, HM51S4170C
-7 -8
Parameter Symbol Min Max Min Max Unit Test Conditions
Operating current*1, *2 ICC1 —120 —105 mA RAS, CAS cycling
tRC = min
Standby current ICC2 —2—2 mA TTL interface
RAS, CAS = VIH
Dout = High-Z
—1—1 mA CMOS interface
RAS, CAS, UWE, LWE, OE ≥
VCC – 0.2 V
Dout = High-Z
Standby current
(L-version) ICC2 —200 —200 µA CMOS interface
RAS, CAS, OE, UWE, LWE ≥
VCC – 0.2 V
Dout = High
RAS-only refresh current*2 ICC3 —120 —100 mA tRC = min
HM514170C, HM51S4170C Series
7
DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V) (cont)
HM514170C, HM51S4170C
-7 -8
Parameter Symbol Min Max Min Max Unit Test Conditions
Standby current*1 ICC5 —5—5mARAS = VIH, CAS = VIL
Dout = enable
CAS-before-RAS refresh
current*2 ICC6 —120 —100 mA tRC = min
Fast page mode current*1, *3 ICC7 —130 —120 mA tPC = min
Battery backup current*4
(Standby with CBR refresh)
(L-version)
ICC10 —300 —300 µA Standby: CMOS interface
Dout = High-Z
CBR refresh: tRC = 125 µs
tRAS ≤ 1 µs, CAS = VIL
UWE, LWE, OE = VIH
Self-refresh mode current
(HM51S4170C) ICC11 —1—1 mA CMOS interface
RAS, CAS ≤ 0.2 V,
Dout = High-Z
Self-refresh mode current
(HM51S4170CL) ICC11 —200 —200 µA CMOS interface
RAS, CAS ≤ 0.2 V,
Dout = High-Z
Input leakage current ILI –10 10 –10 10 µA 0 V ≤ Vin ≤ 6.5 V
Output leakage current ILO –10 10 –10 10 µA 0 V ≤ Vout ≤ 6.5 V
Dout = disable
Output high voltage VOH 2.4 VCC 2.4 VCC V High Iout = –5.0 mA
Output low voltage VOL 0 0.4 0 0.4 V Low Iout = 4.2 mA
Notes: 1. ICC depends on output load condition when the device is selected. ICC max is specified at the
output open condition.
2. Address can be changed once or less while RAS = VIL.
3. Address can be changed once or less while CAS = VIH.
4. VIH ≥ VCC – 0.2 V, 0 ≤ VIL ≤ 0.2 V, Address can be changed once or less while RAS = VIL
5. All the VCC pins shall be supplied with the same voltage. And all the VSS pins shall be supplied
with the same voltage.
Capacitance (Ta = 25°C, VCC = 5 V ± 10%)
Parameter Symbol Typ Max Unit Notes
Input capacitance (Address) CI1 —5pF1
Input capacitance (Clocks) CI2 —7pF1
Output capacitance (Data-in, Data-out) CI/O —10 pF 1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. CAS = VIH to disable Dout.
HM514170C, HM51S4170C Series
8
AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V)*1, *14, *15, *17, *18
Test Conditions
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)
•Input rise and fall time: 5 ns
•Input timing reference levels: 0.8 V, 2.4 V
•Input levels: 0 V, 3 V
•Output load: 2 TTL gate + CL (100 pF) (Including scope and jig)
HM514170C, HM51S4170C
-7 -8
Parameter Symbol Min Max Min Max Unit Notes
Random read or write cycle time tRC 130 —150 —ns
RAS precharge time tRP 50 —60 —ns
RAS pulse width tRAS 70 10000 80 10000 ns
CAS pulse width tCAS 20 10000 20 10000 ns 22
Row address setup time tASR 0—0—ns
Row address hold time tRAH 10 —10 —ns
Column address setup time tASC 0—0—ns
Column address hold time tCAH 15 —15 —ns
RAS to CAS delay time tRCD 20 50 20 60 ns 8
RAS to column address delay time tRAD 15 35 15 40 ns 9
RAS hold time tRSH 20 —20 —ns
CAS hold time tCSH 70 —80 —ns
CAS to RAS precharge time tCRP 15 —15 —ns 23
OE to Din delay time tODD 20 —20 —ns
OE delay time from Din tDZO 0—0—ns
CAS setup time from Din tDZC 0—0—ns
Transition time (rise and fall) tT3 50 3 50 ns 7
Refresh period tREF —16 —16 ms
Refresh period (L-version) tREF —128 —128 ms
HM514170C, HM51S4170C Series
9
Read Cycle
HM514170C, HM51S4170C
-7 -8
Parameter Symbol Min Max Min Max Unit Notes
Access time from RAS tRAC —70 —80 ns 2, 3
Access time from CAS tCAC —20 —20 ns 3, 4, 13
Access time from address tAA —35 —40 ns 3, 5, 13
Access time from OE tOAC —20 —20 ns 22
Read command setup time tRCS 0—0—ns 20
Read command hold time to CAS tRCH 0—0—ns 16, 19
Read command hold time to RAS tRRH 0—0—ns 16
Column address to RAS lead time tRAL 35 —40 —ns
Output buffer turn-off time tOFF1 0 15 0 15 ns 6
Output buffer turn-off to OE tOFF2 0 15 0 15 ns 6
CAS to Din delay time tCDD 15 —15 —ns
Write Cycle
HM514170C, HM51S4170C
-7 -8
Parameter Symbol Min Max Min Max Unit Notes
Write command setup time tWCS 0—0—ns 10, 19
Write command hold time tWCH 15 —15 —ns 20
Write command pulse width tWP 10 —10 —ns 21
Write command to RAS lead time tRWL 20 —20 —ns 21
Write command to CAS lead time tCWL 20 —20 —ns 21
Data-in setup time tDS 0—0—ns 11, 21
Data-in hold time tDH 15 —15 —ns 11, 21
CAS to OE delay time tCOD —0—0ns22
HM514170C, HM51S4170C Series
10
Read-Modify-Write Cycle
HM514170C, HM51S4170C
-7 -8
Parameter Symbol Min Max Min Max Unit Notes
Read-modify-write cycle time tRWC 180 —200 —ns
RAS to WE delay time tRWD 95 —105 —ns 10, 19
CAS to WE delay time tCWD 45 —45 —ns 10, 19
Column address to WE delay time tAWD 60 —65 —ns 10, 19
OE hold time from WE tOEH 20 —20 —ns 21
Refresh Cycle
HM514170C, HM51S4170C
-7 -8
Parameter Symbol Min Max Min Max Unit Notes
CAS setup time (CBR refresh cycle) tCSR 10 —10 —ns 19
CAS hold time (CBR refresh cycle) tCHR 10 —10 —ns 20
RAS precharge to CAS hold time tRPC 10 —10 —ns 19
CAS precharge time in normal mode tCPN 10 —10 —ns
Fast Page Mode Cycle
HM514170C, HM51S4170C
-7 -8
Parameter Symbol Min Max Min Max Unit Notes
Fast page mode cycle time tPC 45 —50 —ns
Fast page mode CAS precharge time tCP 10 —10 —ns
Fast page mode RAS pulse width tRASC —100000 —100000 ns 12
Access time from CAS precharge tACP —40 —45 ns 3, 13
RAS hold time from CAS precharge tRHCP 40 —45 —ns
Fast page mode read-modify-write cycle CAS
precharge to UWE, LWE delay time tCPW 65 —70 —ns 21
Fast page mode read-modify-write cycle time tPCM 95 —100 —ns
HM514170C, HM51S4170C Series
11
Self refresh Mode
HM51S4170C
-7 -8
Parameter Symbol Min Max Min Max Unit Notes
RAS pulse width (self refresh) tRASS 100 —100 —µs 23, 24,
25
RAS precharge time (self refresh) tRPS 130 —150 —ns
CAS hold time (self refresh) tCHS –50 —–50 —ns
Notes: 1. AC measurements assume tT = 5 ns.
2. Assumes that tRCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF.
4. Assumes that tRCD ≥ tRCD (max) and tRAD ≤ tRAD (max).
5. Assumes that tRCD ≤ tRCD (max) and tRAD ≥ tRAD (max).
6. tOFF (max) defines the time at which the output achieves the open circuit condition and is not
referred to output voltage levels.
7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also,
transition times are measured between VIH and VIL.
8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as
a reference point only, if tRCD is greater than the specified tRCD (max) limit, then access time is
controlled exclusively by tCAC.
9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as
a reference point only, if tRAD is greater than the specified tRAD (max) limit, then access time is
controlled exclusively by tAA.
10.tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data
sheet as electrical characteristics only: if tWCS ≥ tWCS (min), the cycle is an early write cycle and
the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD ≥
tRWD (min), tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW ≥ tCPW (min), the cycle is a read-modify-
write and the data output will contain data read from the selected cell; if neither of the above
sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate.
11.These parameters are referred to CAS leading edge in an early write cycle and to WE leading
edge in a delayed write or a read-modify-write cycle.
12.tRASC defines RAS pulse width in fast page mode cycles.
13.Access time is determined by the longer of tAA or tCAC or tACP.
14.After power up pause for 100 µs, then DRAM initialization requires a minimum of eight RAS
only refresh or eight CAS-before-RAS refresh cycles. If the user will implement CAS-before-
RAS timing in their system, then the eight initialization cycles MUST be CAS-before-RAS
cycles
15.In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying
data to the device.
16.Either tRCH or tRRH must be satisfied for a read cycle.
17.The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS
pins must be on the same level.
18.A word of data can be written only when UWE and LWE go low at the same time. This implies
that early write cycles cannot be combined with delayed write cycles in the same cycles
because all data is latched at the fall of the first WE. In other words, staggering the WE signals
in one cycle is not permitted.
19.tRCH, tRRH, tWCS, tRWD, tCWD and tAWD are determined by the earlier falling edge of UWE and LWE.
20.tWCH and tRCS are determined by the later rising edge of UWE or LWE.
21.tWP, tRWL, tCWL, tOEH, tDS, tDH and tCPW should be satisfied by both UWE and LWE.
HM514170C, HM51S4170C Series
12
22.When out put buffers are enabled once, sustain the low impedance state until valid data is
obtained. When output buffer is turned on and off within a very short time, generally it causes
large VCC/VSS line noise, which causes to degrade VIH (min)/VIL(max) level.
23.If you use distributed CBR refresh mode with 15.6 µs interval in normal read/write cycle, CBR
refresh should be executed within 15.6 µs immediately after exiting from and before entering
into self refresh mode.
24.If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 1024 cycles
of distributed CBR refresh with 15.6 µs interval should be executed within 16 ms immediately
after exiting from and before entering into the self refresh mode.
25.Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from
self refresh mode, all memory cells need to be refreshed before re-entering the self refresh
mode again.
26. H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max))
Invalid Dout
HM514170C, HM51S4170C Series
13
Notes concerning 2
WE
control
Please do not separate the
UWE
/
LWE
operation timing intentionally. However skew between
UWE
/
LWE
are allowed under the following conditions.
(1) Each of the
UWE
/
LWE
should satisfy the timing specifications individually.
(2) Different operation mode for upper/lower byte is not allowed; such as following.
RAS
CAS
LWE
UWE
Delayed write
Early write
(3) Closely separated upper/lower byte control is not allowed. Unless the condition (tCP ≤ tUL) is satisfied.
RAS
LWE
UWE
tUL
HM514170C, HM51S4170C Series
14
Timing Waveforms *26
Read Cycle
RAS
Address
UWE
LWE
Dout
tRAS
tRC
tRP
tCSH
tRCD
tRSH
tCAS
tRAL
tCAH
tRAD
t
tASR
RAH tASC
tRCS tRCH
tRRH
tCAC tOFF1
tAA
tRAC
tTtCRP
Row Column
Dout
Din
OE
High-Z
DZC
t
High-Z
DZO
t
tOAC tCDD
tOFF2
tODD
CAS
HM514170C, HM51S4170C Series
15
Early Write Cycle
RAS
Address
Din
Dout
*
tRAS
tRP
tRC
tCSH
tCRP
tRCD
tRSH
tCAS
tT
tCAH
tASC
tRAH
tASR
Row Column
tWCS
tDS tDH
Din
High-Z
tWCH
*OE : H or L
UWE
LWE
CAS
HM514170C, HM51S4170C Series
16
Delayed Write Cycle
Address
RAS
Din
Dout
tRAS
tRC tRP
tCSH tCRP
tRCD tRSH
tCAS
tASR
tRAH
tASC
tCAH
Row Column
tRCS tWP
tRWL
tCWL
tDS
tDH
Din
tODD
tOFF2
tT
* Do not enable Dout during delayed write cycle.
OE
tDZC
tDZO
tOEH
*
tCOD
UWE
LWE
CAS
Invalid Dout*
High-Z
Read-Modify-Write Cycle
HM514170C, HM51S4170C Series
17
Din
Dout
Address
RAS
tRWC tRP
tCRP
tT
tRCD
tRAD
tASR
tRAH tCAH
tASC
Row Column
tCWD
tRCS
tAWD
tRWD
tWP
tCWL
tRWL
tDS
tDH
Din
tODD
tAA
tOFF2
tOEH
tRAC
OE
Dout
tDZO
tOAC
High-Z
tDZC
tCAC
UWE
LWE
CAS
High-Z
HM514170C, HM51S4170C Series
18
RAS
-Only Refresh Cycle
Address
Dout
*: H or L
** UWE, LWE and OE
tRC
tRAS tRP
tT
tCRP tRPC
tCRP
tASR
tRAH
Row
High-Z
Refresh address : A0 – A9 (AX0 – AX9)
CAS
RAS
HM514170C, HM51S4170C Series
19
CAS
-Before-
RAS
Refresh Cycle
RAS
Address
Dout
tRC tRC
tRP tRAS tRP tRAS tRP
tRPC
tT
tCPN tCSR tCHR tCPN tCSR
tRPC tCHR
tCRP
tOFF1
High-Z
*UWE, LWE
CAS
** **
** Do not extend tRAS ≥ tRAS (max).
Untested self refresh mode may be activated and loss of data may be resulted.
(HM514170C)
: H or L
HM514170C, HM51S4170C Series
20
Fast Page Mode Read Cycle
RAS
Address
UWE
LWE
Din
Dout
tRASC tRP
tTtCSH tPC tRSH tCRP
tCAS
tCP
tCAS
tCP
tCAS
tRCD
tASR tRAH tASC tCAH tASC tCAH tCAH
Row Column Column Column
tRAC
tRCH
tRRH
tAA
tCDD
tODD
High-Z
tRCS tRCH tRCS
tDZC
tRCS
tCDD
OE
tRHCP
tRAD tRAL
Dout Dout Dout
tCDD
tODD
tDZO tOFF2
tOAC
tOAC
tODD
tDZO
DZC
ttOFF2
tOAC
tOFF1
tAA
tCAC
tACP
tDZO
tACP
tAA
tCAC
tOFF1
tOFF1
tCAC
t
High-Z
High-Z
tDZC
tASC
tRCH
CAS
OFF2
High-Z
HM514170C, HM51S4170C Series
21
Fast Page Mode Early Write Cycle
RAS
Address
Din
Dout
tRASC tRP
tTtCSH tPC tRSH
tCRP
tCAS
tCP
tCAS
tCP
tCAS
tRCD
tASR tRAH tASC tCAH tASC tCAH tASC tCAH
Row Column Column Column
tDS tDH tDS tDH
tDS tDH
Din Din Din
High-Z
tWCS tWCH
*OE
t
WCH
tWCS
tWCS tWCH
UWE
LWE
CAS
: H or L
HM514170C, HM51S4170C Series
22
Fast Page Mode Delayed Write Cycle
Din
Address
RAS
Dout
tRASC tRP
tT tCSH tPC tRSH
tCAS
tRCD tCP tCAS tCP tCAS tCRP
tASR
tRAH
tASC
tCAH tASC
tCAH tASC tCAH
Row
Column Column
tWP
tRCS
tRCS
tCWL
t
tCWL
tCWL t
tDS
tDH tDS tDS
tDH
Din Din Din
OE
tODD
tOEH
tDH
High-Z
tWP
tRCS
RWL
WP
UWE
LWE
CAS
Column
HM514170C, HM51S4170C Series
23
Fast Page Mode Read-Modify-Write Cycle
Din
Dout
Address
RAS
tRASC
t
tCP
tPCM
tT
tRCD
t
tCP
tRAD
tASR tASC tt
tRAH
t
tCAH
t
tCPW
t
t
CPW
tCWL
t
RWD
tAWD tAWD tAWD
tCWD
t
tCWD
tCWD
tRCS tWP
t
tWP
tDS
t
tDH
t
tDS
tDZC tDH
tODD
tDH
tCAC
tDZO
tOEH tOEH tOEH
tAA
t
Din Din Din
tRP
tRWL
tOAC
tODD
t
tODD
tDZO
t
t
tDZO
AA
t
UWE
LWE
OE
Dout
Dout
Dout
tCAH
tDS
Column
Column
Column
Row
RAC
CWL
High-Z
CAC
ACP
WP
CWL
CAC
t
CRP
ASC
ACP
CAH
t
ASC
RCS
High-Z High-Z
OAC
t
DZC DZC
RCS
OAC
CAS
tOFF2 tOFF2 tOFF2
High-Z
HM514170C, HM51S4170C Series
24
Self Refresh Cycle
RAS
Address
Dout
tRP tRASS tRPS
tRPC
tT
tCPN tCSR tCHS
tCRP
tOFF1
High-Z
*
CAS
UWE, LWE and OE : H or L
The low self refresh current is achieved by introducing extremely long internal refresh
cycle. Therefore some care needs to be taken on the refresh.
1. Please do not use tRASS timing, 10 µs ≤ tRASS ≤ 100 µs. During this period, the
device is in transition state from normal operation mode to self refresh mode. If
tRASS ≥ 100 µs, then RAS precharge time should use tRPS instead of tRP.
2. If you use RAS only refresh or CBR burst refresh mode in normal read/write
cycle, 1024 cycles of distributed CBR refresh with 15.6 µs interval should be
executed within 16 ms immediately after exiting from and before entering into the
self refresh mode.
3. If you use distributed CBR refresh mode with 15.6 µs interval in normal read/write
cycle, CBR refresh should be executed within 15.6 µs immediately after exiting
from and before entering into self refresh mode.
4. Repetitive self refresh mode without refreshing all memory is not allowed. Once
you exit from self-refresh mode, all memory cells need to be refreshed before re-
entering the self refresh mode again.
HM514170C, HM51S4170C Series
25
Package Dimensions
HM51(S)4170CJ/CLJ Series (CP-40DA) Unit: mm
9.40 ± 0.25
120
0.43 ± 0.10
3.50 ± 0.26
21
40 26.16 Max
25.80
0.74
10.16 ± 0.13
11.18 ± 0.13
1.30 Max
2.85 ± 0.12
0.10
0.80 +0.25
–0.17
1.27
HM514170C, HM51S4170C Series
26
HM51(S)4170CTT/CLTT Series (TTP-44/40DB) Unit: mm
0.13 M
0.80
44 23
122
18.41
18.81 Max
0.27 ± 0.07
1.20 Max
10.16
11.76 ± 0.20
0 – 5°
0.145 +0.075
–0.025
1.005 Max
10 13
3235
0.10
0.50 ± 0.10
0.68
0.80
0.13 ± 0.05